Abstract: A system, method, and computer program product are provided for scheduling interruptible hatches of instructions for execution by one or more functional units of a processor. The method includes the steps of receiving a batch of instructions that includes a plurality of instructions and dispatching at least one instruction from the batch of instructions to one or more functional units for execution. The method further includes the step of receiving an interrupt request that causes an interrupt routine to be dispatched to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units. When the interrupt request is received, the method further includes the step of storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.

Abstract: A method for detecting malware includes the steps of identifying a one or more open network connections of an electronic device, associating one or more executable objects on the electronic device with the one or more open network connections of the electronic device, determining the address of a first network destination that is connected to the open network connections of the electronic device, receiving an evaluation of the first network destination, and identifying one or more of the executable objects as malware executable objects. The evaluation includes an indication that the first network destination is associated with malware. The malware executable objects includes the executable objects that are associated with the open network connections that are connected to the first network destination.

Abstract: A network access method, an authentication method, a communications system, and relevant devices are provided. The authentication method includes: receiving a request message sent from an Access Node (AN), wherein the request message carries subscriber line information and a Link-Local Address (LLA); sending an access request to an Authentication, Authorization and Accounting (AAA) server according to the subscriber line information; receiving an authentication result indicating the authentication is successful; determining whether an address matching the LLA carried in the request has been stored in the BNG; and storing the LLA in the BNG, if the address matching the LLA is not stored in the BNG.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for storing and transferring messages. An example method includes providing a queue having an ordered plurality of storage blocks. Each storage block stores one or more respective messages and is associated with a respective time. The times increase from a block designating a head of the queue to a block designating a tail of the queue. The method also includes reading, by each of a plurality of first sender processes, messages from one or more blocks in the queue beginning at the head of the queue. The read messages are sent, by each of the plurality of first sender processes, to a respective recipient. One or more of the blocks are designated as old when they have associated times that are earlier than a first time. A block is designated as a new head of the queue when the block is associated with a time later than or equal to the first time.

Abstract: A first device starts to transfer memory data related to a virtual machine running on the first device to a second device connected to the first device via a switch device. When an accumulated amount of transferred memory data exceeds a first threshold, the first device stops packet transmission performed by the virtual machine and transmits a prior shut-down notice to the second device. The first device shuts down the virtual machine when the accumulated amount exceeds a second threshold. The second device transmits, upon receiving the prior shut-down notice, a first control message to the switch device and the first device and causes a virtual network interface to start reception of packets destined for the virtual machine. When the memory transfer is completed, the second device starts up the virtual machine to start the packet transmission and outputs packets held in the virtual network interface to the virtual machine.

Abstract: A portable data terminal including a processor having an instruction set architecture and data storage means configured to store a plurality of operating systems and a virtual machine monitor application program configured to receive at least one instruction from each operating system, communicate with the processor according to the instruction set architecture, and switch operating system access to the processor upon receipt of an electrical signal representing an event.

Abstract: In an embodiment, a processor may be configured to dynamically infer one or more attributes of input and/or output registers of an instruction, given the attributes corresponding to at least one input registers. The inference may be made at the issue circuit/stage of the processor, for those registers that do not have attribute information at the issue circuit/stage. In an embodiment, the processor may also include a register attribute tracker configured to track attributes of registers prior to the issue stage of the processor pipeline. The processor may feed back, to the register attribute tracker, inferred attributes and the register addresses of the registers to which the inferred attributes apply. The register attribute tracker may be configured to may associate the inferred attribute with the identified register attribute tracker may also be configured to infer input register attributes from other input register attributes.

Abstract: A concurrent data structure allows synchronization to be elided for read accesses. Processing resources that remove one or more elements of the concurrent data structure are allowed to delete the elements only after all other processing resources have reached a safe point. Each processing resource maintains an indicator that indicates whether the processing resource has reached as safe point (i.e., will not access the concurrent data structure). When the indicators indicate that all processing resources have reached a safe point, elements of the data structure may be deleted.

Abstract: A simulation apparatus includes: operations of: dividing code of a program in a target processor into blocks; setting an execution result of an externally-dependant instruction depending on an external environment as a prediction result; carrying out function simulation based on the prediction result; calculating an execution time of the externally-dependant instruction according to instruction execution timing information and a function simulation result; generating host code which makes a host processor execute performance simulation based on the function simulation result: correcting the execution time of the externally-dependant instruction based on a delay time of the externally-dependent instruction and a execution time of an instruction executed before or after the externally-dependent function if an execution result of the externally-dependent function when the host processor executes the host code differs from the prediction result; and setting a corrected execution time of the external-dependent ins

Abstract: The present application is directed to methods and systems for redirecting write requests issued by trusted applications to a secure storage. Upon redirecting the write requests, the data included in those requests can be stored in the secure storage area of a client computer. In some embodiments, the methods and systems can include determining whether an application issuing the request is a trusted application that requires data to be stored in a secure storage repository. Upon making this determination, a filter driver can identify a secure storage area on a client computer and can redirect the write request to this secure storage. In other embodiments, the filter driver may deny requests of trusted applications to write to unsecure storage areas.

Abstract: A rollback record may be created for each step identifier (ID). The rollback record indicates how many times the step record identified by the step ID has been rolled back during operation of the database. The rollback record may be stored in a periodic save record (PSR), separate from or stored in an audit trail containing the step records. By processing the rollback records in the periodic save record during a recovery, a database may identify a time on an audit trail for initiating a recovery prior to the last resume point for a step without going back in the audit trail to a time before the initial start of the step.

Abstract: A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far end data termination devices via a hybrid fiber coaxial network and a cable modem termination system. The described network gateway combines a QAM receiver, a transmitter, a DOCSIS MAC, a CPU, a voice and audio processor, a voice synchronizer, an Ethernet MAC, and a USB controller to provide high performance and robust operation.

Abstract: A method of an aspect includes receiving an indication of an attempt by a virtual machine to modify a paging structure identification storage location to have a given value. It is determined that the given value matches at least one of a set of one or more blacklist values. The attempt by the virtual machine to modify the paging structure identification storage location to have the given value is trapped to a virtual machine monitor. Other methods, apparatus, and systems are also disclosed.

Abstract: A code converter 11 of a simulation apparatus 1 detects, during the execution of a program in a target CPU, an externally dependent instruction affected by the external environment in each of divided blocks, predicts the execution result of the externally dependent instruction, simulates the instruction execution in the predicted result, and generates a host code in which a code for performance simulation is embedded based on the simulation result. A simulation executor 12 performs performance simulation about instruction execution in the prediction result of the program using the host code, and when the execution result of the externally dependent instruction is different from the setting of the prediction result during the execution, corrects the execution time of the instruction in the prediction result using the execution time of instructions executed before and after the instruction, and the like. A simulation information collector 13 collects and outputs performance simulation information.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Embodiments of the present disclosure may be configured to permit development and validation of a device driver or a device application program by using improved virtual devices. Such improved virtual devices may facilitate driver development without use of physical devices or hardware prototypes. In various embodiments, advanced validation of a device-driver combination may be permitted that would be difficult to achieve even with a physical device. Certain embodiments also may detect inconsistencies between virtual and physical devices, which may be used to improve drivers and device application programs and increase compatibility of such drivers and device application programs with physical devices.

Abstract: Scripts are incrementally compiled at runtime to generate executable code. The incremental compilation generates executable code corresponding to a basic block of the script. The executable code for a basic block of script is generated for a set of types of variables of the basic block resulting from execution of the script in response to a request. The generated executable code is stored and executed for subsequent requests if these requests result in the same types of variables for the basic block. The incremental compilation of the script is performed in a lazy fashion, such that executable code is not generated for combinations of types of variables of the script code that are not obtained from requests received at runtime. The script may dynamically generate portions of a web page that is returned in response to a request for execution of the script.

Abstract: A memory stores therein a program status word containing an address of data that is to be read when an interrupt process is executed. a processor determines whether or not the program status word stored in the memory is available, controls the memory to stores a determination result in the memory in association with the program status word, acquires the program status word and the determination result from the memory when the interrupt process occurs, and reads data on the basis of the address contained in the acquired program status word when the acquired determination result indicates that the program status word is available.

Abstract: A device may emulate target instructions by executing a first set of microinstructions, and may store a base address of a table that includes a microinstruction provided in a second set of microinstructions for emulating the target instructions. The device may also locate the microinstruction based on the stored base address, and emulate one of the target instructions by executing the microinstruction.

Abstract: Two or more processes for executing a source application are emulated using: a virtual trampoline memory in which each emulated process has a respective private trampoline memory; and a shared code heap memory. Each emulated process only sees the shared code heap and its respective private trampoline memory. A respective equivalent target instruction fragment for writing to the code heap is generated for each of multiple source instruction fragments from the application, each target instruction fragment being indexed by its physical address in the code heap. Each of at least one jump instruction in the fragment is replaced with a jump to a corresponding slot in the virtual trampoline memory. A trap is written to each corresponding private trampoline slot, each trap adapted to be replaced by a jump to an address in the code heap corresponding to the jump destination.

Abstract: Disclosed is an information processing system having one or more computers. The information processing system includes a request receiver configured to receive a request from a program causing an apparatus to execute a predetermined process, a simulator configured to simulate the process executed by the apparatus in accordance with the request, an instruction receiver configured to receive a status change instruction for changing a status of the simulator from a user, and a status changer configured to cause the simulator to change a status of the simulator in accordance with the status change instruction. In the information processing system, the simulator simulates the process executed by the apparatus in the status changed by the status changer.

Abstract: A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell.

Abstract: Systems, apparatus and methods described herein are configured to receive a user command line instruction, of a first type, for transmission to a device and convert the user command line instruction to a device specific command line instruction. In some embodiments, the systems, apparatus and methods described herein are further configured to transmit the device specific command line instruction to the device, and convert a device specific response received from the device to a response of the first type.

Abstract: Provided is a method of preserving object code translations of a library for future reuse by an emulator. A munmap(2) system call is intercepted from an application for unmapping a mapped library memory address. A determination is made if an entry related to the mapped library memory address is present in a first predefined data structure. If said entry is present, a determination is made if the mapped library memory address corresponds to a library text or library data. If the mapped memory address corresponds to the library text, said entry is flagged as inactive in the first predefined data structure, and an object code translation of the library text is preserved in the mapped library memory address. If the mapped library memory address corresponds to the library data, contents of the mapped address are reset to zero.

Abstract: A method of telephone call management in process of service development that allows a user to model and create telephone call management schemes independent of telecommunications protocols and network layer details. The method of the invention operates by creating an abstract model of a telephone call life-cycle that is converted, using a set of communication threads, into executable code. Models in accordance with the method of the invention are constructed using an Integrated Development Environment (IDE) for creating and developing telecom services that embodies the Telecom Service Domain Specific Language (TS-DSL) which is implemented as a Unified Modeling Language (UML) extension for the telecom domain. By this method, individuals without specialized knowledge of telecom related software programming and protocols can successfully design and implement telecom services that manages calls.

Abstract: A method for synchronizing different components of a computer network system using meta-commands embedded in normal network packets. The data communication channel between different components of a computer network system can be used to transport meta-commands piggybacked in normal network packets, without modifying or compromising the validity of the protocol message. Embodiments of the method can be used for embedding test synchronization and control commands into the network packets sent through a device or system under test. The device or system under test can be an edge device, with the data communication channel carrying normal packets containing meta-commands embedded in the packets to synchronize the test control of the test clients and the test servers connected to the edge device.

Abstract: The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation.

Abstract: A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed.

Abstract: Apparatus and method for processing information may determine whether a migration condition exists by a source information processing unit executing a program. When a migration condition is determined to exist by the source information processing unit, a destination information processing unit may determine whether an instruction to be executed of the program is a predetermined instruction. The instruction to be executed is converted by an instruction emulator, when a result of a determination by the destination information processing unit is the predetermined instruction.

Abstract: An improved emulator for analyzing software code, and associated method. The emulator includes a virtual execution environment in which a series of virtual processing states are represented during emulation of a first portion of the software code, and a hardware accelerator that performs an initialization of the computing hardware to directly execute a second portion of the software code under investigation without emulation thereof in the virtual execution environment. An efficiency assessment module determines a measure of efficiency of performing the executing of the second portion of the software code under investigation without emulation thereof, and an acceleration decision module performs selection of the second portion of the software code under investigation to be directly executed by the hardware accelerator module based on the determined measure of efficiency.

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract: Calls from an application in an emulated environment to a module in the operating system hosting the emulated environment may be combined to reduce the overhead of accessing the module. An application handling secure shell (SSH) communications may execute multiple calls to a cryptographic module in the host operating system. Because many calls to the cryptographic module during SSH communications follow patterns, two or more related calls may be combined into a single combined call to the cryptographic module. For example, a call to generate a server-to-client key and a call to generate a client-to-server key may be combined into a single call.

Abstract: A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.

Abstract: The present invention is directed to a method of operating a knowledge capture program. The knowledge capture program has the steps of starting the knowledge capture program wherein a user can access content that is either existing content or creating new content. Once the content has been selected then a source subject matter can be selected and displayed, and then captured and incorporated into the content. The source subject matter can be edited and saved into the content. The content can then be retrieved and played in a desired mode of learning.

Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.

Abstract: Emulation of source machine instructions is provided in which target machine CPU condition codes are employed to produce emulated condition code settings without the use, encoding or generation of branching instructions.

Abstract: A method, system and program product for executing a multi-function instruction in an emulated computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.

Abstract: This invention allows code emulation in a memory system by implementing a fixed location and size emulation segment that is only accessible to emulation requests, and may be mapped to any area of the physical memory space by the Extended Memory Controller. All areas of the memory space are visible to the emulation process, whether there is a functional segment mapped to that area or not.

Abstract: One embodiment relates to a computer method of evaluating proposed edits to a target layer of an integrated circuit. In the method, a number of editable regions is determined for metal layers overlying the target layer, where an editable region for a metal layer is laterally arranged between segments of the metal layer. The method identifies a number of possible vertical milling paths that extend from an exterior surface of the integrated surface to the target layer. Each possible vertical milling path passes through at least one editable region. The method generates a number of possible edit plans that are based on both the proposed edits and the number of possible vertical milling paths, where each edit plan places edits in a different combination of possible vertical milling paths.

Abstract: A computer system including no basic input/output system (BIOS) for operating bootstrap used in initial activation of a legacy operation system is allowed to perform booting of legacy operation system therefor and includes a central processing unit (CPU) and a memory, in which extended firmware and bootstrap program are stored. The extended firmware includes BIOS emulator and a plurality of device drivers. The extended firmware uses the device driver to make the BIOS emulator perform emulation of BIOS operation in response to a BIOS call issued by the bootstrap program.

Abstract: An original processor uses addresses with a first length of n bits for addressing in a cyclical address space and a target processor uses addresses with a second length of m bits, where the second length m is greater than the first length n. In the original processor, distance values that lie between a lower value min and an upper value max are permissible for the base register-relative addressing. The supported address space on the original processor for the code to be emulated is limited in such a manner that the conversion of address operands as described in the following steps leads to semantically equivalent behavior on the target processor.

Abstract: Methods, apparatuses and storage medium associated with ISA bridging with support for virtual functions, are disclosed. In embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution, to provide an ISA bridging layer to the target device to facilitate a library service of a library of the target device to call a virtual function of the library, while servicing an application operating on the target device, where the application has an overriding implementation. The ISA bridging layer may include a loader configured to load the application for execution, and as part of loading the application, detect the virtual function and modify a virtual function table of the application to enable the call. Other embodiments may be disclosed or claimed.

Abstract: Certain example embodiments relate to a computer program written in the programming language Java for emulating the memory management of a computer program written in the programming language C. The C program includes instructions for allocating a memory area, instructions for defining at least one data structure, and instructions for defining at least one pointer to the allocated memory area in accordance with the at least one data structure. The Java program may include instructions for: providing a Java byte array for emulating the allocated memory area of the C program; and providing at least one Java object for emulating the at least one data structure of the C program. The at least one Java object uses at least one Java ByteBuffer object for emulating the at least one pointer of the C program.

Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer program product for accelerating execution of a program, written in an object oriented programming language, in an emulated environment. In response to receiving a request for an accelerated communications session from a guest virtual machine in the emulated environment, a native virtual machine is initiated external to the emulated environment but within the computing device hosting the emulated environment. Thereafter, an accelerated communications link is established between the guest virtual machine and the native virtual machine. The accelerated communications link enables a transfer of managed code between the guest virtual machine and the native virtual machine. The managed code is then executed by the native virtual machine.

Abstract: An emulator is provided for an interface device. The emulator includes all functional software of the physical interface device, including configuration software, operating system, design-time environment, run-time engine, and so forth. Device elements, which may be standard COM elements objects, may be configured via the emulator, as may particular interface screens, applications, and so forth. The emulator may be used to try interface devices before their specification for a particular product. The emulator may also be used to develop software and interface screens that will be downloaded to interface device hardware prior to product introduction, thereby facilitating and improving time-market for new product introductions.

Abstract: A method for time correction during an emulation of a native computing environment (NCE), including: obtaining, by an emulator, a code segment for execution within the NCE; identifying, during an execution of the code segment within the emulation, a first instance of a time sensitive (TS) instruction; initiating a first instruction sequence window (ISW) in response to identifying the first instance of the TS instruction; identifying, during the execution of the code segment within the emulation, a second instance of the TS instruction after initiating the first ISW; obtaining, in response to identifying the second instance during the first ISW, an expected time between execution of the first instance and the second instance of the TS instruction in the NCE; and inserting an aggregated delay based on the expected time during the execution of the code segment within the emulation.

Abstract: A network performance estimating device for estimating network performance of a parallel computing machine for executing plural processes in parallel, includes a communication data obtaining unit that obtains communication data output from plural calculation nodes when the plural processes are executed by using the plural calculation nodes, a design estimating unit for referring to a design information storing unit that stores design information defining a network as an estimation target to execute a simulation on communications when the communication data obtained by the communication data obtaining unit are transmitted through the network as the estimation target, and renews estimation information representing an estimation result of the estimation target network stored by an estimation information storing unit on the basis of the obtained simulation result, and a communication data transmission unit for transmitting the communication data obtained by the communication data obtaining unit to an addressed ca

Abstract: Methods for simulating an instruction set architecture (ISA) with a instruction set simulator (ISS) are provided. One exemplary embodiment of the methods includes fetching a first decoded instruction during a run time, where the decoded instruction is decoded from an original instruction in a target application program during a compile time preceding the run time. The decoded instruction can designate a template configured to implement the functionality of the original instruction. The method also preferably includes determining whether the fetched instruction is modified from the original instruction and then executing the designated template if the instruction was not modified. The method can also include decoding the original instruction during the compile time by selecting a template corresponding to the original instruction and then customizing the template based on the data in original instruction. The method can also include optimizing the customized template during the compile time.