Architecture Patents (Class 706/27)
  • Patent number: 6502083
    Abstract: The improved neuron is connected to input buses which transport input data and control signals. It basically consists of a computation block, a register block, an evaluation block and a daisy chain block. All these blocks, except the computation block substantially have a symmetric construction. Registers are used to store data: the local norm and context, the distance, the AIF value and the category. The improved neuron further needs some R/W memory capacity which may be placed either in the neuron or outside. The evaluation circuit is connected to an output bus to generate global signals thereon. The daisy chain block allows to chain the improved neuron with others to form an artificial neural network (ANN). The improved neuron may work either as a single neuron (single mode) or as two independent neurons (dual mode). In the latter case, the computation block, which is common to the two dual neurons, must operate sequentially to service one neuron after the other.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: December 31, 2002
    Assignee: International Business Machines Corporation
    Inventors: Didier Louis, Pascal Tannhof, Andre Steimle
  • Publication number: 20020091656
    Abstract: A web-enabled system for teaching skills to participants, assisting participants in integrating and applying those skills to their vocation, assessing the success of participants in applying the skills, and evaluating whether or not additional training is necessary is disclosed. The present system may be used to train instructors based on federal, state or regional industry standards and to assist them in integrating their training into their work environment. This system operates by initially providing a matrix that automatically conforms to standards set by the state or regional districts where the instructor works. Next, instructors use the matrix to train. The system then enables the instructor to integrate the training into their work environment. After the instructor teaches based on the training received, students of the instructor may then be assessed using any of the standardized examinations.
    Type: Application
    Filed: August 31, 2001
    Publication date: July 11, 2002
    Inventor: Chet D. Linton
  • Patent number: 6405122
    Abstract: A data estimation capability using a FNN to estimate engine state data for an engine control system is described. The data estimation capability provides for making data relating to the engine state available as control parameters in a simple, inexpensive manner. The data estimation includes using data from one or more sensors as inputs to a FNN to estimate unmeasured engine operating states. The data estimates are provided as control parameters to an engine control system. The FNN can be used to provide data estimates for engine state values (e.g. the exhaust air fuel ratio, the exhaust NOx. value, the combustion chamber temperature, etc.) that are too difficult or too expensive to measure directly. Each FNN can be configured using a genetic optimizer to select the input data used by the FNN and the coupling weights in the FNN.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: June 11, 2002
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventor: Masashi Yamaguchi
  • Patent number: 6366897
    Abstract: A cortronic neural network defines connections between neurons in a number of regions using target lists, which identify the output connections of each neuron and the connection strength. Neurons are preferably sparsely interconnected between regions. Training of connection weights employs a three stage process, which involves computation of the contribution to the input intensity of each neuron by every currently active neuron, a competition process that determines the next set of active neurons based on their current input intensity, and a weight adjustment process that updates and normalizes the connection weights based on which neurons won the competition process, and their connectivity with other winning neurons.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: April 2, 2002
    Assignee: HNC Software, Inc.
    Inventors: Robert W. Means, Richard Calmbach
  • Patent number: 6332137
    Abstract: A recognition system comprises at least two field-programmable logic array devices connected to a common vector-input port of an array of a zero-instruction-set computers. Each field-programmable logic array device is configured to preprocess data from different respective media inputs and provide feature extraction vectors to the common vector-input port. Neural networks within the zero-instruction-set computer recognize the input patterns by comparing in parallel their vectors with those stored in each neural network cell. A variety of recognition jobs are made possible by changing the programming on-the-fly of the field-programmable logic array devices to suit each new job.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: December 18, 2001
    Inventors: Toshikazu Hori, Guy Paillet, Jeffrey M. Woo
  • Patent number: 6324532
    Abstract: A signal processing apparatus and concomitant method for learning and integrating features from multiple resolutions for detecting and/or classifying objects. The signal processing apparatus comprises a hierarchical pyramid of neural networks (HPNN) having a “fine-to-coarse” structure or a combination of the “fine-to-coarse” and the “coarse-to-fine” structures.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: November 27, 2001
    Assignee: Sarnoff Corporation
    Inventors: Clay Douglas Spence, Paul Sajda
  • Patent number: 6289330
    Abstract: The present invention provides a system for learning from and responding to regularly arriving information at once by quickly combining prior information with concurrent trial information to produce useful learned information. A parallel embodiment of the system performs can perform updating operations for memory elements of matrix through the coordinated use of parallel feature processors and a joint access memory, which contains weighted values and provision for connecting feature processors pairwise. The parallel version also performs feature function monitoring, interpretation and refinement operations promptly and in concert with concurrent operation. A non-parallel embodiment of the system uses a single processor to perform the above operations however, more slowly than the parallel embodiment, yet faster than available alternatives.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: September 11, 2001
    Assignee: Netuitive, Inc.
    Inventor: Robert Jannarone
  • Patent number: 6269354
    Abstract: The invention comprises e-circuits built from basic modules of e-cells which are capable of: recognizing a previously memorized percept anywhere within an arbitrarily large input field without incurring delay related to size of the search space; isolating a previously memorized percept within the input field when in the adjacent presence of other percepts and closely related distractors; locating and recognizing all occurrences of a repeated subfield within the input field, even in the presence of closely related distractors; and performing sequential shift attention between a number of different percepts in the input field. The invention is applicable to various recognition tasks including those in sensory domains such as speech and music recognition, vision, olefaction, and touch.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: July 31, 2001
    Inventor: David W. Arathorn
  • Patent number: 6256619
    Abstract: A analog data neural network processing system is provided in which there is a self optimization capability that varies the signal processing factors in response to a detected contrast in the system output patterns. The system provides feedback type guidance in varying such processing factors as sampling rate, frame length, signal transformation, neural network vigilance and architecture, each in a direction that will maximize or minimize the contracts with patterns used to train the network. The processing system is useful in all signal classification tasks.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: July 3, 2001
    Assignee: Caterpillar Inc.
    Inventor: Anthony J. Grichnik
  • Patent number: 6249781
    Abstract: A method and apparatus is disclosed for machine learning of a pattern sequence which is derived from a plurality of inputs. The pattern sequence is predicted from learning rate parameters that are exponentially related to an incrementally calculated gain parameter for each input. The gain parameter are increased or decreased in real time in correlation with the accuracy of the learning process. The disclosed method and apparatus are advantageously utilized in signal processing, adaptive control systems, and pattern recognition.
    Type: Grant
    Filed: May 5, 1999
    Date of Patent: June 19, 2001
    Assignee: Verizon Laboratories Inc.
    Inventor: Richard S. Sutton
  • Patent number: 6199057
    Abstract: A neuroprocessor architecture employs a combination of bit-serial and serial-parallel techniques for implementing the neurons of the neuroprocessor. The neuroprocessor architecture includes a neural module containing a pool of neurons, a global controller, a sigmoid activation ROM look-up-table, a plurality of neuron state registers, and a synaptic weight RAM. The neuroprocessor reduces the number of neurons required to perform the task by time multiplexing groups of neurons from a fixed pool of neurons to achieve the successive hidden layers of a recurrent network topology.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: March 6, 2001
    Assignee: California Institute of Technology
    Inventor: Raoul Tawel
  • Patent number: 6171109
    Abstract: The objective of this disclosure is to propose a method of designing an intelligent system assuring autonomy in problem solving to the largest extent. An architecture of a general purpose problem solving system and also a new modeling scheme for representing an object which may include human activity are discussed first. Then a special purpose problem solving system dedicated for a given problem is generated. It is extracted from a general purpose system using the object model as a template. Several new concepts are included in this disclosure to achieve this goal; a multi-level function structure and its corresponding knowledge structure, multiple meta-level operations, a level manager for building general purpose problem solving systems, a concept of multi-strata model to represent objects including human activity, and a method of extracting a special purpose system from a general purpose system and so on.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: January 9, 2001
    Assignee: Adin Research, Inc.
    Inventor: Setsuo Ohsuga
  • Patent number: 6169981
    Abstract: A method and system for intelligent control of external devices using a mammalian brain-like structure having three parts. The method and system include a computer-implemented neural network system which is an extension of the model-based adaptive critic design and is applicable to real-time control (e.g., robotic control) and real-time distributed control. Additional uses include data visualization, data mining, and other tasks requiring complex analysis of inter-relationships between data.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: January 2, 2001
    Inventor: Paul J. Werbos
  • Patent number: 6067536
    Abstract: A neural network circuit for performing a processing of recognizing voices, images and the like comprises a weight memory for holding a lot of weight values (initial weight values) which correspond to a plurality of input terminals of each of a plurality of neurons forming a neural network and have been initially learned, and a difference value memory for storing difference values between the weight values of the weight memory and additionally learned weight values. The weight memory is formed by a ROM. The difference value memory is formed by a SRAM, for example. During operation of recognizing input data, the initial weight values of the weight memory and the difference values of the difference value memory are added together. The added weight values are used to calculate an output value of each neuron of an output layer. Accordingly, the initial weight values can be additionally learned at a high speed by existence of the difference value memory having a small capacity.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: May 23, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masakatsu Maruyama, Hiroyuki Nakahira, Masaru Fukuda, Shiro Sakiyama
  • Patent number: 6038556
    Abstract: An autonomous adaptive agent (100) which can learn verbal as well as nonverbal behavior. The primary object of the system is to optimize a primary value function (7) over time through continuously learning how to behave in an environment (which may be physical or electronic). Inputs (1) may include verbal advice or information from sources of varying reliability as well as direct or preprocessed environmental inputs (1C). Desired agent (100) behavior may include motor actions and verbal behavior which may constitute a system output (3) and which may also function "internally" to guide external actions. A further aspect involves an efficient "training" process (306) by which the agent (100) can be taught to utilize verbal advice and information along with environmental inputs (1C).
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: March 14, 2000
    Inventor: William R. Hutchison
  • Patent number: 6032140
    Abstract: A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: February 29, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventors: Vito Fabbrizio, Gianluca Colli, Alan Kramer
  • Patent number: 6009418
    Abstract: A semantic attractor memory uses an evolving neural network architecture and learning rules derived from the study of human language acquisition and change to store, process and retrieve information. The architecture is based on multiple layer channels, with random connections from one layer to the next. One or more layers are devoted to processing input information. At least one processing layer is provided. One or more layers are devoted to processing outputs and feedback is provided from the outputs back to the processing layer or layers. Inputs from parallel channels are also provided to the one or more processing layers. With the exception of the feedback loop and central processing layers, the network is feedforward unless it is employed in a hybrid back-propagation configuration. The learning rules are based on non-stationary statistical processes, such as the Polya process or the processes leading to Bose-Einstein statistics, again derived from considerations of human language acquisition.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: December 28, 1999
    Inventor: David L. Cooper
  • Patent number: 5956703
    Abstract: A neural network IC 31 includes n dedicated processing elements (PEs) 62, an output register 66 for storing the PEs' outputs so that they are immediately accessible to all of the PEs, a number of output circuits 78 that are connected to selected PEs to provide binary outputs, and a timing circuit 74. Each of the PEs includes a weight memory 90 for storing input, output and bias weight arrays, a first in first out (FIFO) memory 88 for storing input data, a dot product circuit 92 and an activation circuit 94. The dot product circuit computes a dot product of the input weight array and the contents of the FIFO memory, a dot product of the output weight array and the contents of the output register, a dot product of the bias value and a constant, and sums the three results. The activation circuit maps the output of the dot product circuit through an activation function to produce the PE's output.
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: September 21, 1999
    Assignee: Delco Electronics Corporation
    Inventors: Douglas D. Turner, Gabriela Breuer
  • Patent number: 5950181
    Abstract: In an apparatus and a method for detecting and assessing a spatially discrete dot pattern disposed in a multidimensional coordinate system, each dot in the pattern assumes at least two differentiatable status values. A measuring device records the coordinate values and status values of each dot of the multidimensional spatial dot pattern. A memory stores data that correspond to the recorded coordinate values and status values of each dot of the multidimensional spatial dot pattern. A computer into which the stored data are entered and in which a coordinate counter for each coordinate value of a coordinate axis is determined from the stored data, is associated with the memory. The value of the coordinate counter is formed from the number of detected dots of the coordinates that have a predetermined status value. A neural network is associated with the computer.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: September 7, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventor: Peter Federl
  • Patent number: 5842190
    Abstract: A network of networks system and method includes a neuron having processing capabilities; a first level module including a network of a plurality of interconnected neurons, the first level module also having processing capabilities; and a second level module including a network of interconnected networks or interconnected neurons, the second level module also having processing capabilities; wherein the first and second level modules are interconnected through neuron to neuron connections such that simultaneous processing can be carried out at by the neuron and by the first and second level modules. The system and method also includes means for forming a boundary between a first module having a first memory state and a second module having a second memory state such that the module comprising the boundary attains a third memory state distinct from the first and second memory states.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: November 24, 1998
    Assignees: Brown University Research Foundation, The General Hospital Corporation
    Inventors: Jeffrey P. Sutton, James A. Anderson
  • Patent number: 5812993
    Abstract: A digital neural network architecture including a forward cascade of layers of neurons, having one input channel and one output channel, for forward processing of data examples that include many data packets. Backward cascade of layers of neurons, having one input channel and one output channel, for backward propagation learning of errors of the processed data examples. Each packet being of a given size. The forward cascade is adapted to be fed, through the input channel, with a succession of data examples and to deliver a succession of partially and fully processed data examples each consisting of a plurality of packets. The fully processed data examples are delivered through the one output channel. Each one of the layers is adapted to receive as input in its input channel a first number of data packets per time unit and to deliver as output in its output channel a second number of data packets per time unit.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: September 22, 1998
    Assignee: Technion Research and Development Foundation Ltd.
    Inventors: Ran Ginosar, Nitzan Weinberg
  • Patent number: 5787408
    Abstract: A system for unwrapping an artificial neural network (ANN) to determine the tilization and functionality of the nodes uses a network generator for generating an initial ANN architecture. Training and pruning processors operate to generate minimal ANN architectures having increasingly lower levels of classification accuracy. A network analyzer uses an analysis controller to receive minimal ANN architectures from the pruning processor. A connection analyzer operates on the minimal ANN architectures to identify the inputs to the minimal ANN architecture and determine the information represented by and contained in the network inputs. A node analyzer, coupled to the connection analyzer, then defines the utilization and functionality of each node in the minimal ANN architecture in terms of known functions.
    Type: Grant
    Filed: August 23, 1996
    Date of Patent: July 28, 1998
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Christopher M. Deangelis
  • Patent number: RE37488
    Abstract: A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a nonlinear function to produce training &phgr; vectors. A systolic array arranged for QR decomposition and least mean squares processing forms combinations of the elements of each &phgr; vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed to provide estimates of unknown result. The processor is applicable to provide estimated results for problems which are nonlinear and for which explicit mathematical formalisms are unknown.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: December 25, 2001
    Assignee: The Secretary of State for Defence in Her Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: David Sydney Broomhead, Robin Jones, Terence John Shepherd, John Graham McWhirter