Abstract: A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate, a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is connected to the CMOS logic gate such that the tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.

Abstract: The present invention discloses a brain machine interface decoding method based on spiking neural network, comprising: (1) constructing a liquid state machine model based on a spiking neural network, the liquid state machine model consists of an input layer, an middle layer and an output layer, wherein, a connection weight from the input layer to the middle layer is Whh, a loop connection weight inside the middle layer is Whh, a readout weight from the middle layer to the output layer is Wyh; (2) Inputting a neuron spike train signal, and training each weight with the following strategy: (2-1) Using STDP without supervision to train the connection weight Whh from the input layer to the middle layer; (2-2) Setting the loop connection weight Whh inside the middle layer by means of distance model and random connection, and obtaining a middle layer liquid information R(t); (2-3) Using ridge regression with supervision to train the readout weight Wyh from the middle layer to the output layer, and establishing a ma

Abstract: Embodiments of the present disclosure provide a dual-modality neuromorphic vision sensor. A first-type current-mode active pixel sensor (APS) circuit can mimic excitatory rod cells, to perceive light intensity gradient information in a target light signal, thereby improving a dynamic arrange of an image sensed by a neuromorphic, vision sensor and its shooting speed. In addition, a first-type control switch is introduced for each of non-target first-type photosensitive devices, to control the obtained light intensity gradient information, and adjust the dynamic arrange of the image sensed by the neuromorphic vision sensor, thereby adjusting the shooting speed, and realizing a reconfigurable effect A voltage-mode APS can mimic cone cells, to output a target voltage signal representing light intensity information in the target light signal, and perceive the light intensity information in the target light signal.

Abstract: Provided is a method for training distributed machine learning models. The method may include initializing a distributed machine learning model on a plurality of computing devices. Training data associated with a plurality of samples may be received. Each sample may be forward propagated through the distributed machine learning model to generate an output. A loss for each sample of the plurality of samples may be determined based on the output. The loss for each sample may be backward propagated to each computing device. The parameter(s) of each computational node may be asynchronously updated based on the loss as it is backward propagated and/or while at least one of the samples is forward propagating. The parameter(s) may be stored and/or communicated to the other computing devices. Each of the other computing devices of the plurality of computing devices may store the parameter(s). A system and computer program product are also disclosed.

Abstract: The present disclosure describes an artificial neural network circuit including: at least one crossbar circuit to transmit a signal between layered neurons of an artificial neural network, the crossbar circuit including multiple input bars, multiple output bars arranged intersecting the input bars, and multiple memristors that are disposed at respective intersections of the input bars and the output bars to give a weight to the signal to be transmitted; a processing circuit to calculate a sum of signals flowing into each of the output bars while a weight to a corresponding signal is given by each of the memristors; a temperature sensor to detect environmental temperature; and an update portion that updates a trained value used in the crossbar circuit and/or the processing circuit.

Abstract: Methods and systems for neural network processing include configuring a physical network topology for a network that includes hardware nodes in accordance with a neural network topology, one of which is designated as a master node with any other nodes in the network being designated as slave nodes. One or more virtual neurons are configured at each of the hardware nodes by the master node to create a neural network having the neural network topology. Each virtual neuron has a neuron function and logical network connection information that establishes weighted connections between different virtual neurons. A neural network processing function is executed using the neural network.

Abstract: A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive in an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate including a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.

Abstract: A molecular electronic device (10) includes a framework of polynucleotides (3), one or more molecular electronic components (4) and one or more electrical contacts (7). The molecular electronic components and the electrical contacts are each connected to the plurality of polynucleotides such that the molecular electronic components and the electrical contacts are located with respect to the framework and with respect to each other. This forms a coupling between the electrical contacts and the molecular electronic components.

Abstract: An artificial neuron for a neuromorphic chip comprises a synapse with resistive memory representative of a synaptic weight. The artificial neuron comprises a read circuit, an integration circuit and a logic circuit interposed between the read circuit and the integration circuit. The read circuit is configured to impose on the synapse a read voltage independent of the membrane voltage and to provide an analogue value representative of the synaptic weight. The logic circuit is configured to generate from the analogue value a pulse having a duration. The integration circuit comprises an accumulator of synaptic weights at the terminals of which a membrane voltage is established and a comparator configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage. Moreover, it comprises a source of current controlled by the pulse to inject a current into the accumulator of synaptic weights during this duration.

Abstract: Provided are a pen state detection circuit, a pen state detection system, and a pen state detection method that can improve estimation accuracy for a pen state in an electronic pen including at least one electrode. A pen state detection circuit acquires, from a touch sensor, a first signal distribution indicating a change in capacitance associated with approach of a first electrode and uses a machine learning estimator to estimate an instruction position or an inclination angle of an electronic pen from first feature values related to the first signal distribution. The first feature values include first local feature values related to a first local distribution corresponding to sensor electrodes in a number fewer than the number of arranged sensor electrodes exhibiting the first signal distribution.

Abstract: The present disclosure provides a method, a device and a computer readable storage medium for food risk traceability information classification.

Abstract: The present invention relates to a neuromimetic network comprising a set of neurons and a set of synapses, at least one neuron comprising a first stack of superimposed layers, the first stack successively comprising: a first electrode, a first barrier layer made of an electrically insulating material, and a second electrode, the first electrode, the first barrier layer and the second electrode forming a first ferroelectric tunnel junction, at least one synapse comprising a second stack of superimposed layers, the second stack successively comprising: a third electrode, a second barrier layer made of an electrically insulating material, and a fourth electrode, the third electrode, the second barrier layer and the fourth electrode forming a second ferroelectric tunnel junction.

Abstract: The present invention relates to a pulse driving apparatus for minimising an asymmetric image between long-term potentiation (LTP) and long-term depression (LTD) in a hardware neural network, and a method therefor; and can minimise asymmetry between the LTP process and the LTD process, thereby improving a match rate of actual results by separately performing a first operation that performs on the LTP process, and a second operation that performs the LTP process and the LTD process.

Abstract: An information processing apparatus includes: an output management information storage unit in which one or more pieces of output management information having an output condition, which is a condition for outputting emotion information and is a condition related to content, and emotion information are stored; an input information accepting unit that accepts input information that is content; an output information acquiring unit that judges whether or not information acquired using the content accepted by the input information accepting unit matches each of the one or more output conditions, and acquires emotion information that is paired with each of the one or more matching output conditions, from the output management information storage unit; and an information output unit that outputs the one or more pieces of emotion information acquired by the output information acquiring unit.

Abstract: A synapse circuit with an arrayed structured memory for machine learning applications is disclosed. The synapse circuit comprises a controlled variable resistance, a controlled switch connected to a contact terminal of the controlled variable resistance, and a memory cell for storing a weight variable. The memory cell is operatively connected to a control terminal of the controlled switch. A control terminal of the controlled variable resistance is configured for receiving an activation signal. The controlled variable resistance has a first resistance value and a second resistance value substantially larger than the first resistance value. A ratio of the second resistance value to the first resistance value is at least one hundred.

Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: Described is a system, integrated circuit and method for reducing ineffectual computations in the processing of layers in a neural network. One or more tiles perform computations where each tile receives input neurons, offsets and synapses, and where each input neuron has an associated offset. Each tile generates output neurons, and there is also an activation memory for storing neurons in communication with the tiles via a dispatcher and an encoder. The dispatcher reads neurons from the activation memory and communicates the neurons to the tiles and reads synapses from a memory and communicates the synapses to the tiles. The encoder receives the output neurons from the tiles, encodes them and communicates the output neurons to the activation memory. The offsets are processed by the tiles in order to perform computations only on non-zero neurons. Optionally, synapses may be similarly processed to skip ineffectual operations.

Abstract: Provided is a neuromorphic system using a neuron circuit. The neuromorphic system includes: one or two or more neuron circuits configured to output a firing signal according to signals input from a synapse array; a homeostatic circuit for each neuron circuit; and a global self-controller configured to generate and provide control signals for the neuron circuits by using the firing signal output from the neuron circuits. The neuron circuit includes a neuromorphic device and an output circuit that outputs the firing signal of the neuromorphic device. The global self-controller generates and supplies a reset signal to the neuromorphic device of the fired neuron circuit, and the global self-controller generates and supplies a lateral inhibition signal to the neuromorphic device of the non-fired neuron circuit. The homeostatic circuit alleviates inhibition of other neurons by the neurons with a predominant firing function.

Abstract: Methods and apparatus are provided for training an artificial neural network, having a succession of neuron layers with interposed synaptic layers each storing a respective set of weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for at least one of the synaptic layers, providing a plurality Pl of arrays of memristive devices, each array storing the set of weights of that synaptic layer Sl in respective memristive devices, and, in a signal propagation operation, supplying respective subsets of the signals to be weighted by the synaptic layer Sl in parallel to the Pl arrays. The method also includes, in a weight-update calculation operation, calculating updates to respective weights stored in each of the Pl arrays in dependence on signals propagated by the neuron layers.

Abstract: A differential-slope-limiting-switch and method are provided. Generally, the switch includes a first transistor having a first source-drain (SD) and well coupled to a first port of the switch, a gate, and a second SD, and a second transistor having a first SD and well coupled to a second port, a gate, and a second SD coupled to the second SD of the first transistor. A selector-circuit couples the gate of the first transistor to a first current-source when a signal to close the switch is received, and to the first port when it is not received. A second selector-circuit couples the gate of the second transistor to a second current-source when the signal is received, or to the second port. First and second feedback-capacitors couple each gate to the port on opposite sides of the switch and with the current-sources limit a slope of voltage transitions across the closed switch.

Abstract: An element construction unit compares output values of one or more elements included in an intermediate layer calculated by an output value calculating unit with a threshold value, and the number of elements included in the intermediate layer is maintained when any of the output values out of the output values of the one or more elements included in the intermediate layer is greater than the threshold value, and the number of elements included in the intermediate layer is increased when all of the output values of the one or more elements included in the intermediate layer are equal to or less than the threshold value.

Abstract: This disclosure describes methods and systems for high-throughput computations in a fully-connected deep neural network. Specifically, a hardware-based deep neural network architecture including a set of parallel node processors is used to process node value transition between layers of the deep neural network, which usually involves a large-scale matrix multiplication. The set of parallel node processors are configured to decompose the large-scale matrix multiplication into sub-matrix multiplications with smaller sizes and thus reducing the hardware-complexity and making feasible direct implementation in hardware. With this implementation deep neural network may achieve a very high throughput and can handle a large number of processing layers.

Abstract: Neuromorphic synapse apparatus is provided comprising a synaptic device and a control signal generator. The synaptic device comprises a memory element, disposed between first and second terminals, for conducting a signal between those terminals with an efficacy which corresponds to a synaptic weight in a read mode of operation, and a third terminal operatively coupled to the memory element. The memory element has a non-volatile characteristic, which is programmable to vary the efficacy in response to programming signals applied via the first and second terminals in a write mode of operation, and a volatile characteristic which is controllable to vary the efficacy in response to control signals applied to the third terminal. The control signal generator is responsive to input signals and is adapted to apply control signals to the third terminal in the read and write modes, in dependence on the input signals, to implement predetermined synaptic dynamics.

Abstract: A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of pairs of magnetic junctions, output transistors and at least one selection transistor coupled with the output transistors. The input lines receive the input signal and its complement. The magnetic junctions store the weight. Each magnetic junction includes a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer. The free layer has stable magnetic states and is programmable using spin-transfer torque and/or spin-orbit interaction torque. The first magnetic junction of a pair receives the input signal. The second magnetic junction of the pair receives the input signal complement. The output transistors are coupled with the magnetic junctions such that each pair of magnetic junctions forms a voltage divider. The output transistors form a sense amplifier.

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Abstract: Three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network includes a plurality of input conductors forming a plurality of stacked input layers having a first orientation, and at least one output conductor forming an output layer having the first orientation. The three-dimensional (3D) neural network also includes a plurality of hidden conductors having a second orientation. Each hidden conductor includes an in-line threshold element. The three-dimensional (3D) neural network also includes synapse elements coupled between the hidden conductors and the input conductors and between the hidden conductors and the output conductor. Each synapse element includes a programmable resistive element.

Abstract: Embodiments of the invention provide a method comprising receiving a set of features extracted from input data, training a linear classifier based on the set of features extracted, and generating a first matrix using the linear classifier. The first matrix includes multiple dimensions. Each dimension includes multiple elements. Elements of a first dimension correspond to the set of features extracted. Elements of a second dimension correspond to a set of classification labels. The elements of the second dimension are arranged based on one or more synaptic weight arrangements. Each synaptic weight arrangement represents effective synaptic strengths for a classification label of the set of classification labels. The neurosynaptic core circuit is programmed with synaptic connectivity information based on the synaptic weight arrangements. The core circuit is configured to classify one or more objects of interest in the input data.

Abstract: A method of classifying an action or event using an artificial neural network. The method comprises obtaining a first and a second plurality of feature responses, corresponding to point data in a first channel and a second channel respectively. Each of the first and second plurality of feature responses have associated temporal and spatial position values, the first and second plurality of feature responses relating to a plurality of objects. The method also comprises generating a third plurality of feature responses based on one of the first plurality of feature responses and one of the second plurality of feature responses, and a weighted combination of associated temporal and spatial position values of the corresponding one of the first and second plurality of feature responses; and classifying an action or event relating to the objects using the artificial neural network based on the third plurality of feature responses.

Abstract: A processor for performing deep learning is provided herein. The processor includes a processing element unit including a plurality of processing elements arranged in a matrix form including a first row of processing elements and a second row of processing elements. The processing elements are fed with filter data by a first data input unit which is connected to the first row processing elements. A second data input unit feeds target data to the processing elements. A shifter composed of registers feeds instructions to the processing elements. A controller in the processor controls the processing elements, the first data input unit and second data input unit to process the filter data and target data, thus providing sum of products (convolution) functionality.

Abstract: A neuromorphic device may include: a pre-synaptic neuron; a synapse electrically connected with the pre-synaptic neuron through a row line; and a post-synaptic neuron electrically connected with the synapse through a column line. The post-synaptic neuron may include a first inverter, the first inverter comprising a first pull-up transistor and a first pull-down transistor, a body of the first pull-up transistor and a body of the first pull-down transistor being electrically connected with a first output node of the first inverter.

Abstract: The present invention discloses an integrated neuro-processor comprising at least a three-dimensional memory (3D-M) array. The 3D-M array stores the synaptic weights, while the neuro-processing circuit performs neural processing. The 3-D integration between the 3D-M array and the neuro-processing circuit not only improves the computational power per die area, but also greatly increases the storage capacity per die area.

Abstract: A method for evaluating a gastrointestinal tract of a subject may comprise using a sensor located in the subject to obtain data regarding qualities of a tissue of the gastrointestinal tract; using the obtained data, determining a measure of perfusion of blood in the tissue; using the obtained data, determining a measure of thickness of the tissue; using the measure of perfusion and the measure of thickness, determining a measure of inflammation of the tissue; and using one or more of the measure of perfusion, the measure of thickness, and the measure of inflammation, classifying a state of the tissue.

Abstract: A neural network device includes a crossbar grid including first metal lines running in a first direction and second metal lines running transversely to the first metal lines and being electrically isolated from the first metal lines. An array of cross-over elements is included. Each cross-over element is connected between a first metal line and a second metal line. The cross-over elements each include a floating gate transistor device having a floating node. The floating node is configured to store a programmable weight value.

Abstract: A radiation imaging system images a distributed source of radiation from an unknown direction by rotating a scatter mask around a central axis. The scatter mask has a pixelated outer surface of tangentially oriented, flat geometric surfaces that are spherically varying in radial dimension that corresponds to a discrete amount of attenuation. Rotation position of the scatter mask is tracked as a function of time. Radiation counts from gamma and/or neutron radiation are received from at least one radiation detector that is positioned at or near the central axis. A rotation-angle dependent detector response curve (DRC) is generated based on the received radiation counts. A reconstruction algorithm for distributed radiation source(s) and/or localized source(s) are applied based on the tracked rotation position and prior characterization of the detector response for a given scatter mask. A two-dimensional image with relative orientation and source distribution is generated from the measured DRC.

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.

Abstract: Apparatus and methods for processing neural network models are provided. The apparatus can comprise a plurality of identical artificial intelligence processing dies. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies can include at least one inter-die input block and at least one inter-die output block. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die.

Abstract: Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.

Abstract: A processor includes an array of resistive processing units connected between row and column lines with a resistive element. A first single instruction, multiple data processing unit (SIMD) is connected to the row lines. A second SIMD is connected to the column lines. A first instruction issuer is connected to the first SIMD to issue instructions to the first SIMD, and a second instruction issuer is connected to the second SIMD to issue instructions to the second SIMD such that the processor is programmable and configurable for specific operations depending on an issued instruction set.

Abstract: Disclosed is a system and a method to use the system that includes a substrate to support a film of liquid helium and an electron subsystem confined by image forces in a direction perpendicular to the surface of the film, a side gate to electrostatically define a boundary of the electron subsystem, a trap gate to electrostatically define an electron trap located outside the boundary of the electron subsystem, and a load gate to selectively open and close access from the electron subsystem to the electron trap, wherein to open access to the electron trap is to apply a first load gate voltage to the load gate to allow the electrons to access the electron trap, and wherein to close access to the electron trap is to apply a second load gate voltage to the load gate to prevent the electrons from accessing the electron trap.

Abstract: Thermal pattern sensor including a matrix of multiple rows and columns of pixels, each pixel comprising: - a pyroelectric capacitor comprising a pyroelectric portion positioned between lower and upper electrodes, in which a first of these electrodes forms a readout electrode; and —a heating element that is capable of heating the pyroelectric portion of said pixel; and in which: - for each row of pixels, the heating elements are capable of heating the pyroelectric portion of the pixels of the row independently of the heating elements of the pixels of the other rows; and —for each column of pixels, the readout electrodes of each pixel are electrically linked to one another and are formed by a first electrically conductive portion that makes contact with the pyroelectric portions of the pixels of the column, and that is separate from the first portions of the other columns.

Abstract: In an example, an apparatus can include an array of memory cells and a neural memory unit controller coupled to the array of memory cells and configured to assert respective voltage pulses during a first training interval to memory cells of the array to change respective threshold voltages of the memory cells from voltages associated with a reset state to effectuate respective synaptic weight changes. The neural memory unit controller can be configured to initiate a sleep interval, during which no pulses are applied to the memory cells, to effectuate respective voltage drifts in the changed respective threshold voltages of the memory cells from a voltage associated with a set state toward the voltage associated with the reset state, and determine an output of the memory cells responsive to the respective voltage drifts in the changed respective threshold voltages after the sleep interval.

Abstract: A sensor system may be configured for continuous operation in a low resource environment and/or in extreme environmental conditions. The sensor system may have sufficient processing capabilities to provide scientific computing for pre-processing, quality control, statistical analysis, event classification, data compression and corrections (e.g., spikes in the data), autonomous decisions and actions, triggering other nodes, and information assurance functions that provide data confidentiality, data integrity, authentication, and non-repudiation. The hardware may have both mesh networking and satellite and cellular communication capability, and may be available for relatively low cost. Such a network provides the flexibility to have potentially any number of nodes be completely independent from one another. Thus, the network may scale across a diverse terrain.

Abstract: A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t1. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.

Abstract: The present invention relates to artificial neural network (ANN), for example, convolutional neural network (CNN). In particular, the present invention relates to how to implement and optimize a convolutional neural network based on an embedded FPGA. Specifically, it proposes a CPU+FPGA heterogeneous architecture to accelerate ANNs.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines.

Abstract: A circuit design support system, a circuit design support method, a circuit design support program, and a recording medium having the program recorded thereon are provided by which a design can be performed in consideration of the stochastic operation of the stochastic operation element and the influence caused by the stochastic operation of the stochastic operation element on the operation reliability of the circuit can be evaluated.

Abstract: This invention relates to an apparatus, system, and method for computing with neuromorphic circuit architectures that have neurons with interconnected internal state information. The interconnected internal state information allows the neurons to enable or strengthen the input to other neurons. Furthermore, neuron internal state information provides insights on the characteristics of the input data that can be used to enhance the performance of the neuromorphic system. The neuromorphic system can be implemented with an artificial phase-change-based neurons.

Abstract: A memory device may include a plurality of resistive elements and a control unit for controlling the memory device. The memory device is configured to program single weights of the memory device by groups of at least two resistive elements. A related method and a related computer program product may be also provided.