Abstract: A neuron circuit and an operating method thereof are disclosed. The neuron circuit may include an input unit to which an input pulse is applied, a bipolar memristor configured to have one end connected to one end of the input unit, a first capacitor configured to be connected between the one end of the bipolar memristor and a ground, a first diode configured to have an anode connected to the one end of the bipolar component, a second capacitor configured to have one end connected to a cathode of the first diode, a first switch configured to be connected between the one end of the second capacitor and the ground, and a second switch configured to be connected between the anode of the first diode and the other end of the second capacitor.

Abstract: A method of soft-decision decoding including training a machine learning agent with communication signal training data; providing to the trained machine learning agent a signal that has been received via a communications channel; operating the machine learning agent to determine respective probabilities that the received signal corresponds to each of a plurality of symbols; and, based on the determined probabilities, performing soft decision decoding on the received signal.

Abstract: A digital to analog converter is constructed using a neural network layer. The converter has inputs for receiving parallel bits of a digital input signal and an output for outputting an analog signal which is based on the digital input. Connecting the input and the output is a neural network layer which is configured to convert the parallel bits into an output analog signal that is representative of the digital input signal. The neural network may be hardwired and the synapses may rely on memristors as programmable elements.

Abstract: A neuromorphic device having a synapse array is provided. The synapse array of the neuromorphic device may include an input neuron; an output neuron; and a synapse. The synapse may include a plurality of ferroelectric field effect transistors electrically connected to each other in parallel.

Abstract: An optimization device includes: a state hold circuit that holds values of state variables included in an evaluation function that represents energy; an objective function calculation circuit that calculates an energy change value in an objective function included in the evaluation function for each of state transitions when a state transition occurs in response to a change in any of the values of the state variables; a constraint term calculation circuit that calculates a constraint term evaluation value, which is an evaluation value of a constraint term included in the evaluation function, for each of the state transitions; a temperature control circuit that controls a temperature value that indicates a temperature; and a transition control circuit that determines stochastically whether to accept any of the state transitions based on the temperature value, a random number value, and a sum of the change value and the constraint term evaluation value.

Abstract: A neuromorphic computing apparatus has a network of neuromorphic cores, with each core including an input axon and a plurality of neurons having synapses. The input axon is associated with an input data store to store an input trace representing a time series of filtered pre-synaptic spike events, and accessible by the synapses of the plurality of neurons of the core. Each neuron includes at least one dendritic compartment to store and process variables representing a dynamic state of the neuron. Each compartment is associated with a compartment-specific data store to store an output trace representing a time series of filtered post-synaptic spike events. Each neuron includes a learning engine to apply a set of one or more learning rules based on the pre-synaptic and post-synaptic spike events to produce an adjustment of parameters of a corresponding synapse to those spike events.

Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Abstract: Arithmetic circuits calculate d?1 energy values (hi2 to hid) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons including a first neuron whose output value is allowed to be updated and n-bit output values of n neurons. An adder circuit calculates a sum of these values, and a comparator circuit compares a value based on a sum of the sum and a noise value with a threshold, to determine the output value of the first neuron. An update circuit outputs n-bit updated output values in which one bit has been updated on the basis of a selection signal and the output value of the first neuron. The holding circuit holds the updated output values and outputs the updated output values as the n-bit output values used by the arithmetic circuits.

Abstract: In an information processing apparatus, a calculation circuit calculates energy values representing total energies of Ising devices that are set up with different noise widths, where the Ising devices have equal conditions about neuron-to-neuron connections. An exchange control circuit exchanges output values of neurons or noise widths, between first and second Ising devices having adjacent noise widths. This exchange takes place with an exchange probability based on a difference in the energy values between the first Ising device and the second Ising device.

Abstract: A neural network system comprises a plurality of neurons, comprising a layer of input neurons, one or more layers of hidden neurons, and a layer of output neurons. The system further comprises a plurality of arrays of weights, each array of weights being configured to receive a plurality of discrete data points from a first layer of neurons and to produce a corresponding discrete data point to a second layer of neurons during a feed forward operation, each array of weights comprising a plurality of resistive processing units (RPU) having respective settable resistances. The system includes a neuron control system configured to control an operation mode of each of the plurality of neurons, wherein the operation mode comprises: a feed forward mode, a back propagation mode, and a weight update mode.

Abstract: A synaptic circuit performing spike-timing dependent plasticity STDP interposed between a pre-synaptic neuron and a post-synapse neuron includes a memristor having a variable resistance value configured to receive a first signal from the pre-synaptic neuron. The circuit has an intermediate unit connected in series with the memristor for receiving a second signal from the pre-synaptic neuron and provides an output signal to the post-synaptic neuron. The intermediate unit receives a retroaction signal generated from the post-synaptic neuron and the memristor modifies the resistance value based on a delay between two at least partially overlapped input pulses, a spike event of the first signal and a pulse of the retroaction signal, in order to induct a potentiated state STP or a depressed state STD at the memristor. An electronic neuromorphic system having synaptic circuits and a method of performing spike timing dependent plasticity STDP by a synaptic circuit are also provided.

Abstract: An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.

Abstract: A method of controlling transistors includes receiving a control signal, and controlling the top and bottom gate biases of the transistors according to the control signal to normalize or randomize power drawn as observed outside of a core. A device for controlling transistors includes a core performing computational instructions, and a bias circuit receiving a control signal, the bias circuit controlling the top and bottom gate biases of the transistors according to the control signal to normalize or randomize power drawn as observed outside of the core.

Abstract: A computer-implemented method for detecting malware using machine learning may include (1) identifying data to be analyzed for malware, (2) classifying, using a classifier created by a combination of at least one deep learning neural network and at least one supervised data mining method, the data to be analyzed for malware, (3) determining, based on a predefined threshold, that the classification of the data indicates potential malware on the computing device, and (4) performing a security action based on the determination of potential malware on the computing device. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method and a circuit for generating a reference voltage are provided. The circuit includes: a first column of dummy neurons with weight 0 and a second column of dummy neurons with weight 1, wherein the plurality word-lines are connected to the dummy neurons in the first and second columns, respectively; a bit-line connected to a voltage source and the first column of dummy neurons; a complementary bit-line is connected to the voltage source and the second column of dummy neurons, wherein when the artificial neural network system is operated to sense the neurons of the memory cell array, one or more of the plurality of word-lines are activated, and the corresponding dummy neurons of the first column and the second column are activated to generate the reference voltage at the output end for sensing the neurons of the memory cell array.

Abstract: Technical solutions are described for implementing a neural network. An example system includes a crosspoint array including a plurality of nodes, each node representing a weight assigned to a neuron of the neural network. The system also includes a capacitor associated with a set of nodes from the plurality of nodes, where the capacitor is configured to store a current value corresponding to a sum of outputs from each respective node from the set of nodes. The system also includes a clocking circuit that initiates a forward pass to propagate the current value stored in the capacitor to a subsequent layer of the neural network. The clocking circuit further initiates a backward pass to propagate the current value stored in the capacitor to a preceding layer of the neural network. The clocking circuit further initiates a weight-update pass to update the weights in the neural network.

Abstract: A communications routing system, and method, for representing a plurality of predicted characteristics of a plurality of communications sources, each having an economic utility; representing a plurality of predicted characteristics of a plurality of communications targets each having an economic utility; and determining an optimal routing between the plurality of communications sources and the plurality of communications targets, by maximizing an aggregate utility with respect to the respective predicted characteristics of communications source and communications destination represented by linkages.

Abstract: A neural network has an array of interconnected processors, at least a first processor in the array operating in a pulse domain and at least a second processor in the array operating in a spike domain, and each said processor having: first inputs selectively coupled to other processors in the array of interconnected processors, each first input having an associated VCCS (a 1 bit DAC) coupled to a summing node, second inputs selectively coupled to inputs of the neural network, the second inputs having current generators associated therewith coupled to said summing node, a filter/integrator for generating an analog signal corresponding to current arriving at the summing node, and for processors operating in the pulse domain, an analog-to-pulse converter for converting an analog signal derived either directly from the filter/integrator or via a non-linear element, to the pulse domain, and providing the converted analog signal as an unquantized pulse domain signal at an output of each processor operating in the p

Abstract: The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling.

Abstract: An analog-digital crosspoint-network includes a plurality of rows and columns, a plurality of synaptic nodes, each synaptic node of the plurality of synaptic nodes disposed at an intersection of a row and column of the plurality of rows and columns, wherein each synaptic node of the plurality of synaptic nodes includes a weight associated therewith, a column controller associated with each column of the plurality of columns, wherein each column controller is disposed to enable a weight change at a synaptic node in communication with said column controller, and a row controller associated with each row of the plurality of rows, wherein each row controller is disposed to control a weight change at a synaptic node in communication with said row controller.

Abstract: In general, the invention is directed to a technique for selection of parameter configurations for a neurostimulator using neural networks. The technique may be employed by a programming device to allow a clinician to select parameter configurations, and then program an implantable neurostimulator to deliver therapy using the selected parameter configurations. The parameter configurations may include one or more of a variety of parameters, such as electrode configurations defining electrode combinations and polarities for an electrode set implanted in a patient. The electrode set may be carried by one or more implanted leads that are electrically coupled to the neurostimulator. In operation, the programming device executes a parameter configuration search algorithm to guide the clinician in the selection of parameter configurations. The search algorithm relies on a neural network that identifies potential optimum parameter configurations.

Abstract: A neural network has an array of interconnected processors, each processor operating either the pulse domain or spike domain.

Abstract: A timestamp neural network comprised of sensor elements, internal elements, and motor elements is responsive to timestamps. Sensor elements transform a wide variety of signals into events that trigger the updating of timestamps. Internal elements are responsive to timestamps. Motor elements convert timestamps into useful output signals. A real time video pattern recognition system is implemented.

Abstract: A pulse signal processing circuit, a parallel processing circuit, and a pattern recognition system including a plurality of arithmetic elements for outputting pulse signals and at least one modulation circuit, synaptic connection element(s), or synaptic connection means for modulating the pulse signals, the modulated pulse signals then being separately or exclusively output to corresponding signal lines.

Abstract: We develop a system consisting of a neural architecture resulting in classifying regions corresponding to users' keystroke patterns. We extend the adaptation properties to classification phase resulting in learning of changes over time. Classification results on login attempts of 43 users (216 valid, 657 impersonation samples) show considerable improvements over existing methods.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract: A current-mode pulse-width-modulation (PWM) circuit converts analog current signals into pulse signals. The PWM circuit includes a first I-V converter and one or more second I-V converters, each of the one or more second I-V converters being coupled to one of the current signals. Each of the first and second I-V converters is also coupled to a current generator which generates a current that linearly changes with time. For each of the first and second I-V converters, when a polarity of the input current thereof changes, an output changes between a high voltage level and a low voltage level. A logic circuit is coupled to the first and each second I-V converter to obtain a pulse signal that has a pulse width linearly proportional to the current level of the respective current signal.

Abstract: A multi-functional arithmetic apparatus with multi value-states comprise a gating array, which is composed of gating elements arranged in n row by m column. Each gating element has at least two input terminals and one output terminal, and has input value-states and output value-states. There is operational relationship between the input value-state and the output value-state according to the model of self-organizing principle of integer cluster. The output value-states determine the output based on the gating of the gating element, i.e. the mathematical manipulation is completed by the structure operation. The mathematical manipulation may be addition operation, subtract operation, mixed mode operation and bidirectional logic reversible operation implemented by one add operation and two subtract operations.

Abstract: An associative artificial neuron and method of forming output signals of an associative artificial neuron includes receiving a number of auxiliary input signals; forming from the auxiliary input signals a sum weighted by coefficients and applying a non-linear function to the weighted sum to generate a non-linear signal. The neuron and method further include receiving a main input signal and forming, based on the main signal and the non-linear signal, the function S OR V, which is used to generate a main output signal, and at lest one of three logical functions S AND V, NOT S AND V, and S AND NOT V. The at least one logical function is used to generate an additional output signal for the associative artificial neuron.

Abstract: The present invention relates to the field of computer science and can be used for neural network emulation and digital signal processing. Increasing of the neural processor performance is achieved using the ability to change word lengths of results in program mode. The neural processor includes six registers, a shift register, a AND gate, two FIFOs, a switch, a multiplexer, two saturation units, a calculation unit and a adder circuit to execute operations over vectors of programmable word length data. Increasing of the saturation unit performance is achieved using the ability to process vector of input operands with programmable word length at a time. Increasing of the adder circuit performance is achieved using ability to sum two vectors of input operands of programmable word lengths.

Abstract: The neural semiconductor chip first includes: a global register and control logic circuit block, a R/W memory block and a plurality of neurons fed by buses transporting data such as the input vector data, set-up parameters, etc., and signals such as the feed back and control signals. The R/W memory block, typically a RAM, is common to all neurons to avoid circuit duplication, increasing thereby the number of neurons integrated in the chip. The R/W memory stores the prototype components. Each neuron comprises a computation block, a register block, an evaluation block and a daisy chain block to chain the neurons. All these blocks (except the computation block) have a symmetric structure and are designed so that each neuron may operate in a dual manner, i.e. either as a single neuron (single mode) or as two independent neurons (dual mode). Each neuron generates local signals.

Abstract: A neural network circuit is provided having a plurality of circuits capable of charge storage. Also provided is a plurality of circuits each coupled to at least one of the plurality of charge storage circuits and constructed to generate an output in accordance with a neuron transfer function. Each of a plurality of circuits is coupled to one of the plurality of neuron transfer function circuits and constructed to generate a derivative of the output. A weight update circuit updates the charge storage circuits based upon output from the plurality of transfer function circuits and output from the plurality of derivative circuits. In preferred embodiments, separate training and validation networks share the same set of charge storage circuits and may operate concurrently.

Abstract: A neuron circuit including means for synaptic modification is described. The circuit emulates the electrical behaviors of the neuron membrane, dendrite, and synapse, using principles based on the actual biology. In one embodiment, the circuit is implemented as an analog very large scale integrated (VLSI) circuit which utilizes CMOS integrated circuit technology. The analog VLSI circuit includes a synapse circuit having a circuit portion which models a mechanism for the modification of the synaptic conductance.

Abstract: Detection is implemented by a multiplier, a lookup table or other apparatus with two inputs, one of which typically receives an input signal from a sensor, and the other a reference or weighting factor W stored or generated locally. The detected value is added to the contents of a memory location A after the previous contents of memory locations A have been modified by a loss or gain factor Q. Memory location A is one of several such memory locations in a shared memory simultaneously accessible by an external user. In a neural engine the memory locations represent neurons. For each cycle of operation of the neural engine a new value of W, Q and A are provided.

Abstract: A semiconductor arithmetic circuit which compares the magnitudes of a plurality of data with each other in real time by using a simple circuit. The semiconductor arithmetic circuit containing one or more neuron MOS transistors each having a plurality of input gate electrodes has an inverter circuit group of a plurality of inverter circuit each of which is constituted of neuron MOS transistors and a means for applying a prescribed signal voltage to at least one first input gate of the inverter circuit.

Abstract: A method for generating fault classification signals which identify faulty loops which develop in a multiphase energy supply network observed in the event of a fault from a protective device with a starting arrangement. To be able to generate such fault classification signals in a relatively simple manner, a neural network is used which is trained using input variables simulating faulty loops in the form of normalized resistance and reactance variables formed taking into consideration the starting characteristic of the starting arrangement. In the case of a fault, normalized resistance and reactance measured variables network for generating fault classification signals.

Abstract: Each neural element of a column-structured recurrent neural network generates an output from input data and recurrent data provided from a context layer of a corresponding column. One or more candidates for an estimated value is obtained, and an occurrence probability is computed using an internal state by solving an estimation equation determined by the internal state output from the neural network. A candidate having the highest occurrence probability is an estimated value for unknown data. Thus, the internal state of the recurrent neural network is explicitly associated with the estimated value for data, and a data change can be efficiently estimated.