Layout (e.g., Circuit, Construction) Patents (Class 706/921)
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Patent number: 9864739Abstract: A method provides automatic layout of GUI screens based on contents of a response to a resource request. A display format is selected based on whether a resource in the response includes only a single data object (form display format) or an array of data objects (table display format). A specification is then created for a display object of the selected display format to be rendered on a GUI screen. For the form display format, the specification includes label:value pairs and location information specifying locations for the pairs in form columns. For the table display format, the specification includes a table definition (number of columns, column headings etc.) and row data values for the data objects of the array. Values are arranged in a display order of the resource fields in the response.Type: GrantFiled: March 13, 2013Date of Patent: January 9, 2018Assignee: EMC IP Holding Company LLCInventors: Bruce R. Rabe, Scott E. Joyce, Norman M. Miles
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Patent number: 9619608Abstract: The present disclosure relates to a system and method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include recording, at a client computing device, a plurality of operations associated with an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include generating a script based upon, at least in part, the recorded operations and displaying, at the client computing device, at least a portion of the generated script.Type: GrantFiled: August 27, 2015Date of Patent: April 11, 2017Assignee: Cadence Design Systems, Inc.Inventors: Patrick Bernard, Sean Bergan
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Patent number: 9418194Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.Type: GrantFiled: August 11, 2014Date of Patent: August 16, 2016Assignee: ASML NETHERLANDS B.V.Inventors: Taihui Liu, Been-Der Chen, Yen-Wen Lu
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Patent number: 8817102Abstract: A device which can support a determination of a camera layout by automatically preparing the camera layout that satisfies a customer request based on the customer request including a surveillance layout. Specifically, a need table that is a data set of a plurality of arrangement candidate cameras satisfying the customer request is prepared from the customer request including the surveillance layout. An arrangement of the plurality of the arrangement candidate cameras on a map is calculated based on the need table using a clustering method and a temporary layout of cameras is prepared. Then, an arrangement layout of the cameras in the surveillance layout is determined based on the temporary layout.Type: GrantFiled: June 28, 2011Date of Patent: August 26, 2014Assignee: Hitachi, Ltd.Inventors: Takashi Saeki, Ryo Yumiba, Masaya Itoh, Takao Sukegawa, Yasuhiro Suda, Masanori Miyoshi
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Patent number: 8049762Abstract: Architectural structure design methods, architectural structure design apparatuses, and articles of manufacture are described according to some aspects of the disclosure. In one aspect, an architectural structure design method includes responsive to user input, modifying a visual representation of an architectural structure, wherein the visual representation comprises an object of the architectural structure, first displaying the visual representation comprising the object at a first moment in time, wherein the object is positioned at a first location of a display screen, responsive to user input, selecting an attribute for the object from a second location of the display screen which is different than the first location of the display screen, responsive to user input, associating the attribute with the object after the selecting, and displaying the visual representation comprising the object having the attribute at a second moment in time after the associating.Type: GrantFiled: January 13, 2006Date of Patent: November 1, 2011Assignee: Chief Architect, Inc.Inventors: Gregory Wells, Jason Troye, Dermot Dempsey
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Patent number: 7657416Abstract: A method of system design, and more particularly a method of designing systems that achieve a set of performance goals using a hierarchically partitioned system representation wherein performance simulations are performed at multiple levels within the hierarchy and are combined to simulate a system level result in order to reduce the aggregate time required for performance simulation.Type: GrantFiled: August 12, 2005Date of Patent: February 2, 2010Assignee: Cadence Design Systems, IncInventors: Pero Subasic, Enis Aykut Dengi
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Patent number: 7337154Abstract: A recursive binary splitting and recombination procedure coupled with a specially tailored genetic algorithm provides a solution to the general binary minimization problem with much lower run times than other methods. A minor modification to the procedure solves a variant of the binary minimization problem using an alternate operator logic that is crucial to solving certain combinatorial geometry problems.Type: GrantFiled: May 4, 2004Date of Patent: February 26, 2008Assignee: Raytheon CompanyInventor: Steven J Manson
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Patent number: 7024636Abstract: A method and system for automatically guiding a user through a design flow for an integrated circuit are disclosed. The method and system include displaying a design flow user interface on a user's computer, where the user interface includes symbols corresponding to design flow process steps. The design flow process steps are defined with a set of rules, and user input for each step is analyzed for compliance with the rules. The user is allowed to proceed to a next step in the flow once it is determined that the previous steps have been completed successfully.Type: GrantFiled: November 20, 2002Date of Patent: April 4, 2006Assignee: LSI Logic CorporationInventor: Dan Weed
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Patent number: 7020852Abstract: An automated framework and methodology for the development, testing, validation, and documentation of the design of semiconductor products that culminates in the release of a design kit having a flow manager and flow file to actualize a methodology to design a semiconductor product. The flow framework and methodology receives a methodology and a technology description for the semiconductor product. Then the flow framework and methodology coordinates and tests flow files developed by flow developers using testcases from testcase developers, libraries from library developers and tools from tool from flow developers that may be constantly updated. When a flow file, a testcase, a library, and/or a tool is updated, added, or otherwise changed, ongoing regression testing is accomplished to update the correct flow file.Type: GrantFiled: May 8, 2003Date of Patent: March 28, 2006Assignee: LSI Logic CorporationInventors: Bret Alan Oeltjen, Scott Allen Peterson, Donald Ray Amundson, Richard Karl Kirchner
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Patent number: 6968517Abstract: A method of interactively determining at least one optimized design candidate using an optimizer, the optimizer having a generation algorithm and an objective function, the optimized design candidate satisfying a design problem definition, comprises generating design candidates based on the generation algorithm. The generated design candidates are added to a current set of design candidates to form a new set of design candidates. The design candidates are evaluated based on the objective function so that design candidates can be selected for inclusion in a preferred set of design candidates. The current state of the optimizer is presented to a designer for interactive examination and input is received from the designer for updating the current state of the optimizer. These steps are repeated until a stopping criterion is satisfied.Type: GrantFiled: November 7, 2002Date of Patent: November 22, 2005Assignee: Synopsys Inc.Inventor: Trent Lorne McConaghy
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Publication number: 20040254906Abstract: A resource board for a circuit emulator holds programmable logic devices (PLDs) and other emulation resources such as random access memories (RAMs) and employs both hard-wired and network-based virtual signal paths to flexibly route signals between the emulation resources on the resource board and resources mounted on other resource boards, workstations and other external equipment. The resource board also provides the logic and balanced signal paths needed to deliver clock signals to the PLDs and reduces the number of signals needed to communicate with external test equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit.Type: ApplicationFiled: December 11, 2003Publication date: December 16, 2004Inventors: Sweyyan Shei, Ming Yang Wang, Vincent Chiu, Neu Choo Ngui
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Patent number: 6751735Abstract: An apparatus and method provide a controlled, dynamically loaded, modular, cryptographic implementation for integration of flexible policy implementations on policy engines, and the like, into a base executable having at least one slot. The base executable may rely on an integrated loader to control loading and linking of fillers and submodules. A policy module may be included for use in limiting each module's function, access, and potential for modification or substitution. The policy may be implemented organically within a manager layer or may be modularized further in an underlying engine layer as an independent policy, or as a policy created by a policy engine existing in an engine layer. The policy module is subordinate to the manager module in the manager layer in that the manager module calls the policy module when it is needed by the manager module. The policy module is preferably dynamically linkable, providing flexibility, and is layered deeper within the filler module than the manager module.Type: GrantFiled: May 26, 1999Date of Patent: June 15, 2004Assignee: Novell, Inc.Inventors: Roger R. Schell, Kevin W. Kingdon, Thomas A. Berson, Robert R. Jueneman
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Patent number: 6424959Abstract: The present invention consists of a method and apparatus for the automatic creation of the topology, component sizing, placement, and routing of complex structures, such as electronic circuits or mechanical systems, to satisfy prespecified high-level design goals. The present invention uses a population of entities which are evolved over a series of generations by an iterative process involving the application of operations, such as mutation, crossover, reproduction, and architecture-altering operations. The individuals in the population are each developed, in a developmental process, into a structure that may potentially satisfy the design goals. The present invention also determines the placement of components within the developing structure and determining the routing of the connecting means (wires for electrical circuits) between the components.Type: GrantFiled: June 17, 1999Date of Patent: July 23, 2002Inventors: Forrest H. Bennett, III, John R. Koza
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Patent number: 6292766Abstract: The present invention is a simulation tool input file generator implemented in a computer system that permits a designer to efficiently and effectively create and modify electrical circuit simulation tool input files. The simulation tool input file generator permits a user to conveniently enter high level circuit description information in user friendly formats such as an easy to use GUI. Based upon the information provided by a user, the present invention assembles data including circuit description files stored in a memory and produces a detailed simulation tool input files.Type: GrantFiled: December 18, 1998Date of Patent: September 18, 2001Assignee: VLSI Technology, Inc.Inventors: Derwin Mattos, Henry Jen, Saeid Moshkelani
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Patent number: 6283759Abstract: Compliance with a standard is demonstrated by displaying a floor plan on a first computer. The displayed floor plan includes designated areas. Each designated area includes a corresponding communication link, and the designated areas are regulated by the standard. A message is transmitted to a second computer in response to selection of one of the designated areas by a user on the first computer. The message is dependent upon the communication link corresponding to the selected designated area and causes compliance information to be downloaded by the second computer to the first computer. The compliance information is displayed on the first computer and demonstrates that the selected designated area is in compliance with the standard.Type: GrantFiled: November 13, 1998Date of Patent: September 4, 2001Inventors: James R. Price, Karl W. Fronczke
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Patent number: 5892678Abstract: An improved LSI design automation system includes: an input unit, a circuit component storage unit, a circuit component selection unit, a design method decision unit, a design process unit, and a component entry unit. The input unit receives LSI function and performance information as a requirements specification and LSI component configuration information. The circuit component storage unit collectively stores a circuit data item, design method information items, and performance information items, as a circuit component. The circuit component selection unit selects a circuit component from the circuit component storage unit for implementation of a desired circuit. The design method decision unit selects an optimum design method information item from the design method information items held by each circuit component. The design process unit generates, modifies, and evaluates a circuit.Type: GrantFiled: October 3, 1997Date of Patent: April 6, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Seiji Tokunoh, Noriko Matsumoto, Tamotsu Nishiyama