Plural Complete Computers Patents (Class 708/104)
  • Patent number: 11010309
    Abstract: A computer system for executing one or more software applications includes a host computer device configured to execute the one or more software applications. The computer system further includes one or more memory devices configured to cryptographically protect volatile memory of the one or more memory devices. The one or more memory devices are configured to provide access to the cryptographically protected volatile memory for the one or more software applications. The host computer device is configured to execute the one or more software applications by executing a portion of the one or more software applications associated with the cryptographically protected volatile memory using a processor of the one or more memory devices.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Somnath Chakrabarti, Mona Vij, Matthew Hoekstra
  • Patent number: 10176621
    Abstract: A set of graphics primitive information for a virtual object may be processed with compute shader running on a graphics processing unit (GPU) to generate a modified set of primitive information. The modified set of primitive information may be passed to a vertex shader running on the GPU. The vertex shader may perform vertex shading on the modified set of primitive information. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: January 8, 2019
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Mark Evan Cerny, David Simpson, Jason Scanlin
  • Patent number: 10007651
    Abstract: In an embodiment, a document error handling method is disclosed. The document error handling method may include or comprise accessing an electronic document that includes or comprises a plurality of data fields, identifying a plurality of errors associated with the electronic document, and accessing a data field from among the plurality of data fields, wherein the data field corresponds to a selected error from among the plurality of errors. The document error handling method may also include or comprise editing the data field in response to an error editing input to thereby enable an elimination of the selected error.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: June 26, 2018
    Inventor: Jens Straten
  • Patent number: 8996595
    Abstract: A method of executing a dynamic clock and voltage scaling (DCVS) algorithm in a central processing unit (CPU) is disclosed and may include monitoring CPU activity and determining whether a workload is designated as a special workload when the workload is added to the CPU activity.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: March 31, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Norman Scott Gargash, Brian J. Salsbery
  • Patent number: 8856196
    Abstract: A multi core system for allocating a task generated from a control system program to an appropriate CPU core and executing the task includes a trial-execution instructing part configured to cause a second CPU core to trial-execute a task which a first CPU core executes before the multi core system transfers the task from the first CPU core to the second CPU core and causes the second CPU core to execute the task, a determining part configured to determine whether an execution result by the first CPU core matches an execution result by the second CPU core, and an allocation fixing part configured to fix the second CPU core as the appropriate CPU core to which the task is allocated if the determining part determines that the execution result by the first CPU core matches the execution result by the second CPU core.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: October 7, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Kazumi Yamada
  • Publication number: 20130239122
    Abstract: The invention provides hardware logic based techniques for a set of processing tasks of a software program to efficiently communicate with each other while running in parallel on an array of processing cores of a multi-core data processing system dynamically shared among a group of software programs. These inter-task communication techniques comprise, by one or more task of the set, writing their inter-task communication information to a memory segment of other tasks of the set at the system memories, as well as reading inter-task communication information from their own segments at the system memories. The invention facilitates efficient inter-task communication on a multi-core fabric, without any of the communications tasks needing to know whether and at which core in the fabric any other task is executing at any given time. The invention thus enables flexibly and efficiently running any task of any program at any core of the fabric.
    Type: Application
    Filed: April 26, 2013
    Publication date: September 12, 2013
    Inventor: Mark Henrik Sandstrom
  • Patent number: 8407531
    Abstract: A technique for collecting and correlating locking data collects and correlates information on a plurality of programs waiting on or holding a plurality of resources in a multi-computer database system. The technique identifies a program executing on one computer of the multi-computer database system that is waiting on a resource. The technique also identifies a second program, executing on another computer, as the ultimate holder of the resource. An operator display screen displays information corresponding to the first program and the second program. The operator display screen may be switched between a multiline display format and a single line display format. The collection, identification, and display of the locking data is performed periodically, to allow the operator to discover locking problems and take a desired corrective action.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: March 26, 2013
    Assignee: BMC Software, Inc.
    Inventors: Loc D. Tran, Gary B. Genest, Dale J. Stroyick
  • Publication number: 20120110047
    Abstract: A method for scheduling a data processing job includes receiving the data processing job formed of a plurality of computing units, combining the plurality of computing units into a plurality of sets of tasks, each set including tasks of about equal estimated size, and different sets having different sized tasks, and assigning the tasks to a plurality of processors using a dynamic longest processing time (DLPT) scheme.
    Type: Application
    Filed: November 15, 2010
    Publication date: May 3, 2012
    Applicant: International Business Machines Corporation
    Inventors: Kirsten W. Hildrum, Rohit M. Khandekar, Vibhore Kumar, Sujay S. Parekh, Deepak Rajan, Joel L. Wolf, Kun-Lung Wu
  • Patent number: 8166518
    Abstract: A computer implemented method provides remote access to a plurality of sessions at a computer. The method includes initiating a master process in a context independent from the sessions, establishing a first slave process in a context of a first session, and maintaining communication between the master process and the first slave process. The master process provides access to the computer's display while the display is under control of the first session, detects a second session, having a respective second slave process, communicates with the second slave process, and provides access to the computer's display while the display is under control of the second user session.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: April 24, 2012
    Assignee: Netopia, Inc.
    Inventors: Michael Byron Price, Marc A. Epard, Donald W. Griffin
  • Patent number: 7974405
    Abstract: In an input process, a circuit and an input bit to the circuit are inputted to a plurality of computers. Firstly, one computer performs calculation and transmits the calculation result to another computer of the computers. Next, the another computer which has received the calculation result performs the next calculation. Thus, calculation is performed by one computer after another. When all the computers have performed calculation once, the last computer which has performed calculation transmits the calculation result to the first computer which has performed calculation. After this, calculation is performed by one computer after another and the calculation result is transmitted to the next computer, thereby repeating the calculation of each cycle. Thus, it is possible to realize calculation of a value of a given function by using a device including a plurality of computers, with a simpler configuration.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: July 5, 2011
    Assignee: NEC Corporation
    Inventors: Jun Furukawa, Isamu Teranishi
  • Patent number: 6352504
    Abstract: A device is provided for monitoring patients, which is used to detect and process physiological data of a patient, which are measured by sensors. To make possible the most flexible use possible in patient monitoring, especially the connection of additional special sensors (2) and to ensure simple handling of the device even in the case of transportation, the patient monitoring device has a transportable terminal (8), which has connections (18) for connection to sensors (2) for measuring physiological parameters of the patient and signal processing devices (31, 23, 24, 25) for receiving and processing the sensor signals received, and is provided with a network adapter (26) for forwarding the processed sensor data to a stationary medical workplace (14) with display and alarm devices, as well as one or more expansion modules (9) for the connection of additional desired sensors (2).
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: March 5, 2002
    Assignee: Dräger Medizintechnik GmbH
    Inventors: Edgar Ise, Rob Spapens, Christoph Landowski, Markus Rechlin