Abstract: A control signal for controlling a light emitting device is PWM modulated in time, the PWM modulation comprising PWM pulses and PWM periods. The PWM pulse instantaneous frequency of a PWM pulse is the reciprocal of the instantaneous PWM period of the PWM pulse. The PWM pulse instantaneous frequency depends on the PWM duty cycle of the PWM pulses of the control signal. The PWM pulse instantaneous frequency of the PWM pulses is a first PWM pulse instantaneous frequency at a first PWM duty cycle of the control signal, and is a second PWM pulse instantaneous frequency at a second PWM duty cycle of the control signal. In an operating condition, the first PWM duty cycle is less than the second PWM duty cycle and the first PWM pulse instantaneous frequency is less than the second PWM pulse instantaneous frequency.

Abstract: A jitter generator may include a duty cycle code generator that generates a duty cycle control signal and an input buffer that outputs a signal based on its duty cycle. The input buffer may be coupled to the duty cycle code generator and to a source of a clock signal. After receiving the clock signal, the input buffer outputs the clock signal having jitter relative to the clock signal received from the source. The jitter may be added at least in part by components of the input buffer offsetting different transitions of the clock signal according to the duty cycle. Jitter may be added when the duty cycle changes in response to changes in the duty cycle control signal, such as in response to number generator circuitry of the duty cycle code generator update its output number, in response to a mode change received from a controller, or the like.

Abstract: An example method of clock and data recovery (CDR) includes adding a pre-defined offset to an output of a phase detector (PD) of a CDR circuit, and loading an accumulator of a frequency loop of the CDR circuit with a pre-defined load value. The method further includes detecting the phase of an incoming signal using a PD, and determining that the CDR has locked onto a real lock point. In some examples, the method further includes determining that the CDR has locked on a real lock point, and, in response to the determination, modifying the pre-defined offset to equal zero.

Abstract: A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2? radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e.

Abstract: Apparatus and methods for disrupting or preventing periodicity in DTC circuits are provided. In an example, a communication circuit can include a digital-to-time converter (DTC) and a processing path coupled to the DTC. The DTC can be configured to receive reference information, modulation information and first dither information, and to provide a modulated signal using the reference information, the modulation information and the first dither information. The processing path can be configured to receive second dither information and to cancel the first dither information using the second dither information, wherein the DTC is configured to disrupt processing periodicity of the communication circuit using the first dither information.

Abstract: A phase deviation method determines an offset between a reference and suspect signal by analyzing a phase deviation surface created by computing a deviation metric for phase shift and then analyzing a surface formed from the deviation metrics for an array of offsets. The phase deviation method analyzes the deviation surface to determine an offset that minimizes phase deviation. This method is applied at increasing levels of detail to refine the determination of the offset.

Abstract: Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.

Abstract: A phase coherent signal generator apparatus is disclosed that outputs a coherent continuous phase signal that includes fast switched multiple different frequency bursts. The apparatus comprises: a clock generator including an input to receive a reference clock signal, and outputs to independently supply a master clock signal and a slave clock signal; an accumulating digital synthesizer that includes independent inputs to receive the slave clock signal, a digital frequency tune word signal, a phase tune word signal, and a reset signal, and an output that supplies a digital coherent continuous phase signal; a master digital synthesizer that includes independent inputs to receive the master clock signal and the digital frequency tune word signal, and independent outputs to supply the digital phase tune word signal and the reset signal; and a converter that receives the digital coherent continuous phase signal and supplies the coherent continuous phase signal.

Abstract: One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.

Abstract: A phase coherent signal generator apparatus is disclosed that has fast frequency shifting and numerous phase memory points, outputting a coherent continuous phase signal that includes fast switched multiple different frequency bursts.

Abstract: A terminal device includes a central processing unit, a data memory, a first selector, and a digital-to-analog conversion module. The data memory includes a first data storage apparatus and a second data storage apparatus. A first output end of the central processing unit is connected to an input end of the first selector. A second output end of the central processing unit is connected to a gating end of the first selector. An output end of the second data storage apparatus is connected to an input end of the digital-to-analog conversion module. The digital-to-analog conversion module is configured to send repeatedly a periodic signal to a receiving device within a sending time.

Abstract: A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.

Abstract: A phase estimation method estimates the phase of signal components using a point spread function. The method obtains a point spread function that expresses complex frequencies at a non integer location in terms of integral frequencies, for a complex frequency of a signal at a non integer location in a complex frequency domain. It obtains complex frequencies of the signal for the integral frequencies, and computes a sum of products of the complex frequencies of the signal at the integral frequencies with the corresponding complex values of the point spread function to provide an estimate of phase of the signal at the non integer location.

Abstract: A spurious frequency attenuation servo is provided. The spurious frequency attenuation servo includes a first function generator that generates a first signal at a first frequency and at a spurious frequency; a second function generator that generates a second signal in-phase with the first signal and at the spurious frequency; a third function generator that generates a third signal ninety degrees out-of-phase with the first signal and at the spurious frequency; in-phase and quadrature-phase mixers to input a feedback signal and the second and third signals, respectively; in-phase and quadrature-phase error accumulators; an in-phase and quadrature-phase multiplier to multiply an output from the in-phase and quadrature-phase error accumulators with the second and third signals, respectively; and a summing node to sum the first signal with output from the in-phase and quadrature-phase multipliers to form an output signal that is fed back to the in-phase mixer and the quadrature-phase mixer.

Abstract: Techniques and architecture are disclosed for improving spurious performance in a signal generator/system. The disclosed techniques/architecture can be used, for example, to enhance/improve the wideband and/or narrowband spurious free dynamic range (SFDR) between a given carrier signal and spurious signals. In some example instances, wideband and/or narrowband SFDR may be improved to about ?40 dBc or better. In some other example instances, wideband and/or narrowband SFDR may be improved to about ?70 dBc or better. The disclosed techniques/architecture can be implemented in a wide variety of signal generators/systems, such as a direct digital synthesizer (DDS)-based system, and over a wide range of input clock frequencies (e.g., in the range of about 10 MHz to 40 GHz, or higher).

Abstract: A method for implementing variable symbol rate, presetting counters M and N, and M=1, N=0, f being the preset output symbol rate, fs being the frequency of input clock, the method comprises: triggering to judge whether N×f is greater than M×fs at the rising edge of the input clock, if it is, letting the counter M add 1 and outputting a clock pulse; else further judging whether the value of the counter N is equal to fs?1; when N=fs?1, letting the counter N return to 0, and waiting for the next rising edge of the input clock; when N?fs?1, waiting for the next rising edge of the input clock after letting the counter N add 1; letting the output clock pulse be the system clock, controlling the data to be output to set the symbol rate output.

Abstract: A jitter generator for generating a jittered clock signal, includes a jitter control signal generator and a jittered clock generator. The jitter control signal generator is utilized for selecting a digital control code from a plurality of candidate digital control codes at individual time points and respectively outputting a plurality of selected digital control codes. The jittered clock generator is coupled to the jitter control signal generator, and utilized for generating the jittered clock signal. The jittered clock generator dynamically adjusts the jittered clock signal according to the plurality of different digital control codes.

Abstract: A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.

Abstract: An integrated circuit for providing digital frequency synthesis is disclosed. For example, the integrated circuit comprises a phase detector for receiving a reference clock signal and an oscillator clock signal, wherein the phase detector outputs an error signal. The integrated circuit further comprises a synthesizer control block, coupled to the phase detector, for receiving the error signal to generate a delay select signal, wherein the synthesizer control block comprises an integral adjustment filter and a proportional adjustment filter.

Abstract: A method for reducing signal edge jitter in an output signal from a numerically controlled oscillator includes processing an input signal with a first accumulator to provide a first accumulator output signal and continuing to use a carry in the processing of the input signal with the first accumulator in the event of an overflow. The method further includes processing the input signal with a second accumulator to provide a second accumulator output signal and rejecting a carry in the processing of the input signal with the second accumulator in the event of an overflow. The method further includes outputting the second accumulator output signal at an output of the numerically controlled oscillator and synchronizing the second accumulator using the first accumulator output signal.

Abstract: A delta-sigma modulator includes: a loop filter for processing an analog input signal and a feedback signal to generate a filtered signal; a noise coupler operable to generate a noise coupled signal based on the filtered signal and the feedback signal; a quantizer for quantizing the noise coupled signal to generate a digital output signal; and a digital-to-analog converter converting the digital output signal to the feedback signal. The noise coupler includes an amplifier that has an inverting input terminal receiving a difference between the filtered signal and the feedback signal, and a non-inverting output terminal outputting the noise coupled signal, and a capacitor coupled between the inverting input terminal and the non-inverting output terminal of the amplifier.

Abstract: An apparatus and method for operating a frequency synthesizer wherein a value of an first control signal associated with a fine frequency feedback loop connected to a signal generator is monitored, and a second control signal associated with a medium or coarse frequency feedback loop connected to the signal generator is adjusted based on the monitoring. The first and second control signals are then output to control the frequency synthesizer.

Abstract: A frequency synthesizer for generating a low noise and low jitter timebase of a reference signal generates first and second output signals a difference frequency that is low enough for use in sub-scanning is implemented with a first incrementer, having a preset increment and a preset end value E1 controlling a first fractional divider and a second incrementer having a preset increment and a present end value E2 controlling a second fractional divider, wherein each of the incrementers is clocked from the output signal of each fractional divider so that, when the end value E1, E2 is reached, an end signal is output and the incrementers are reset to a carryover value as a new starting value and the end signal is switched between the division factors of the fractional dividers so that the switching sequence of the end signal is periodic with the output signals of the fractional dividers.

Abstract: Filter banks may have different structures and different individual output signal domains. Often a translation between different filter bank domains is desirable. Usually, mapping matrices are used that, however, vary over frequency. This requires a significant amount of lookup tables. A method for transforming first data frames of a first filter bank domain to second data frames of a different second filter bank domain, comprises steps of transcoding sub-bands of the first filter bank domain into sub-bands of an intermediate domain that corresponds to said second filter bank domain but has warped phase, and transcoding the sub-bands of the intermediate domain to sub-bands of the second filter bank domain, wherein a phase correction is performed on the sub-bands of the intermediate domain.

Abstract: A DDS system is disclosed that is configured to provide a variable clock delay that allows timing of data coming out of the ROM to be adjusted. In one example case, a DDS system is provided that includes a ROM for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values, and delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system. The delay circuitry may include, for instance, delay elements that can be selected alone or in combination to adjust the timing. The timing can be adjusted, for example, by adjusting delay of a clock signal that clocks one or more ROM pipeline registers. The system may include a phase accumulator and DAC, and adjusting the timing may include adjusting delay of a clock signal that clocks one or more DAC pipeline registers.

Abstract: An output signal is generated from a received input data stream representing a sequence of digital data values. For each group of successive data values in the sequence of data values, a respective waveform pattern is assigned in dependence of the data content of the respective group of successive data values. The output signal is generated by generating the assigned respective waveform patterns corresponding to the input data stream.

Abstract: Data rate conversion devices and methods are provided. A method for converting a first digital signal having a first sampling rate into a second digital signal having a sampling rate close to a predetermined second sampling rate comprises the following operations: when the ratio of the first sampling rate to the second sampling rate is a repeating infinite decimal, calculate at least two calibrating coefficient values and output the calibrating coefficient values according to a predetermined rule; conduct overflow operation on the output calibrating coefficient; and interpolate the first digital signal using the output calibrating coefficient and the result of the overflow operation to obtain the second digital signal such that during any period of a certain length along time axis, sampling times of the second digital signal equals to sampling times of the second sampling rate.

Abstract: A system and method are provided for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers. The method accepts a plurality (k) of reference frequency values (fri), where 1?i?k, associated with a corresponding plurality of synthesized frequency values (foi). For each synthesized frequency value, a raw ratio of integers Nprawi and Dprawi is calculated, such that: f o i = Np raw i Dp raw i × f r i . A greatest common divisor (GCD) of Nprawi and Dprawi and a primitive ratio of integers Np i Dp i is found for each raw ratio of integers, such that: N p i = Np raw i GCD ? ( Np raw i , Dp raw i ) ; and , ? D p i = Dp raw i GCD ? ( Np raw i , Dp raw i ) .

Abstract: The electronic circuit arrangement is used for generating poly-phase sequences as synchronization sequences and/or reference sequences in radio communications systems. It comprises a first adder, a first multiplier, a first register, a second register, a first counter and a trigonometry device. The first adder adds a value (km) formed from the value (k) of the counter to the value (B) of the first register. The first multiplier multiplies the value (A) of the second register by a value (y) formed from the value (B) of the first register and the value (k) of the counter. The trigonometry device forms the real part and the imaginary part of the present value of the poly-phase sequence (ak) from a value formed at least from the output value (wk) of the first multiplier.

Abstract: An RF transceiver apparatus comprises transmitter circuitry arranged to convert signals from a baseband frequency to RF transmission frequencies and receiver circuitry arranged to convert signals from RF reception frequencies to the baseband frequency. The transmitter and receiver circuitry each comprise three mixers arranged to convert a signals between the baseband frequency, a first intermediate frequency; a second intermediate frequency that is higher than the transmission frequencies; and a second intermediate frequency to the transmission frequency.

Abstract: A method is provided for synthesizing signal frequencies using low resolution rational division decomposition in a frequency synthesis device. An integer numerator (n) and an integer denominator (d) ratio is reduced; n/d=IO(NO/DO)=IO+NO/DO=(IO+1)?(DO?NO)/DO, and where NO/DO<1 and NO and DO are integers. NO is reduced; NO=In(Nn/Dn)=In+Nn/Dn=(In+1)?(Dn?Nn)/Dn, where In, Nn, and Dn are integers, and Nn/Dn<1. In, Nn, and Dn are used to create a final numerator divisor. DO is reduced; DO=Id(Nd/Dd)=Id+Nd/Dd=(Id+1)?(Dd?Nd)/Dd, where Id, Nd, and Dd are integers, and Nd/Dd<1. Id, Nd, and Dd are used to create a final denominator divisor. Finally, IO, the final numerator divisor, and the final denominator divisor are used to create a final divisor.

Abstract: A method for use in a digital frequency synthesizer, the method comprising phase to amplitude conversion of an output value of a phase accumulator in said synthesizer, said conversion being carried out as an approximation (y) of a phase value (x) which corresponds to said output amplitude value, the method being characterized in that the approximation comprises a combination of a linear interpolation value and a second order sinusoidal value, the second order sinusoidal value being used as an error term to correct for errors in the linear interpolation value.

Abstract: A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q<1 (decimal). The numerator (p) and the denominator (q) are supplied to a flexible accumulator module, and a divisor is generated as a result. N is summed with a k-bit quotient to create the divisor. In a phase-locked loop (PLL), the divisor and the reference signal are used to generate a synthesized signal having a frequency equal to the synthesized frequency value.

Abstract: A technique for the suppression of spurious Direct Digital Synthesis (“DDS”) signals includes a method and an apparatus that equally and oppositely dithers a pair of complementary input digital words from which a pair of analog signals are direct digital synthesized and then mixes the generated analogy signals.

Abstract: A direct digital synthesis is provided with added circuitry to reduce jitter in an IC so that a programmable frequency output can be provided near the limits of the IC system clock with minimal jitter. The system derives the quotient Q as a remainder R in an accumulator at the instant of an overflow, divided by a programmable input N. The quotient Q is subjected to conversion logic that can be provided by a fast parallel to serial converter such as, for example a multi-gigabit transceiver (MGT) of an FPGA. As an alternative to an MGT, a series of delay devices such as found in a carry chain can be used if calibration is performed to assure the accuracy of delays.

Abstract: A system, method, and apparatus for distortion analysis is provided. A method in accordance with at least one embodiment of the present disclosure may include receiving a clock frequency at a direct digital synthesizer (DDS) and generating at least one stream of phase numbers via said DDS. The method may further include generating a digital sine wave using, at least in part, said clock frequency and said at least one stream of phase numbers. Of course, additional implementations are also within the scope of the present disclosure.

Abstract: A DDS (direct digital synthesizer) remarkably increased in the number of frequencies which can be output while maintaining the phase coherency, and an NMR instrument using such a DDS are provided. A DDS including phase accumulators and a phase-to-amplitude modulator is provided with a plurality of phase accumulators operating with fixed phase implements which are equal to powers of 2, a controller for outputting each bit of a frequency tuning word as control data, a plurality of switches for outputting an output of an associated one of the phase accumulators when an associated one of the control data supplied from the controller is 1 and outputting 0 when the associated one of the control data is 0, and an adder for adding up outputs of the switches.

Abstract: There is provided a digital signal processing device capable of suppressing occurrence of an unnecessary frequency component (spurious) in performing a reduction processing of a bit number of a frequency signal made of a digital signal. A signal output section 10 outputs a frequency signal by a digital signal made of bit data and an addition section 16 adds noise data for suppressing occurrence of an unnecessary frequency component to the bit data. A reduction processing section 11 performs a predetermined processing in correspondence with whether the bit data obtained in the addition section 16 is positive or negative, and thereafter, shifts each bit of the bit data to the right by m digits set in advance (m is an integer smaller than a bit number of the bit data) and cut off an m-bit portion to reduce the number, rounding down “0” and rounding up “1” for the most significant bit of the bits having been cut off.

Abstract: To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born.

Abstract: A digital filter instruction and filter implementing the filter instruction are disclosed. The filter instruction synthesizes a digital filter and includes an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit. The filter instruction a concise instruction format to significantly decrease memory required, allow for instruction pipelining without branch penalty, and uses a circular buffer for the data so the data address pointer is only needed to be updated for the next input sample. The filter instruction may be used to implement FIR or IIR filters by using the options of pre-clear accumulator or pre/post storing accumulator results.

Abstract: A system and method are provided for efficiently switching a loop bandwidth using stored values in a digital filter of a phase-locked loop system. In a first timeslice, an input signal is digitally filtered using base coefficients multiplied by stored filter output and input values from previous timeslices. The filter output value is used to acquire the input signal frequency in a first bandwidth. In response to changes in the input signal frequency, the input signal is digitally filtered in a predetermined number of first intermediate period timeslices using transient coefficients multiplied by stored filter output and input values from previous timeslices. As a result, the first filter output value is maintained within a predetermined range. In a second timeslice, the input signal is digitally filtered using base coefficients multiplied by stored filter output and input values from previous timeslices to acquire the input signal frequency in a second bandwidth.

Abstract: A method for accumulation of information is described. The information is separated into first portions of MSBs and second portions of LSBs. The first and second portions are respectively input to a first adder and a second adder to provide first and second sums. The first and second sums are output from a first and a second storage device for feedback input respectively to the first and second adder to provide the first and second sums. A carry bit output from the second storage device is generated responsive to each wrap condition associated with the storing of the second sums in the second storage device. The carry bit is fed back to the first adder and fed forward for subsequent consolidation with the first sums respectively output from the first storage device. The first sums and the second sums are respectively accumulated as numbers represented in a redundant number system.

Abstract: This invention relates to Pade approximation convert circuit of the direct digital frequency synthesizer in which a multiplier receives and multiplies a first input signal and a variable signal so as to produce a multiplication signal; a divider receives and divides a second input signal and a variable signal so as to produce a division signal; an adder receives and adds the multiplication signal and the division signal so as to generate an output signal, that is then returned back to the divider. A quarter period of a sinusoidal wave signal is completed by the proceeding of direct calculation two times such that the time for the calculation of a complete sinusoidal wave can be saved and the area of the calculation circuit can be reduced.

Abstract: A function generator for a digital system includes a plurality of sub-function generators. Each sub-function generator has an input that receives a respective input value and has an output that provides a respective output value responsive to the respective input value. A case detector receives a system input value and selectively routes at least a first portion of the system input value to the input of at least one selected sub-function generator. The case detector selects the selected sub-function generator in response to at least a second portion of the system input value. The case detector further suppresses transitions of data on the input of at least one non-selected sub-function generator. The case detector further selects the respective output value provided by the at least one selected sub-function generator and provides the selected respective output value as a function generator output value.

Abstract: A signal generator including a DDS-signal source that is configured to operate according to the principle of direct digital synthesis (DDS), and a PLL signal synthesizer that is configured to operate according to the principle of phase locked loop (PLL) using an output signal from the DDS-signal source as a reference signal. The DDS-signal source can be connected via a direct connection, without further frequency division or mixing, directly to an output of the signal generator or directly to a level-adjustment device of the signal generator in order to generate a portion of an overall frequency range of an output signal of the signal generator.

Abstract: The present invention is related to a digital circuit for use in a mixed-signal circuit.

Abstract: Provided is a deterministic component model determining apparatus that determines a type of a deterministic component included in a probability density function supplied thereto, comprising a standard deviation calculating section that calculates a standard deviation of the probability density function; a spectrum calculating section that calculates a spectrum of the probability density function; a null frequency detecting section that detects a null frequency of the spectrum; a theoretical value calculating section that calculates a theoretical value of a spectrum for each of a plurality of predetermined types of deterministic components, based on the null frequency; a measured value calculating section that calculates a measured value of the spectrum for the deterministic component included in the probability density function, based on the standard deviation and the spectrum; and a model determining section that determines the type of the deterministic component included in the probability density function

Abstract: Interpolators for quadratic approximation for sinusoids are described. A sample source providing first order derivatives of sub-sampled sets of phase factor samples is used. A differentiator is coupled to receive the first order derivatives and configured to provide second order derivatives of the first order derivatives. A first scaling device is coupled to receive each of the first order derivatives. A second differentiator is coupled to receive each of the first order derivatives and configured to respectively provide second order derivatives of the first order derivatives. A second scaling device is coupled to receive the second order derivatives. A first integrator is coupled to receive output from the first scaling device for preloading, and to receive output from the second scaling device for integration. A third scaling device is coupled to receive output from the first integrator. A second integrator is coupled to receive output from the third scaling device.

Abstract: An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter.

Abstract: An all-digital frequency conversion apparatus is provided that achieves frequency conversion using a simple phase detector and integer and fractional phase feedback information from a digital oscillator output. In an embodiment, a target phase accumulator unit generates a target phase signal to the phase detector unit. The target phase accumulator unit receives inputs from a reference signal input, and a target phase input value. The digital phase detector unit receives the reference signal, a current phase feedback input signal, and the target phase input signal. The phase detector unit outputs a frequency setting signal to a frequency value generator unit. The detector output is based on the difference between the current phase and the target phase. A frequency value generator unit is configured to output a frequency value signal to a digital oscillator unit that generates a corresponding digital output signal that is directly fed back to the current phase feedback input of the phase detector unit.