Abstract: The present disclosure relates to a method and an apparatus for approximating non-linear function. In some embodiments, an exemplary processing unit includes: one or more registers for storing a lookup table (LUT) and one or more operation elements communicatively coupled with the one or more registers. The LUT includes a control state and a plurality of data entries. The one or more operation elements are configured to: receive an input operand; select one or more bits from the input operand; select a data entry from the plurality of data entries using the one or more bits; and determine an approximation value of a non-linear activation function for the input operand using the data entry.

Abstract: A circuit and method for calculating a non-linear function of floating-point numbers using hierarchical look-up tables are provided. The look-up tables are programmable to hold non-linear ranges of values for any of a variety of non-linear functions. The circuit includes computation modules in respective stages of a high-throughput computation pipeline. A first computation module in a first stage receives one or more floating-point numbers and, for each floating-point number, selects a first entry from a first look-up table based on the floating-point number. The first computation module then calculates and outputs a table index and a variable based on the first floating-point number and the first entry. The second compute module in a second stage, selects a second entry from a second look-up table based on the table index, and calculates and outputs an approximate value for the non-linear function using the variable and the second entry.

Abstract: In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor.

Abstract: A processor includes a linear approximator and a front end including circuitry to assign linear approximation of a nonlinear function to a linear approximator. The linear approximator includes circuitry to divide a range of values for the linear approximation into a defined number of segments, perform linear approximation for each segment, move borders between the segments to reduce discontinuity moving along segments of variable length, repeat linear approximation for each segment until convergence, and return values for the linear approximation.

Abstract: A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h?1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.

Abstract: A method and system for approximating functions, including a function approximation repository, which includes a hybrid lookup table configured to store coefficients associated with polynomials in factored form (PFFs), and a results store configured to store results. The system also includes a function approximation device that includes two processors, memory, an IO module and a function approximation module, which includes functionality to receive a request to approximate the function for an argument; verify that the argument falls within a function interval; perform a determination to find a subinterval in which the argument falls; select a PFF associated with the subinterval; obtain PFF coefficients associated with the PFF from the hybrid lookup table; evaluate the PFF using the PFF coefficients and the argument to obtain a result; store the result in the results store; and return the result as an answer to the requesting entity via the IO module.

Abstract: Mathematical functions are computed in a single pipeline performing a polynomial approximation (e.g. a quadratic approximation, or the like) using data tables for RCP, SQRT, EXP or LOG using a single pipeline according and opcodes. SIN and COS are also computed using the pipeline according to the approximation ((?1)^IntX)*Sin(?*Min(FracX, 1.0?FracX)/Min(FracX, 1.0?FracX). A pipeline portion approximates Sin(?*FracX) using tables and interpolation and a subsequent stage multiplies this approximation by FracX. For input arguments of x close 1.0. LOG 2(x?1)/(x?1) is computed using a first pipeline portion using tables and interpolation and subsequently multiplied by (x?1). A DIV operation may also be performed with input arguments scaled up to avoid underflow as needed. Inverse trigonometric functions may be calculated using a pre-processing stage and post processing stage in order to obtain multiple inverse trigonometric functions from a single pipeline.

Abstract: Mathematical functions are computed in a single pipeline performing a polynomial approximation (e.g. a quadratic approximation, or the like); and one or more data tables corresponding to at least one of the RCP, SQRT, EXP or LOG functions operable to be coupled to the single pipeline according to one or more opcodes; wherein the single pipeline is operable for computing at least one of RCP, SQRT, EXP or LOG functions according to the one or more opcodes. SIN and COS are also computed using the pipeline according to the approximation ((?1)^IntX)*Sin(?*Min(FracX, 1.0?FracX)/Min(FracX, 1.0?FracX). A pipeline portion approximates Sin(?*FracX) using tables and interpolation and a subsequent stage multiplies this approximation by FracX. For input arguments of x close 1.0. LOG 2(x?1)/(x?1) is computed using a first pipeline portion using tables and interpolation and subsequently multiplied by (x?1). A DIV operation may also be performed with input arguments scaled up to avoid underflow as needed.

Abstract: Methods and circuitry for evaluating reciprocal, square root, inverse square root, logarithm, and exponential functions of an input value, Y. In one embodiment, an approximate value, RA, of the reciprocal of Y is generated. One Newton-Raphson iteration is performed as a function of RA and Y, resulting in a truncated approximate value, R. R is multiplied by Y and 1 is subtracted, resulting in a reduced argument, A. A Taylor series evaluation of A is performed, resulting in an evaluated argument, B. B is multiplied by a post-processing factor for the final result.

Abstract: Methods and apparatus are provided in which a computed vector index (CVI) can be generated/computed based on an input value being searched for within an index vector of a lookup table. When the CVI is greater than a length of an index vector, the CVI can be re-computed to generate a re-computed vector index (RVI). When the value of the CVI is determined to be correct, or when the RVI is generated, an interpolation routine for a linearly indexed index vector can be executed using a presently computed vector index (e.g., either the CVI or the RVI) to determine an interpolated output value that corresponds to the input value. By contrast, when the value of the CVI is determined to be incorrect, an interpolation routine for a piecewise indexed index vector can be executed to determine the interpolated output value.

Abstract: Precision of arithmetic operations on floating-point numbers is improved while also preventing an increase in the amount of processing. A second converter converts an exponent included in an exponent field according to an exponent conversion rule defined in accordance with a function. A storage stores in a table a value obtained by converting a mantissa field according to a mantissa conversion rule defined in accordance with the function. A retrieving unit derives an index of the table, by extracting the most significant 8 bits from the 23 bits constituting the mantissa field. The retrieving unit adds 1 to the mantissa field approximated by the most significant 8 bits so as to derive a second index. A deriving unit derives a tentative return value A and a tentative return value B. Further, the deriving unit interpolates between the tentative return value A and the tentative return value B so as to derive a return value of the function.

Abstract: A DDS system is disclosed that is configured to provide a variable clock delay that allows timing of data coming out of the ROM to be adjusted. In one example case, a DDS system is provided that includes a ROM for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values, and delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system. The delay circuitry may include, for instance, delay elements that can be selected alone or in combination to adjust the timing. The timing can be adjusted, for example, by adjusting delay of a clock signal that clocks one or more ROM pipeline registers. The system may include a phase accumulator and DAC, and adjusting the timing may include adjusting delay of a clock signal that clocks one or more DAC pipeline registers.

Abstract: A system and method are provided for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers. The method accepts a plurality (k) of reference frequency values (fri), where 1?i?k, associated with a corresponding plurality of synthesized frequency values (foi). For each synthesized frequency value, a raw ratio of integers Nprawi and Dprawi is calculated, such that: f o i = Np raw i Dp raw i × f r i . A greatest common divisor (GCD) of Nprawi and Dprawi and a primitive ratio of integers Np i Dp i is found for each raw ratio of integers, such that: N p i = Np raw i GCD ? ( Np raw i , Dp raw i ) ; and , ? D p i = Dp raw i GCD ? ( Np raw i , Dp raw i ) .

Abstract: Exemplary embodiments comprise memory for storing the look-up table values. One exemplary memory comprises a decoder, an encoder, and one or more patterns of crisscrossed interconnect lines that interconnect the encoder with the decoder. The patterns of crisscrossed interconnection lines may be implemented on one or more planar layers of conductor tracks vertically interleaved with isolating material.

Abstract: Exemplary embodiments of the present invention comprise a method for compressing data for storage in memory. According to one embodiment, the method forms a set of values based on a monotonically ordered series of look-up table values. For one or more paired values in the set, the exemplary method generates a difference of the values in the pair. After replacing one of the values in the pair with a value based on the differences to modify the set, the exemplary method stores final values based on the modified set in memory. The present invention also comprises memory for storing the look-up table values. One exemplary memory comprises a decoder, an encoder, and one or more patterns of crisscrossed interconnect lines that interconnect the encoder with the decoder. The patterns of crisscrossed interconnection lines may be implemented on one or more planar layers of conductor tracks vertically interleaved with isolating material.

Abstract: This method of converting a computational formula having been acquired in the form of a tree structure containing at least one node associated with a parameterized conditional branching operation and connected to at least a first and a second child node, the child node which is associated with the operation which is not executed and the set of nodes which have this child node as parent node being called ‘dead branch’, this method comprising:—the identification and the deletion (198) of the dead branch corresponding to the acquired value of a conditional parameter so as to obtain a computational formula pruned of this dead branch, and—the compilation (208) of the computational formula pruned of the dead branch so as to obtain the code executable by a chip card.

Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.

Abstract: Configurable compression and decompression of waveform data in a multi-core processing environment improves the efficiency of data transfer between cores and conserves data storage resources. In waveform data processing systems, input, intermediate, and output waveform data are often exchanged between cores and between cores and off-chip memory. At each core, a single configurable compressor and a single configurable decompressor can be configured to compress and to decompress integer or floating-point waveform data. At the memory controller, a configurable compressor compresses integer or floating-point waveform data for transfer to off-chip memory in compressed packets and a configurable decompressor decompresses compressed packets received from the off-chip memory. Compression reduces the memory or storage required to retain waveform data in a semiconductor or magnetic memory. Compression reduces both the latency and the bandwidth required to exchange waveform data.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The signal is input to a synthesizer timed to a rational multiplier of the RF frequency fRF. The signal is then divided to generate a plurality of phases of the divided signal. A plurality of combination signals are generated which are then multiplied by a set of weights and summed to cancel out some undersired products. The result is filtered to generate the LO output signal.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The use of analog mixers of the prior art is avoided and replaced with an XOR gate configured to generate the correct average frequency. The edges are dynamically adjusted by ±T/12 or zero based on the state of the controlled oscillator down-divided clock.

Abstract: A look-up table which is required during looking up table for data transferring and a method for looking up table are provided. The method reduces the size of the look-up table used in the method for looking up table by simplifying the calculations. A reasonable error range is obtained for the required look-up table by adjusting appropriate modifiers. The method can be applied in the method for looking up table similar to the Q ? ( x ) = x B A calculation in the digital signal coder/decoder (CODEC), where both A and B are integers, and the calculation is more efficient if B/A is close to 1 or smaller than 1.

Abstract: The purpose is to provide a waveform generator that generates signals with a frequency lower than the minimum sampling frequency of the DAC. In the waveform generator 10, the clock generator 106 generates a clock signal 140. The frequency divider 112 divides the frequency of the clock signal 140 and generates the frequency-divided clock signal 144. The reader 118 provides an address signal at the period of frequency-divided clock signal 144 for the waveform memory 120 and reads the pattern data from the waveform memory 120 into the DAC 130. The DAC 130 converts the data provided from the waveform generator 120 at the period of clock signal 140 into an analog value and outputs a waveform of arbitrary shape.

Abstract: A power function is approximated over an applicable data interval with polynomials determined by means of a Chebyshev minimax approximation technique. In some cases, multiple polynomials may be used to approximate the function over respective ranges of the desirable interval, in a piecewise manner. The appropriate polynomial that approximates the power function over the range of interest is derived and stored. When the power function is to be applied to a particular data value, the data value is first evaluated to determine where it lies within the applicable interval. The constants for the polynomial associated with that range of the interval are then retrieved and used to calculate the power of that data value.

Abstract: Multipurpose arithmetic functional units can perform planar attribute interpolation and unary function approximation operations. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x?xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for both classes of operations.

Abstract: A nonlinear conversion system using precision mapping and the method thereof are described. The system includes a source value converter, a mapping table unit, a recovering parameter computing unit, and an output computing unit. The method includes the steps of: receiving an input value; converting the input value into a source value; mapping the source value to a destination value in a limited domain for restricting the calculation within a destination domain; establishing a mapping table by directly selecting a precision according to the destination domain and inverse-mapping back to a source domain; and outputting the destination value according to the mapping table, combining the destination value with a recovering parameter for recovering an output value produced by the nonlinear conversion of the input value.

Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.

Abstract: An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recoded output values directly to partial product generators of a multiplier unit is also disclosed.

Abstract: A technique for approximating output values of a function based on LaGrange polynomials is provided. Factorization of a LaGrange polynomial results in a simplified representation of the LaGrange polynomial. With this simplified representation, an output value of a function may be determined based on an input value comprising a fixed point input mantissa and an input exponent. Based on a first portion of the fixed point input mantissa, a point value and at least one slope value are provided. At least one slope value is based on a LaGrange polynomial approximation of the function. Thereafter, the point value and the at least one slope value are combined with a second portion of the fixed point input mantissa to provide an output mantissa. Based on this technique, a single set of relatively simple hardware elements may be used to implement a variety of functions with high precision.

Abstract: A plasma control system including a direct digital synthesizer (DDS) for generating more than one individual RF power signal, where the individual RF power signals are combined to define a combined RF power signal. The DDS includes an accumulator which receives a phase increment signal that defines a frequency of a frequency signal generated by the accumulator. The frequency signal is split and input to a plurality of adders. Each adder receives a phase offset signal that defines a phase shift of the frequency signal input to that particular adder. The phase increment signal and phase offset may be stored to reduce the startup portion of the plasma control system.

Abstract: A frequency synthesizing and back-end processing circuit and method thereof are provided. This circuit includes a fully digital frequency synthesizer by using interpolation and a linear feedback shift register to synthesize a frequency. After digital-to-analog conversion, it provides two options of the digital and analog signals. Then the selected signal will be mixed by the corresponding mixer. Finally, the filer removes the undesired noise to obtain the desired synthesized frequency signal. This frequency synthesizer does not require complex digital or analog circuits and can achieve a high frequency resolution with a lower circuit complexity, which is superior to the conventional art. The present invention also includes mixers for different frequencies and filters for back-end processing.

Abstract: A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds.

Abstract: A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.

Abstract: A multi-phase signal generating apparatus is provided for readily generating multiple phase signals. The multi-phase signal generating apparatus comprises a signal data storage which stores a plurality of data segments for determining a predetermined period of one signal. A data segment selector circuit selects segments for constituting the phase signals from a plurality of data segments stored in the signal data storage for determining the predetermined period of a signal in each of a plurality of segment intervals which make up a phase signal cycle for generating a phase signal. Each phase signal generator circuit forms each phase signal using a plurality of selected segments for each phase signal during a plurality of segment intervals.

Abstract: The present invention relates to a look up table method for reducing the use of memory and more particularly to a condition while the input value has higher bits than the output value. This look up table method comprises: data storing that storing the input data into memory corresponding with output data with reference to the address of output data; and data searching including reading an input data, finding a closest address to the input data, and outputting the closest address. In this present invented look-up table method, the relation curve between the output value and corresponded input value is a monotonic curve, such as a ? curve.

Abstract: A waveform drawing routine is disclosed that includes receiving an array of predecessor image data points, wherein the predecessor image data points form a predecessor line that has a predecessor high end point and a predecessor low end point, receiving an array of successor image data points, wherein the successor image data points form a successor line having a successor high end point and a successor low end point, comparing the successor line to the predecessor line, and maintaining any portions of the predecessor line on a display that intersect with the successor line. The method described above for drawing each line segment that forms the waveform is repeated until a complete waveform is drawn on the display that consists of the concatenation of these individual lines.

Abstract: Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.

Abstract: A technique for approximating output values of a function based on LaGrange polynomials is provided. Factorization of a LaGrange polynomial results in a simplified representation of the LaGrange polynomial. With this simplified representation, an output value of a function may be determined based on an input value that includes an input mantissa and an input exponent. Based on a first portion of the input mantissa, a point value and at least one slope value are provided. Each of the at least one slope value is based on a LaGrange polynomial approximation of the function. Thereafter, the point value and the at least one slope value are combined with a second portion of the input mantissa to provide an output mantissa. Based on this technique, a single set of relatively simple hardware elements may be used to implement a variety of functions with high precision.

Abstract: A system for generating waveforms may include a memory configured to store a plurality of waveform segments, a plurality of waveform segment queues each coupled to receive waveform segments output by the memory, and a selection unit coupled to each of the waveform segment queues and configured to read waveform segments out of a selected one of the waveform segment queues. Each of the waveform segment queues may be configured to store a series of one or more waveform segments. The selection unit may be configured to access the first waveform segment queue during a first time period and to access the second waveform segment queue if a first trigger occurs.

Abstract: An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recorded output values directly to partial product generators of a multiplier unit is also disclosed.

Abstract: An apparatus and method for detecting an operation value using a look-up table at high speed, which not only minimizes the size of the look-up table but also satisfies a desired error rate. The apparatus includes a means for storing seed values corresponding to seed points determined according to the range of the input data and output data and an error rate, an address and data generator for comparing a predetermined reference value with the input data to generate an address of the storing means and revised input data corresponding to the input data, and an operator for performing a predetermined operation using the seed values output from the storing means and the revised input data generated by the address and data generator to output an operation value corresponding to the input data. Accordingly, an operation value having a minimum error rate can be provided with a small sized memory.

Abstract: A sin (x) or cos (x) computational generator is provided by a coarse and fine storage element sharing a common address bus with the coarse storage element storing full precision values for every Jth sample and said fine storage element storing correction values between the Jth samples. An arithmetic block operates on the output of the storage elements in response to addresses on the address bus to provide full precision values without storing full precision values.

Abstract: A digital synthesizer includes a memory containing values representing amplitudes of a signal such as a sinewave, a digital/analog converter for converting outputs from the memory into an analog signal, and a counter for counting by a predetermined fixed increment, which operates at a high frequency to enable the generation of very precise frequency waveforms. The digital synthesizer has many practical applications including the generation of precise signals to extract information from input radio frequency signals, the obtaining of a precise frequency from a low-cost clock, and the use as a component of a FSK modulator to permit selection between signals of multiple frequencies without any phase discontinuity. Finally, the digital synthesizer can be used in combination with an 8-bit memory, to generate a 10-bit input to a digital-to-analog converter.

Abstract: A circuit for digitally generating a series of encoded sampling values of a periodic function by virtue of ROM table conversion, include (a) a function ROM in which an amplitude associated with one-fourth of a period of a periodic function is stored, and (b) an address counter which generates an address signal to be input into the function ROM.

Abstract: A data serializer includes a differential output stage. The differential output stage has n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of n data inputs and n is an integer greater than one. Each pair of first and second control inputs is driven by a respective logic AND circuits having a rise time controlled by a first adjustable controlled current source and a fall time controlled by a second adjustable controlled current source.

Abstract: An amplitude data generator receives L-bit data, and outputs amplitude data of a predetermined periodic function of a phase specified by the data. A frequency setter sets frequency data of (K+L−1) bits obtained by dividing a desired output frequency by a frequency of a predetermined clock signal. A K bit counter counts the clock signal. L-set product and sum computation circuits subject the frequency data of (K+L−1) bits into L-set K-bit data in which a start bit is shifted by one bit each other. Then, these circuits compute a logical product between the counter output of K bits from the counter and a bit unit, and obtains a total number of bits for each set when the computation result is 1. A shifting/adding circuit adds each total number data obtained by the L-set product and sum computation circuits by shifting a bit, and outputs the least significant L bits of the computation result to the amplitude data generator.

Abstract: A method and apparatus for generating a timing signal for a semiconductor device, wherein the timing of rising and falling edges in the timing signal can be very precisely controlled. In one embodiment, a serial data stream derived from data stored in a memory device is applied to the inputs of first and second programmable delay elements each adapted to introduce a delay into the serial data stream. The resulting first delayed serial data stream is applied to the SET input of a flip-flop circuit; the resulting second delayed serial data stream is applied to the RESET input of the flip-flop. The output of the flip-flop constitutes the generated timing signal. The rising and falling edges of the timing signal are controlled through manipulation of the lengths of the delays introduced by the first and second delay elements into the serial data stream. Manipulation of the delay times is accomplished through adjustment of analog programming voltages applied to the respective delay elements.

Abstract: The invention relates to a method for generating a signal amplitude behaving according to a desired function and to a converter implementing the method. In the method, a function that is used for controlling the behaviour of a signal amplitude is piecewise linearized to provide straight lines; a slope and a constant term of each straight line is stored in a memory (202 and 203); and a midpoint of each straight line is shifted to form an origin in a common coordinate system. Variable data (213) is used as address data, which is divided into an MSB (207) and an LSB part (208). The MSB part (207) is used for addressing from the memory (202 and 203) the slope and the constant term of the straight line. The LSB part (208) functions as a variable of a common coordinate system of the straight lines.

Abstract: A waveform pattern file storage section is used for specifying a waveform pattern of a control signal, and storing waveform pattern bit strings formed from bits each of which specifies 1 logical state (an NRZ waveform). A waveform input section reads out the waveform pattern bit string. A waveform recognition section recognizes 1 cycle waveform pattern consisting of 3 consecutive bits in the waveform pattern bit string that has been read out. As a result, if an RZ waveform pattern has been recognized, an RZ waveform is generated with respect to the RZ waveform section; if an NRZ waveform pattern is recognized, an NRZ waveform is generated with respect to the NRZ waveform section.

Abstract: There are provided an electronic computing apparatus having a graph displaying function and a graph displaying method which allow an optimum graph to be quickly displayed. A graph is displayed on a display based on data for displaying the graph inputted from a key input section or the like. When one numeric key selected from among a plurality of numeric keys is specified by a predetermined number of times, a quadrant corresponding to the numeric key is selected from a quadrant selection table and a scale corresponding to the specified number of times is selected from a quadrant scale selection table, redisplaying a part of the graph existing in the selected quadrant on the selected scale. Thus, a desired graph may be quickly displayed by selecting the quadrant and scale of the displayed graph.