Abstract: Systems and methods for producing a linear-phase digital FIR filter from two sub-filters for an audio signal. In one method, the sub-filters are provided as sub-sets having numbers of coefficients, a lower cutoff frequency of the particular sub-filter being greater than the sampling frequency of the audio signal divided by the number. The sub-sets are linearly convoluted with one another so as to form a total set having a number of coefficients greater than the numbers, and the total set is symmetrically reduced to a number less than the number, so as to form a reduced total set of the filter. A linear-phase digital FIR filter for an audio signal is created by the method.

Abstract: A wireless apparatus includes a channel estimation part that acquires an estimated impulse response which is an estimate value of an impulse response of a channel between a wireless terminal and the wireless apparatus, a tap location error detection part that detects a tap location error between estimated impulse responses at different time points out of the estimated impulse responses, and a channel prediction part that calculates a predicted impulse response which is an impulse response of the channel at a future time point by using the estimated impulse responses and the tap location error.

Abstract: A method for multiplying two binary numbers includes configuring, in an integrated circuit, a plurality of lookup tables based on a known binary number (w). The lookup tables can be configured in three layers. The method further includes receiving, by the integrated circuit, an input binary number (d). The method further includes determining, by the integrated circuit, a multiplication result (p) of the known binary number w and the input binary number d by determining each bit (pi) from p using the lookup tables based on specific combinations of bits from the known binary number w and from the input binary number d, wherein a notation jx represents the xth bit of j from the right, with bit j0 being the rightmost bit of j.

Abstract: A method of enabling full speed test and characterization for high-speed Digital-to-Analog Converter (DAC) by employing an on-chip pattern generator. The test pattern is written to the on-chip pattern generator through a low data rate Integrated circuit (IC) interface, and the pattern generator is then enabled and coupled to DAC to facilitate full speed test for DAC. This method does not require extra input/output pin or extra process and minimize design complexity.

Abstract: A navigation device including a digital filter configured to smooth tracking is provided. The digital filter is configured to sequentially receive input data and output a tap sum, and calculate a quotient and a remainder by dividing an accumulation value with an average number, wherein the remainder is feedback to the tap sum for updating the accumulation value and the quotient is configured as output data.

Abstract: A digital signal is processed by splitting it into at least two frequency subbands and the two subband signals are downsampled. A filter is applied in at least one of the subband signals. At least one of the phase and magnitude of the subband filtered signals is matched in the transition frequency band between the two subbands.

Abstract: Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one implementation, an apparatus includes multiple processing branches, each including: a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit, and a digital bandpass filter. A combining circuit then combines signals at the processing branch outputs into a final output signal. The continuous-time quantization-noise-shaping circuits include adjustable circuit components for changing their quantization-noise frequency-response minimum, and the digital bandpass filters include adjustable parameters for changing their frequency passbands.

Abstract: A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit.

Abstract: A data signal delay system may include a delay unit and a phase interpolation unit. The delay unit may include multiple delay elements that each have an element delay. The delay unit may be configured to generate multiple delay signals by delaying a data signal using the delay elements such that each of the delay signals has a different delay. The phase interpolation unit may be coupled to the delay unit and may include a mixer. The mixer may be configured to mix two of the delay signals based on mixing weights selected for the two delay signals to generate a final delayed data signal that is the data signal delayed by a final delay. The mixing weights may be selected based on the final delay.

Abstract: A method for designing a set of sub-band FIR filters, where each FIR filter has a number of filter coefficients and is connected to an adjustable delay line. The method includes dividing an input signal into a number of sub-band signals, where a spectrum of the input signal comprises spectra of the sub-band signals; providing a respective goal sub-band signal for each sub-band dependent on a goal signal; filtering and delaying each sub-band signal using a corresponding FIR filter and delay line to provide filtered signals; providing error signals for each sub-band dependent on the filtered signals and the corresponding goal signals; adapting the filter coefficients of each sub-band FIR filter such that the respective filtered signal approximately matches a corresponding goal sub-band signal; and changing a respective delay of the delay line for each sub-band to reduce or increase a first quality criterion.

Abstract: A fabric for delaying digital signals in continuous time has an array of node filters. Inputs of filters in the first column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form an output signal of the filter. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other rows of the array. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements. A delay line is constructed by combining a phase generator and a fabric, where the phase generator splits a digital input signal in multiple incrementally delayed versions for the fabric inputs.

Abstract: A finite impulse response filter (FIR) for processing a communication channel. The FIR comprises a delay line, a tap processor and a summer. The delay line has “N” taps to successive portions of the communication channel. The delay line shifts the successive portions of the communication channel once in each symbol processing interval. The tap processor subjects each of the “N” taps to a first scaling utilizing first scaling coefficients associated with filtering the current symbol interval and further subjects at least one of the “N” taps to a second scaling by a second scaling coefficient associated with filtering the prior symbol interval. The summer generates in each symbol interval a filtered output comprising a sum of the “N” scaled taps from the first scaling in the prior symbol interval and the second scaling of the at least one tap in the current symbol interval, thereby increasing an order of the FIR without corresponding increase in an order of the delay line.

Abstract: An infinite impulse response (IIR) filter is provided for receiving an input signal and outputting a filtered signal. The filter comprises feedback circuitry for feeding back said filtered signal, the feedback circuitry comprising a first delay element for delaying said filtered signal; and a sub-unit, for receiving said delayed filtered signal, for outputting a summed signal which is the difference between said delayed filtered signal and a further-delayed filtered signal, and for outputting a multiplied signal which is an inverted further-delayed filtered signal multiplied by a first filter coefficient. At least said input signal, said delayed filtered signal, said multiplied signal, and said summed signal are employed to generate said filtered signal.

Abstract: An acquired signal indicative of electrophysiological activity is filtered using both a wavelet filter and either a notch filter or a band-pass filter to eliminate noise or interference, such as power line interference. A wavelet transform is used to transform the acquired signal into the wavelet domain, where a wavelet filter is applied to extract a soft component (e.g., a component with small wavelet coefficients). A filter, such as a notch filter or a band-pass filter, is applied to the soft component in order to isolate an interference signal. The interference signal is used to produce an output signal representing the acquired signal filtered to eliminate the interference signal. For example, the interference signal may be subtracted from the acquired signal. Alternatively, the output signal may be reconstructed from respective hard and soft components of the acquired signal as transformed into the wavelet domain.

Abstract: An equalization filter is provided for solving the problem in which there is a limited range in which compensated for distortion of a transmission signal can be made. Measuring instrument 104 measures a distortion quantity which characterizes distortion of the transmission signal. Comparator 105a generates a differential signal which indicates the difference between the transmission signal and a compensation signal. Delay device 105b delays the differential signal based on the distortion quantity measured by measurement instrument 104 and generates the compensation signal.

Abstract: In one embodiment, a circuit-based apparatus that operates on an input data stream includes delay-line circuitry that characterizes the input data stream, modified over time. A plurality of integrators provide a plurality of integrated signals in response to the delay-line circuitry, and a plurality of weighting amplifiers amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit combines the weighted signals. The circuit-based apparatus also includes a plurality of parallel signal-processing circuit paths that couple the weighted signals to the signal-combining circuit. By combining the weighted signals from the parallel signal-processing circuit paths, the signal-combining circuit provides a signal representative of the input data stream.

Abstract: A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal.

Abstract: A hybrid FIR filter includes a plurality of FIR filter units arranged as Direct Form FIR filters, connected together in an arrangement similar to a Transpose Form FIR filter. The hybrid filter arrangement may be used to configure a larger FIR filter in a programmable logic device having one or more specialized functional blocks, incorporating multipliers and adders, that are particularly well-suited for configuration as small Direct Form FIR filters.

Abstract: A method and circuit that gives a sequence pattern that represents directions of positive and negative transitions of the phase that continue over a predetermined number from a certain reference symbol to an adjoining next reference symbol; finds (heuristically) one or more interpolate symbols that meet conditions (such as standards for power spectra) of a predetermined frequency spectrum, i.e., band, and a predetermined (range of) amplitude with reference to the given sequence pattern; and stores the found sequence pattern and a phase value and an amplitude value corresponding to the found one or more interpolate symbols in a memory as a lookup table against the prepared memory area.

Abstract: The present invention is directed toward a Finite Impulse Response (FIR) no-multiply filter (NMF), which replaces complex multiplications with phase additions. At each tap in the FIR filter, only phases are accumulated and at the output the complex result is reconstructed in I/Q. Noise dither is relied upon to smooth the digitized phase resolution. The NMF is ideally suited to a matched filtering scenario for constant modulus signals.

Abstract: The invention relates to a method and filter structure for filtering an input signal, which is applied to an input (1) of the filter structure, having a symbol rate. The input signal is guided to multiple parallel branches of the filter structure connected to the input (1), in which at least two sequence holding members (4) are each disposed. Symbol values of the input signal, which are applied to the outputs of the sequence holding members (4) at certain points are guided to multiple (N) parallel signal addition units (3) having weighted inputs. One output signal each is generated in the signal addition units (3) as the sum of the weighted symbol values that are applied to the inputs. According to the invention, space and energy saving filter structure is provided, wherein: the same amount of sequence holding members (4.1, 4.2, 4.3) is disposed in each of the parallel branches; as many signal addition units (3.1, 3.2, 3.3, 3.

Abstract: A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal.

Abstract: An adaptive low pass filtering process with a filter delay DA is conducted in parallel with reference low pass filtering process with a filter delay DR which is greater than DA. The error is measured between a delayed version of the adaptive process output and the reference process output. Filter parameters of the adaptive process are controlled to minimise the error.

Abstract: A control system is provided for controlling a transducer array. The control system includes a plurality of sparse filters and integrators. The control system can be used to separate signals from a plurality of sources or to generate complex signal patterns that combine and map to different spatial regions.

Abstract: Methods and systems for a configurable finite impulse response (FIR) filter using a transmission line as a delay line are disclosed and may include selectively coupling one or more taps of a multi-tap transmission line to configure delays for one or more finite impulse response (FIR) filters to enable transmission and/or reception of signals. The delays may be configured based on a location of the one or more selectively coupled taps on the multi-tap transmission line. The FIR filters, which may include one or more stages, may be impedance matched to the selectively coupled taps. The multi-tap transmission line may be integrated on the chip, or a package to which the chip is coupled. The multi-tap transmission line may include a microstrip structure or a coplanar waveguide structure, and may include ferromagnetic material. The distortion of signals in the chip may be compensated utilizing the FIR filters.

Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.

Abstract: A single finite impulse response filter designed to operate on a single signal is used in conjunction with an input multiplexer that interleaves samples from multiple signals and an output decimator. The output of the decimator contains interleaved samples of the multiple signals with independent filtering applied to each.

Abstract: The invention relates to a filter device (200) for filtering an input signal (s(t)). The filter device (200) has a plurality of taps (210-216) having a respective filter coefficient (w0-w6) and a plurality of delay elements (221-226), wherein at least two delay elements (221-226) have different delays.

Abstract: The digital filter is connected to an upstream analog unit, changes bit data outputs corresponding to analog computation results every N clock pulse, operates in accordance with a clock in synchronization of the analog unit, and removes noise from the bit data output from the analog unit, the digital filter including an Nth-order sinc filter having a cascade of N sinc filters, each acquiring a moving average of a sample, and a moving average filter having a tap number of K connected to the output of the Nth-order sinc filter.

Abstract: A digital filter has a plurality of filters, wherein each filter performs coefficient multiplication and delay processing for an input signal and an output signal, obtains the output signal from the input signal, and includes a plurality of coefficient multipliers for multiplying a signal by a predetermined coefficient. The digital filter also includes a plurality of delay circuits for delaying a signal, and an adder for adding a plurality of signals. A first RAM stores a plurality of sets of coefficient data for a plurality of coefficient multipliers of the first filter and stores delay data for the delay circuit of the second filter. A second RAM stores a plurality of sets of coefficient data for a plurality of coefficient multipliers of the second filter and stores delay data for the delay circuit of the first filter.

Abstract: Systems and methods for utilizing new communication standards in wireless local area networks are provided that also support legacy wireless stations. The method can include user equipment determining channel state information, selecting a unitary channel decomposition precoder format based on the determined channel state information and transmitting the precoder format information to a base station. During a return transmission the user equipment can receive user data with the precoder format information and utilize a non-linear detector to demodulate and decode the user data. Based on the reception the user equipment can estimate channel quality; and transmitting channel quality information as feedback.

Abstract: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations, including finite impulse response (FIR) filters and infinite impulse response (IIR) filters. By using the programmable connections, and in some cases the programmable resources of the programmable logic device, and by running portions of the specialized processing block at higher clock speeds than the remainder of the programmable logic device, more complex FIR and IIR filters can be implemented.

Abstract: A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block.

Abstract: A digital filter includes at least a first and a second delayed summation line. One of the delay lines includes a warped finite impulse response (FIR) filter and the other line is a FIR filter. Midpoint elements from the first delayed summation line are used as input to the second delayed summation line. Output from the first delayed summation line is delayed with a delay corresponding to the total delay of the second delayed summation line and the delayed output from the first delayed summation line is added to output from the second delayed summation line to faun a new output.

Abstract: A partial response signaling system includes a transmitter circuit configured to equalize input data in response to a control signal and to transmit a partial response signal through a transmission medium; and a receiver circuit configured to recover an output data from the partial response signal and to generate the control signal based on the partial response signal and an expected signal to output the control signal to the transmitter circuit.

Abstract: An information handling system includes a wireless device and interference suppression apparatus that adapts to the different interference problems experienced by the wireless device when the system changes from one operating mode or state to another. The interference suppression apparatus includes a controller that instructs an adaptive filter with respect to the appropriate filter characteristics to employ to suppress interference when the system is operating in a first mode. When the system changes to a second mode of operation, the interference suppression apparatus updates the filter characteristics to filter characteristics which are appropriate for suppressing interference associated with the second mode of operation.

Abstract: A FIR filter (20) has a delay line comprising four delay elements (21a, 21b, 21c, 21d) for delaying a signal received at a filter input (22) and four multipliers (24a, 24b, 24c, 24d) for multiplying the delayed signals by respective partial filter coefficients a, b, c, d. The delay elements (21a, 21b, 21c, 21d) and multipliers (24a, 24b, 24c, 24d) are connected alternately in series. Four taps (23a, 23b, 23c, 23d) extract the signal from the delay line immediately after each of the delay elements (21a, 21b, 21c, 21d) and output the delayed, multiplied signals to an adder (25) for adding the delayed, multiplied signals to generate a filter output (26). The partial filter coefficients a, b, c, d effectively combine to implement filter coefficients A, B, C, D for the taps (23a, 23b, 23c, 23d), e.g. with A=a, B=a*b, C=a*b*c and D=a*b*c*d.

Abstract: Digital signaling processing (DSP) circuitry that supports multiple channel or time division multiplexing (TDM) applications is provided. For example, the DSP circuitry can process one or more channels of data without mixing the data of one channel with data of another channel. DSP circuitry of the invention supports multiple channel or TDM applications by embedding a tap delay line structure within the DSP circuitry. Utilizing this embedded tap delay line structure enables the DSP circuitry to support multi-channel or TDM applications independent of any external circuitry such as logic resources, thereby freeing up those resources for other uses.

Abstract: An FIR filter for filtering a prescribed real impulse constant (r) (?1<r<1) receives in a terminal the input of the input signal of the Chebyshev-chaos type spreading code sequence having a chip length D. A plurality of signals obtained by delaying the input signals by 0, D, 2D, 3D, . . . , and (N?1)D are output by a delay circuit. When the delay time is T, a plurality of delayed and output signals are multiplied by (?r)N?T/D with an amplifier and output, and the sum of a plurality of amplified and output signals, namely an optimum chaos-type spreading code string, is output by an adder.

Abstract: A method for generating an output sequence of samples in response to a first and a second subsequence of samples, the method comprising—applying a weighted overlap-add procedure to the first and second subsequences so as to generate the output sequence of samples, —optimizing a weighting function involved in the weighted overlap-add procedure in response to a measure of matching between the output sequence of samples and one or more target sequences of samples.

Abstract: An analog delay circuit to impart a group delay to an analog input signal is described. The analog delay circuit may comprise a capacitor to impart at least a portion of the group delay to the analog output signal and a buffer circuit coupled between the capacitor and an input stage to substantially remove at least a portion of a capacitive load at the input stage.

Abstract: A digital filtering apparatus and method for digitally filtering out undesirable or invalid data from data signal lines. The digital filtering apparatus includes a digital delay element having one or more outputs, a comparator connected to the outputs of the digital delay element, and a final stage connected to the output of the comparator and the outputs of the digital delay element. The digital filtering apparatus recognizes and filters out invalid data from data received by the digital delay element, and allows valid data to pass through the filter. Data is considered invalid data if its logical data state transition has a duration less than the clock setting of the digital filtering apparatus. The clock setting can be established by the number of active delay components in the digital delay element. The inventive digital filtering apparatus represents an improvement over conventional analog filters, e.g., in manufacturing efficiency and filtering performance.

Abstract: A delay line is constructed using a lossless (or low loss) transmission line which, in turn, can be constructed using an auxiliary conductor inductively coupled to the primary conductor. The auxiliary conductor is driven by the primary conductor through an active shunt network distributed along the transmission line. The auxiliary conductor is placed close enough to the primary conductor so that the two conductors have a substantial amount of mutual inductance compared to their self-inductance. In one embodiment, a combination of conductance and transconductance are used to cancel losses and control dispersion in the transmission line for high frequency signal transmission. In one embodiment, an FIR filter is constructed using the delay line.

Abstract: A series of digit processing units (DPUs) are connected to form a finite impulse response (FIR) filter. Each DPU includes a register, a multiplexer, and a coefficient multiplier. The register stores and delays an input digital signal to be filtered. The multiplexer has inputs connected to the input node and to an output of the register, an output of the multiplexer for connecting to a next stage DPU. The coefficient multiplier is connected to the output of the register and multiplies the input signal by a coefficient or part of a coefficient. A group of DPUs can have multiplexers set so that the register of each DPU stores the same part of the input signal for processing a single filter coefficient. An adder is provided to sum output of the DPUs and output a filtered signal. The critical path of the FIR filter is independent of coefficient number and precision.

Abstract: An n-level look-ahead network converts input values to intermediate values that are provided to a plurality of multiplexers arranged to form a pipelined multiplexer loop. The first stage of the multiplexer loop consists of a single multiplexer. The second stage consists of at least two multiplexers. Communication links couple the output ports of the second stage multiplexers to the input ports of the first stage multiplexer. A first feedback loop electrically couples the output port of the first stage multiplexer to the control port of the first stage multiplexer. This first feedback loop has a first delay device having a first delay time. A second feedback loop couples the output port of the first stage multiplexer to the control ports of the second stage multiplexers. This second feedback loop includes the first delay device and a second delay device having a second delay time.

Abstract: A method, apparatus, and system for scaling a value of an amplitude to a binary value and a method, apparatus and system for reducing an undesirable portion of a signal.

Abstract: A digital parallelized Infinite Impulse Response (IIR) integrator filter comprising a first channel having a first input and second channel having a second input, a first adder to add the two channel inputs, an integrator to integrate the added channel inputs to provide a first channel output is described herein. The second input channel is adjacent in time to the first channel input. The second channel further comprises a second adder which adds the first output with the second channel input in order to produce a second output, adjacent in time with the first output. This configuration can be generalized to n inputs and m outputs.

Abstract: A filter circuit is provided which has a filtered input and an unfiltered input. The filtered input passes through delay elements to coefficient circuitry. The unfiltered input passes to the coefficient circuitry without passing through the delay elements. In this manner, an unfiltered offset can be added to the filtered output. This filter is especially useful when the filtered value is in phase representation form; for example, when the filter value is a hue value encoded as a phase.

Abstract: A method for adjusting a time delay between a first audio signal and a second audio signal is disclosed. The method includes generating the first audio signal from a buffer as a first data stream and generating the second audio signal from the buffer as a second data stream after an initial time delay. The method further includes receiving the first data stream at a first sample rate converter at a first consumption rate and generating a first output data stream at an output sample rate. The second data stream is received at a second sample rate converter at a second consumption rate and the second sample rate converter generates a second output data stream at the output sample rate. One of the first and second consumption rates are changed so that the time delay between the first and second output data streams is adjusted over time from the initial time delay. A system for adjusting the time delay between a first audio signal and a second audio signal is also disclosed.

Abstract: A method and an apparatus for a channel estimator comprising a plurality of distinct filters each of which has a set of different coefficients and each of which is selectively coupled to the input and output of the channel estimator. The channel estimator further comprises a switching circuit that receives an error signal and switches to one of the plurality of filters based on the value of the error signal relative to an established threshold. The error signal is from a decoder coupled to a communication channel whose response is being estimated by the apparatus and method of the present invention.