Abstract: On a device having a maximum data rate, an interpolation filter can be configured in stages, with each stage may be broken into subfilters, which divides the output into phases. The ratio of the number of subfilters or phases in the final stage to the number of subfilters or phases in the initial stage is equal to the factor by which the data rate would otherwise increase. Thus for an interpolation factor of M, the output data rate can be kept the same as the input data rate by providing M subfilters, yielding M output phases each having an output rate equal to the input rate. The effective, or synthesized, output rate is M times the input rate. A decimation filter can be provided in the same way, with the effective input rate M times the output rate, even where the effective input rate would exceed the maximum data rate.

Abstract: A method and system for the design and implementation of desensitized digital filters with droop correction. The desensitized digital filter includes a first filter configured to receive an input signal, a decimator or upsampler, and a modified desensitized half-band filter. The first filter introduces droop into the passband of the desensitized digital filter. The desensitized half-band filter has a transfer function F(z)=K(1+z?1)G(z) wherein K?0 is a scale factor, that is modified to omit a (1+z?1) factor block. The modified desensitized half-band filter compensates for the passband droop introduced by the first filter. The first filter may be a sinc filter, CIC filter, or filter having similar properties.

Abstract: The invention may provide a method and filter block for compensating droop in a frequency response of a signal. The filter block may include a decimator, which decimates a high frequency input signal to a set frequency output signal. The set frequency can be, for example, the Nyquist frequency for the input signal. Further, the filter block may include a droop compensator that compensates the droop in the frequency response of the output signal from the decimator. The droop compensator may be made using recursive filters, as opposed to large tap FIR filters, which may result in less memory consumption and decreased power consumption.

Abstract: A method and system for the design and implementation of filters is presented in which the filter's transfer function can be provided with a significant insensitivity to the filter's tap coefficient values. A desensitized digital filter includes a first halfband filter and a second filter coupled in cascade between an input of the digital filter and the output of the digital filter. In embodiments, the first filter has the transfer function F(z)=K(1+z?1)(1+z?1) wherein K?0 is a scale factor. The digital filter may also interact with an up-sampler or a down-sampler. A desensitized Hilbert transformer includes an FIR filter having filter-tap coefficients whose absolute values equal the absolute values of the coefficients of an FIR filter F(z) for which the product (1+z?1)F(z) is a halfband filter coupled in cascade with a second filter.

Abstract: An image adjusting method is adapted to an image adjusting circuit. The image adjusting method includes following steps. An image signal is received and up-sampled to generate a first up-sampled image signal and a second up-sampled image signal. The first up-sampled image signal includes interpolated pixels and original pixels. Values of the interpolated pixels and the original pixels are detected, and a weight value is outputted according to the detection result. Whether the values of the interpolated pixels are adjusted or not is determined based on the detection result. According to the weight value, the second up-sampled image signal and the adjusted first up-sampled image signal are mixed to output a mixed image signal. An image adjusting circuit is also provided.

Abstract: One embodiment of the present invention relates to an analog correlation unit comprising a plurality of parallel correlation components configured to operating according to an advanced switched-capacitor low pass filter principle that increases coding gain of the unit. Each correlation component comprises a sampling stage and a correlation stage. The sampling stage may comprise a switched capacitor configured to sample a received baseband signal to determine a value (e.g., polarity) of the baseband signal. The sampled baseband signal is provided to the correlation stages, which may respectively comprise a plurality of switched integrators configured to selectively receive and integrate the sampled baseband signal over time depending upon values (e.g., polarity) of the correlation code to generate voltage potential values. The analog correlation result is evaluated by a comparison of an adjustable threshold voltage with the difference between the output voltage potential values.

Abstract: A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.

Abstract: Briefly, embodiments of methods or structures for reconstruction of uniform digital signal sample values from nonuniform digital signal sample values are disclosed.

Abstract: Various embodiments of the present invention provide systems and methods for data filter tuning. As an example, a method for filter tuning is disclosed that includes: providing a tunable filter having an operation filter and a calibration filter; applying a low frequency test input to the operation filter in place of an input signal to yield a first filter output; calculating a low frequency magnitude value corresponding to the first filter output; applying a high frequency test input to the operation filter in place of an input signal to yield a second filter output; calculating a high frequency magnitude value corresponding to the second filter output; modifying a tuning factor of the calibration filter when a ratio of the high frequency magnitude value and the low frequency magnitude value is outside of a defined range; and storing the tuning factor of the calibration filter when the ratio of the high frequency magnitude value and the low frequency magnitude value is within the defined range.

Abstract: A method and an apparatus for digital up-down conversion using an Infinite Impulse Response (IIR) filter are provided. The method for digital up-down conversion for frequency conversion in a mobile communication system using plural frequency converts, includes IIR-filtering, by a magnitude response IIR filter having the same magnitude response as in Finite Impulse Response (FIR) filtering, an input signal and a stable filter coefficient calculated according to a Levinson polynomial; and receiving, by the magnitude response IIR filter, the IIR filtered signal, and performing IIR filtering by a phase compensation IIR filter having a filter coefficient compensating for a non-linear phase to a linear phase.

Abstract: A digital signal processing system comprising: an input terminal to receive an input signal that includes a distorted component and an undistorted component, the input signal having a sampling rate of R; and an adaptive self-linearization module coupled to the input terminal, to perform self-linearization based at least in part on the input signal to obtain an output signal that is substantially undistorted, wherein: the adaptive self-linearization module is to generate a replica distortion signal that is substantially similar to the distorted component, the generation being based at least in part on a target component having a sampling rate of R/L, L being an integer greater than 1; the adaptive self-linearization module includes a first digital signal processor (DSP) that is adapted to obtain a filter transfer function that approximates a system distortion transfer function, and a second DSP that is configured using configuration parameters of the first DSP.

Abstract: Systems and methods described herein provide for low latency active noise cancellation, which alleviates the problems associated with analog filter circuitry. The present technology utilizes low latency digital signal processing techniques that overcome the high latency conventionally associated with conversion between the analog and digital domains. As a result, low latency active noise cancellation is performed utilizing digital filter circuitry which is not subject to the inaccuracies and drift of analog filter components. In doing so, the present technology provides robust, high quality active noise cancellation.

Abstract: A method of determining interpolation coefficients (607, 609, 610, 611) of a symmetric interpolation kernel (608) is disclosed. The method comprises determining a first interpolation coefficient (611) from the symmetric interpolation kernel (608) and storing the first interpolation coefficient in a memory (506). The method then determines the value of an intermediate function (310) from symmetrically opposed segments (201, 204) of the kernel, and determines a subsequent interpolation coefficient dependent upon the first interpolation coefficient and the value of the intermediate function.

Abstract: Disclosed is an efficient and configurable apparatus and method for sample rate conversion using interpolation. The apparatus and method employ a configuration file to change the conversion coefficients, sampling rate, and interpolation algorithm without having to recompile control software and/or reprogram the controlled device. In some embodiments, the interpolation employs polynomial interpolation, which may include Lagrange interpolation. In some embodiments, the interpolation method is selected to minimize the loop delay in teleoperation applications.

Abstract: A digital signal processor for interpolating a gain (coefficient) to be applied to a digital signal, the processor including: first memory means for storing a target gain coefficient; second memory means for storing a current gain coefficient; response determining means for determining an output gain coefficient based on the target gain coefficient and the current gain coefficient; means for storing the output gain coefficient in the second memory means in place of the current gain coefficient, to be used as the current gain coefficient in subsequent operations. In this way, a gain coefficient interpolator can be implemented using hardware rather than the previous DSP software approach.

Abstract: There is provided a sound processing apparatus and a sound processing method which are capable of reproducing discrete data with a high-quality sound matching users' preferences. In a sound processing means 2, since an interpolation value reflecting a value of a variable parameter ? by which the value of a control sampling function c0(t) is multiplied can be calculated, an analog signal obtained through the interpolation performed in a sampling function sN(t) can be regulated in accordance with the variable parameter ? by changing the value of the variable parameter ?. In this way, by allowing the user to appropriately change the variable parameter ? in accordance with various conditions including music reproduction environments, sound sources, musical tones and so on, it becomes possible to reproduce high-quality-sound music in which its frequency characteristics of the analog signal have changed and a high quality desired by the user is obtained.

Abstract: A signal decimating system decimates an initial data signal having an initial data rate R to a final data signal having a final data rate R? in two stages, using a base decimation factor N and a decimation multiplier factor P. In the first stage, N FIR filters having coefficients corresponding to the final data rate R? condition the initial data signal using the final data rate coefficients and thereafter decimate the initial data signal, as conditioned, by a base decimation factor of N to generate an intermediate data signal having an intermediate data rate R?, where R ? = R N . In the second stage, a sub-sampling unit includes a switch that sub-samples the intermediate data signal at a sub-sampling rate P to generate a final data signal having a final data rate R?, where R ? = R ? P = R ( NxP ) .

Abstract: The present invention receives simultaneously RF signal of different frequency band and processes the RF signal received, at this time a BPS receiver minimizes aliasing generated by RF signal. The present invention comprises a sampling process unit which samples a signal summing a first RF signal and a second RF signal of different frequency bands with time gap, a quantization process unit which generates a first stream signal and a second stream signal from signals sampled by the sampling process unit according respective time information in the signal summing the first RF signal and the second RF signal and a signal process unit which performs FIR filtering with reference to phase shift for a respect frequency band of the first stream signal and the second stream signal, separates the first RF signal and the second RF signal based on a result of the performance.

Abstract: Provided is a signal processing apparatus for compensating for a non-linear distortion of a digital signal, including: an analysis signal generating section that converts the digital signal into a analysis signal of a complex number, using a digital filter; and a compensation section that compensates for the analysis signal, using a compensation coefficient of a complex number corresponding to the non-linear distortion, where the digital filter divides data of the digital signal into “n” data sequences, assigns (n*L+k)th data of the digital signal to a k-th data sequence, performs filtering on each of the data sequences using a same filter coefficient, and combines each of the data sequences after the filtering, thereby generating an imaginary number portion of the analysis signal, where “n” is an integer equal to or greater than 2, L=0, 1, . . . , and k=1, 2, . . . , n.

Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.

Abstract: Data rate conversion devices and methods are provided. A method for converting a first digital signal having a first sampling rate into a second digital signal having a sampling rate close to a predetermined second sampling rate comprises the following operations: when the ratio of the first sampling rate to the second sampling rate is a repeating infinite decimal, calculate at least two calibrating coefficient values and output the calibrating coefficient values according to a predetermined rule; conduct overflow operation on the output calibrating coefficient; and interpolate the first digital signal using the output calibrating coefficient and the result of the overflow operation to obtain the second digital signal such that during any period of a certain length along time axis, sampling times of the second digital signal equals to sampling times of the second sampling rate.

Abstract: A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.

Abstract: A filtering method approximates a target Finite Impulse Response (FIR) (or transversal) filter and reduces computational requirements by eliminating high pass filtering required by known multi-rate filters. An input signal is copied into two identical signals and processed in parallel by a full-rate path, and by a reduced-rate path. Parallel filters are computed and applied in each path, the reduced-rate signal is up-sampled, and the two signals summed. The high pass filter required by known multi-rate filters is eliminated and the low pass filter in the prior art is implicit in a down sampling. Linear phase FIR filters are used for down and up sampling, resulting in constant group delay. Added benefits include the option of zero added latency through the filtering and the constant group delay added to the target FIR. The user may choose criteria such as minimum resolution in each band.

Abstract: A digital-to-analog converter (DAC) includes a resistor leg that is switchably connected to a first voltage reference via an n-channel MOSFET and to a second voltage reference via a p-channel MOSFET, and a generator circuit. The generator circuit further includes a first sub-circuit for generating a drive voltage (Vgn) and a second sub-circuit for a) offsetting the first drive voltage by an offset voltage to generate a second drive voltage, and b) supplying the second drive voltage to a gate of one of the first NMOS and the first PMOS.

Abstract: Systems and methods described herein provide for low latency active noise cancellation, which alleviates the problems associated with analog filter circuitry. The present technology utilizes low latency digital signal processing techniques that overcome the high latency conventionally associated with conversion between the analog and digital domains. As a result, low latency active noise cancellation is performed utilizing digital filter circuitry which is not subject to the inaccuracies and drift of analog filter components. In doing so, the present technology provides robust, high quality active noise cancellation.

Abstract: Methods and an apparatus are provided for interpolation of pixels in a pixel array having rows and columns of pixels. The apparatus includes a shift register array to shift pixel values of the pixel array, the shift register array including two or more shift registers; an interpolation filter array interconnected to the shift register array, the interpolation filter array including one or more interpolation filters; and a controller configured to provide pixel values in columns of the pixel array from the shift register array to respective interpolation filters in a first mode and configured to provide pixel values in rows of the pixel array from the shift register array to respective interpolation filters in a second mode. The controller may be configured to supply vertical sub-pixel values from the shift register array to the interpolation filters to generate diagonal sub-pixel values.

Abstract: Apparatus and methods for electronic hardware resource management in video processing are provided. A hybrid filter is controllable to apply either Finite Impulse Response (FIR) filtering or Infinite Impulse Response (IIR) filtering for vertical filtering of a video image during a resizing process. A scale factor by which the video image is to be resized in the resizing process is determined, and the hybrid filter is controlled to apply FIR filtering for the vertical filtering where the determined scale factor satisfies a first condition relative to a threshold value ST or to apply IIR filtering for the vertical filtering where the determined scale factor satisfies a second condition relative to the threshold value ST. The first and second conditions are different and exclusive, such that only one type of filtering is applied. This hybrid filtering approach uses each type of filtering to avoid defects of the other.

Abstract: A signal processing system includes a digital sample rate converter to convert a signal sampled at a first sampling frequency into a corresponding signal sampled at a second sampling frequency. In at least one embodiment, the sample rate converter includes a digital sample rate conversion filter. The digital sample rate conversion filter includes a digital filter that models a continuous time filter such as a low pass RC filter and generates filtered samples. The digital sample rate conversion filter also includes an interpolation filter that determines samples between the digital filtered samples. A sample selector selects the samples generated by the interpolation filter at the second sampling frequency. In at least one embodiment, the sample selector determines when to generate interpolated samples and the amount of time offset from an adjacent sample generated by the digital filter.

Abstract: A method for use in a digital frequency synthesizer, the method comprising phase to amplitude conversion of an output value of a phase accumulator in said synthesizer, said conversion being carried out as an approximation (y) of a phase value (x) which corresponds to said output amplitude value, the method being characterized in that the approximation comprises a combination of a linear interpolation value and a second order sinusoidal value, the second order sinusoidal value being used as an error term to correct for errors in the linear interpolation value.

Abstract: A method and apparatus provide digital frequency channelization of a digitally sampled input stream having a first bandwidth.

Abstract: A SAR ADC includes a DAC including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage. The SAR ADC further includes a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted when the common node is connected to ground. The SAR ADC further includes a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to ground when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from ground during a first of a plurality of successive approximations.

Abstract: The invention relates to a cascaded scheme in which an RRC filter, a modified RRC filter or other digital filter is implemented at a relatively low data rate, such as twice the symbol or chip rate, or 2×. Interpolation filters are used to increase the data rate to a higher data rate, such as 8×. Decimation filters are used to reduce the data rate from a higher rate, such as 8×, to a lower rate, such as 2×. The coefficients of the digital filter may be adjusted to compensate for characteristics of other components across the entire filter chain. Most of the implementation complexity of the filter chain is consolidated into the relatively low rate (such as 2×) digital filter while interpolation or decimation filters can be implemented at very low cost. The compensation capability provided by the digital filter makes design of simple decimation or interpolation filters much easier.

Abstract: Approaches for preparing a design of a digital multirate filter. In one approach, an objective function and an input and output characteristic are input for determining an effectiveness of a plurality of filters. The characteristic includes an overall rate change value that specifies a ratio of an input to an output sample rate. The overall rate change value is factored into a plurality of ordered sets, and the overall rate change value is a product of the factors in the ordered sets. Each of the filters corresponds to one of the ordered sets and includes a respective stage for each factor in the ordered set. One of the filters is selected based on respective values determined from evaluating an objective function for the filters, and the factor(s) in the ordered set that corresponds to the selected one of the filters is stored.

Abstract: To variably change the filter characteristic of a decimation filter in accordance with a sampling rate. A decimation filter 13 in a semiconductor device 1 sequentially inputs a signal sampled at a predetermined sampling rate fos, and calculates, for each input signal that is input within a predetermined period (a period for M+2N), a filter coefficient Cj for performing predetermined filtering processing in response to a trigger signal TR continuously applied, and furthermore sequentially multiplies the input signal by the calculated filter coefficient, accumulates a multiplication value within the predetermined period, and sequentially outputs the result. The predetermined period is made variable in accordance with a time interval at which the trigger signal is applied.

Abstract: A discrete time filter includes a plurality of sampling cells and a first dummy sampling cell. Each of the sampling cells performs a current mode sampling operation based on current input to an input terminal in response to a corresponding one of a plurality of sampling clock signals and is reset in response to a corresponding one of the plurality of sampling clock signals and a first dummy sampling clocks. The first dummy sampling cell alternately performs with the first sampling cell the current mode sampling operation based on current input to the input terminal in response to the first dummy sampling clock signal and is alternately reset with the first sampling cell in response to the first sampling clock signal.

Abstract: A multi-rate filter bank including an anti-aliasing filter, a plurality of multiplier block modules, a folding block, and a data composer is disclosed. The anti-aliasing filter receives an anti-aliasing input signal. The multiplier block modules receive an original signal and sequentially generate a plurality of processed signals. The multiplier block modules also receive a plurality of block input signals and a select signal. Each of the multiplier block modules is configured into a decimation block or an expanding anti-aliasing filter according to the select signal. The folding block receives the select signal and a folding input signal and generates a folding block output signal. The data composer receives and composes the folding block output signal and the outputs of the multiplexer block modules and the anti-aliasing filter and generates an anti-aliasing filter output signal.

Abstract: Some embodiments relate to a method for use in a sigma-delta analog to digital converter, sigma-delta analog to digital converters and systems comprising sigma-delta analog to digital converters. In accordance with an aspect of the invention, there is provided a method for use in a sigma-delta analog to digital converter (SD-ADC) comprising a modulator, a decimation filter, a decimation counter, and a decimator data output, wherein the method comprises receiving an external trigger signal and capturing a value of the decimation counter and a value of the decimator data output upon receiving the external trigger signal.

Abstract: A digital filter is provided for radio communication processing capable of dynamically modifying the characteristic and simultaneously processing a plurality of systems. In the digital filter, calculation core groups capable of modifying function are arranged and connected to one another by an input interface unit and an output interface unit. When the communication mode is modified, the number of calculation resources to be used and setting contents are decided according to the setting candidate of the filter characteristic required and the calculation resource empty state.

Abstract: A digital radio signal is processed by converting an analog signal to a digital signal, decimating the digital signal using a CIC filter and supplying the decimated digital signal directly to an asynchronous sample rate converter (ASRC). The decimated signal is resampled in the ASRC and the ASRC output is supplied directly to a droop compensation filter to compensate the output of the ASRC. By carefully choosing the response of the CIC filter and the resample rate of the ASRC, aliased artifacts in the pass band can be kept below a threshold magnitude without the need for a channelization filter.

Abstract: A noise reducing apparatus includes: a voice signal inputting unit inputting an input voice signal; a noise occurrence period detecting unit detecting a noise occurrence period; a noise removing unit removing a noise for the noise occurrence period; a generation source signal acquiring unit acquiring a generation source signal with a time duration corresponding to a time duration corresponding to the noise occurrence period; a pitch calculating unit calculating a pitch of an input voice signal interval; an interval signal setting unit setting interval signals divided in each unit period interval; an interpolation signal generating unit generating an interpolation signal with the time duration corresponding to the noise occurrence period and alternately arranging the interval signal in a forward time direction and the interval signal in a backward time direction; and a combining unit combining the interpolation signal and the input voice signal, from which the noise is removed.

Abstract: Aspects of a method and system for multi-band amplitude estimation and gain control in an audio CODEC are provided. In this regard, an audio signal may be filtered and delayed to generate one or more sub-band signals, a gain may be applied to each sub-band signal to generate one or more level adjusted sub-band signals, and the one or more level adjusted signals may be added to a delayed version of the audio signal. The gain applied to a particular one of the one or more sub-band signals may be controlled based on a detected amplitude of a summed signal derived by summing the particular one of the one or more sub-band signals and a corresponding one of the one or more level-adjusted sub-band signals.

Abstract: Techniques for efficient upconversion can process complex input data, such as for example data in an inphase and quadrature form. Half sample interpolation filtering and delay can be performed, and the results can be combined in a quarter-rate upconverter. The quarter rate upconversion can allow one of the half-sample interpolating filtering and the delay to be performed on one of either the inphase and quadrature samples.

Abstract: A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.

Abstract: A programmable logic device can be configured as a fractional rate resampling filter capable of performing downsampling prior to upsampling without modifying the overall filter response. Input data may be received at a first sample rate and may be downsampled to generate downsampled data. Portions of the downsampled data may be respectively output to different filtering paths. Each filtering path may include a cluster of filter components that corresponds to different subfilters of the overall filter response and may be operable to receive and process the different portions of the downsampled data. Outputs of each cluster may be combined to generate output data at a second sample rate. The resampling filter structure can reduce the number of multiplier circuits used by allowing time-division multiplexing among different filter components.

Abstract: A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M?1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

Abstract: An asynchronous sample rate converter prevents the folding back of a signal in the passband of an input sample rate into the passband of the output sample by adaptively controlling the decimation rate. The ASRC includes an adaptive decimation rate controller that selectably controls a decimation filter based on the ratio of the input sampling rate to the output sampling rate. By adaptively controlling the decimation rate in the ASRC, a significant amount of area and power is saved.

Abstract: Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.

Abstract: Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter.

Abstract: A three-dimensional (3D) image generator and 3D image generation method scale a depth map or a two-dimensional (2D) image, perform a cross filtering to sharpen a blurred region on the depth map based on location information of the depth map and 2D image, and thus obtain a clearer depth map and provide a more graphical 3D image using the depth map.

Abstract: A method for converting a sampling frequency of a digital signal sampled at a first sampling frequency includes receiving digital signal input samples, and forming output samples corresponding to a second sampling frequency based on the digital signal input samples and an interpolation filter. The first sampling frequency may be larger than the second sampling frequency. The method may further include delivering the output samples. Forming output samples includes, for each of the digital signal input samples, updating current values of N successive output samples with N contributions. The N contributions may be respectively calculated based on a value of a current input sample of the digital input samples weighted by values of N filter coefficients associated with the current input sample, N being fixed and identical for all the digital signal input samples regardless of a value of the conversion ratio between the first and second sampling frequencies.