Lattice Patents (Class 708/318)
  • Speech enhancement device, speech enhancement method, and non-transitory computer-readable medium
    Patent number: 10997983
    Abstract: A speech enhancement device includes: a filter to extract, from an input signal, a component in a frequency band including a fundamental frequency of speech, as a first filter signal; a filter to extract, from the input signal, a component in a frequency band including a first formant of speech, as a second filter signal; a filter to extract, from the input signal, a component in a frequency band including a second formant of speech, as a third filter signal; a mixer to mix the first and second filter signals, thereby outputting a first mixed signal; a mixer to mix the first and third filter signals, thereby outputting a second mixed signal; a controller to delay the first mixed signal, thereby generating a first speech signal for a first ear; and a controller to delay the second mixed signal thereby generating a second speech signal for a second ear.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: May 4, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Satoru Furuta
  • Low delay decimator and interpolator filters
    Patent number: 10904661
    Abstract: Systems and methods for low latency adaptive noise cancellation include an audio sensor to sense environmental noise and generate a noise signal, an audio processing path to receive an audio signal, process the audio signal through an interpolation filter, and generate a primary audio signal having a first sample frequency, an adaptive noise cancellation processor to receive the noise signal and generate an anti-noise signal, a direct interpolator to receive the anti-noise signal and generate an anti-noise signal having the first sample frequency, and a limiter to provide clipping to reduce a number of bits in the anti-noise signal, an adder operable to combine the primary audio signal and the anti-noise signal and generate a combined output signal, and a low latency filter to process the combined output signal.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 26, 2021
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Jens Kristian Poulsen, Trausti Thormundsson, Ali Abdollahzadeh Milani, Mark Miller
  • Complex exponential modulated filter bank for high frequency reconstruction
    Patent number: 9653090
    Abstract: An apparatus and method are disclosed for filtering and performing high frequency reconstruction of an audio signal. The apparatus includes an analysis filter bank, a phase shifter, a high frequency reconstructor, and a synthesis filter bank. The analysis filterbank receives real-valued time domain input audio samples and generates complex valued subband samples. The phase shifter shifts a phase of the complex-valued subband samples by an arbitrary amount. The high frequency reconstructor modifies at least some of the complex valued subband samples. A phase shifter unshifts a phase of the modified complex-valued subband samples by the arbitrary amount. The synthesis filter bank receives the modified complex valued subband samples and generates time domain output audio samples. The analysis filter bank comprises analysis filters that are complex exponential modulated versions of a prototype filter with an arbitrary phase shift.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 16, 2017
    Assignee: Dolby International AB
    Inventor: Per Ekstrand
  • Low power voice detection
    Patent number: 9633654
    Abstract: Methods of enabling voice processing with minimal power consumption includes recording time-domain audio signal at a first clock frequency and a first voltage, and performing Fast Fourier Transform (FFT) operations on the time-domain audio signal at a second clock frequency to generate frequency-domain audio signal. The frequency domain audio signal may be enhanced to obtain better signal to noise ratio, through one or multiple filtering and enhancing techniques. The enhanced audio signal may be used to generate the total signal energy and estimate the background noise energy. Decision logic may determine from the signal energy and the background noise, the presence or absence of the human voice. The first clock frequency may be different from the second clock frequency.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Arijit Raychowdhury, Willem M. Beltman, James W. Tschanz, Carlos Tokunaga, Michael E. Deisher, Thomas E. Walsh
  • Second order real allpass filter
    Patent number: 8521798
    Abstract: A digital all-pass filter has an input port leading to an input sum block and a first feed forward path. Within the first feed forward path is a multiplier. The filter also has an output port coupled to an output sum block that receives a signal from the first feed forward path. A first feedback path is also provided from the output port to the input sum block. The first feedback path includes a multiplier therein. Nested within this structure is a first order all-pass filter having a feed forward path including a forward path delay and forward path that is delayed and a feedback path absent a separate delay element and beginning after the forward path delay element.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: August 27, 2013
    Assignee: Magor Communications Corporation
    Inventor: Dean Swan
  • Filtering Discrete Time Signals Using a Notch Filter
    Publication number: 20120185525
    Abstract: Various techniques are generally described for digital signal processing (DSP) such as discrete time filters. In some examples, a Canonic Filter Module (CFM) can be used to configure the discrete time filter using an LSF-Model with a finite length sequence. A single CFM can be configured to provide any type of discrete time filter used in signal processing. Filters can be modeled as a set of interconnected notch filters, a lattice structure of a discrete time filter is generally described that is based on a LSF-Model.
    Type: Application
    Filed: December 4, 2010
    Publication date: July 19, 2012
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Satya Sudhakar Yedlapalli, Kuchibhotla Venkata Subrahmanya Hari
  • SECOND ORDER REAL ALLPASS FILTER
    Publication number: 20100077014
    Abstract: A digital all-pass filter has an input port leading to an input sum block and a first feed forward path. Within the first feed forward path is a multiplier. The filter also has an output port coupled to an output sum block that receives a signal from the first feed forward path. A first feedback path is also provided from the output port to the input sum block. The first feedback path includes a multiplier therein. Nested within this structure is a first order all-pass filter having a feed forward path including a forward path delay and forward path that is delayed and a feedback path absent a separate delay element and beginning after the forward path delay element.
    Type: Application
    Filed: September 22, 2008
    Publication date: March 25, 2010
    Applicant: Magor Communications Corporation
    Inventor: Dean SWAN
  • Image synthesis by rank-1 lattices
    Patent number: 7589729
    Abstract: Systems and techniques are described in which rank-1 lattices are used in computerized image processing, in particular in the context of image synthesis. These include systems and techniques for selection of rank-1 lattices, rasterization on rank-1 lattices, anti-aliasing by rank-1 lattices, and adaptive refinement and filtering by rank-1 lattices.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: September 15, 2009
    Assignee: Mental Images GmbH
    Inventors: Sabrina Skibak, Alexander Keller
  • Estimation method of flat fading channel in CDMA communication system and apparatus for the same
    Patent number: 7277472
    Abstract: The invention provides a method and apparatus for estimating flat fading channel in CDMA communication system, said method is implemented by using an adaptive forward prediction technique based on lattice filter and maximum likelihood technique of Viterbi algorithm. The adaptive lattice filter is used to carry out prediction of LS criteria on channel fading, and a maximum likelihood detection technique completes Viterbi algorithm in accordance with a channel fading value obtained by the prediction, thus obtaining final estimation and decision about the transmitting signals. The present invention has the advantages that it can obtain accurate result for channel estimation and sequence decision when it operates in the fast fading channel, and overcome fast fading influence due to motion speed up of mobile station, thereby satisfying mobile station speed and corresponding receiving performance required in 3G mobile communication.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: October 2, 2007
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Gang Li, Yu Jin, Sheng Liu
  • Elementary cell of a linear filter for image processing
    Patent number: 7190842
    Abstract: The present invention relates to an elementary cell of a linear filter for image processing, as well as to a corresponding module, element and process. The cell comprises a data circulation output and a calculation output, as well as a main delay line and an auxiliary delay line in parallel. Delay line selection means (MUX4) make it possible to link the input of the cell to the circulation output by way of one or other of the delay lines. The cell also comprises an adder having two inputs which can be linked respectively to the input of the cell and to the output of the main delay line, by calculation selection means (MUX1, MUX2) and a multiplier at the output of the adder, connected to a multiplier coefficients memory. Application to linear filtering for image processing and to random access for motion compensation.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: March 13, 2007
    Assignee: Thomson Licensing
    Inventors: Gérard Briand, Jean-Yves Babonneau, Didier Doyen, Patrice Lesec
  • Limit-cycle-absent allpass filter lattice structure
    Patent number: 6711599
    Abstract: A lattice-based second-order allpass filter (200) providing a digital filter, absent of limit cycles, includes interconnected quantizers(214, 224), delays (232, 240), multipliers (210, 220), and adders (208, 216, 228) for defining a transfer function, where the circuit corresponds in order and values to intrinsic values of the transfer function. The quantizers are connected in series after the multipliers to eliminate any double precision additions which give rise to the appearance of parasitic oscillations. The savings in hardware results from locating the quantizers after the multipliers; thus, eliminating all double precision additions that are mandatory in the classical second-order lattice structure. The second-order allpass filter coefficients that retain the limit-cycle-absent property of the filter correspond to specific guidelines.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Zhongnong Jiang
  • Application program interface for network software platform
    Publication number: 20030167356
    Abstract: An application program interface (API) provides a set of functions, including a set of base classes and types that are used in substantially all applications accessing the API, for application developers who build Web applications on Microsoft Corporation's .NET™ platform.
    Type: Application
    Filed: July 10, 2001
    Publication date: September 4, 2003
    Inventors: Adam W. Smith, Anthony J. Moore, Brian A. LaMacchia, Anders Hejlsberg, Brian M. Grunkemeyer, Caleb L. Doise, Christopher W. Brumme, Christopher L. Anderson, Corina E. Feuerstein, Craig T. Sinclair, Daniel Takacs, David S. Ebbo, David O. Driver, David S. Mortenson, Erik B. Christensen, Erik B. Olson, Fabio A. Yeon, Gopala Krishna R. Kakivaya, Gregory D. Fee, Hany E. Ramadan, Henry L. Sanders, Jayanth V. Rajan, Jeffrey M. Cooperstein, Jonathan C. Hawkins, James H. Hogg, Joe D. Long, John I. McConnell, Jesus Ruiz-Scougall, James S. Miller, Julie D. Bennett, Krzysztof J. Cwalina, Lance E. Olson, Loren M. Kohnfelder, Michael M. Magruder, Manish S. Prabhu, Radu Rares Palanca, Raja Krishnaswamy, Shawn P. Burke, Sean E. Trowbridge, Seth M. Demsey, Shajan Dasan, Stefan H. Pharies, Suzanne M. Cook, Tarun Anand, Travis J. Muhlestein, Yann E. Christensen, Yung-shin Lin, Ramasamy Krishnaswamy, Joseph Roxe, Alan Boshier, David Bau
  • Background code update for embedded systems
    Publication number: 20030163508
    Abstract: According to the present invention, there is provided an embedded system and method for performing a background code update of a current code image with an incoming code image in an embedded system, the method comprising the steps of: executing the current code image in the embedded system; executing one or more code update routines from the incoming code image to update the current code image with the incoming code image; and executing a task switching function from the current code image to switch microprocessor control from executing the one or more code update routines of the incoming image to execute a function in the current code image. The system and method may further provide for retrieving an offset from the incoming code image for the one or more code update routines in the incoming code image. The system and method may further provide for retrieving an offset from the current code image of a task switching function.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 28, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Brian Gerard Goodman
  • Discrete wavelet transform apparatus for lattice structure
    Patent number: 6539412
    Abstract: A discrete wavelet transform apparatus for a lattice structure is disclosed. This apparatus includes first through M-th lattice lattices installed in series along the length of a selected filter and each having an upper signal path and a lower signal path for supplying an output of the discrete wavelet transform apparatus, a data form transform unit for converting the form of the input signal and supplying to the first lattice stage, and a delay control unit connected between the lattice stages for thereby simplifying the hardware structure and implementing a scalable characteristic with respect to the different resolution levels and different filter lengths.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: March 25, 2003
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Joon-Tae Kim, Yong-Hoon Lee
  • Lattice structure for IIR and FIR filters with automatic normalization
    Patent number: 6442581
    Abstract: Apparatus providing a “reverse lattice” structure for IIR and FIR filters, which exhibits desirable scaling properties at no additional computational or memory cost. The reverse lattice structure implementation of an IIR filter scales down signals at sections corresponding to reflection coefficients close to 1 in magnitude. This feature provides automatic scaling for poles lying close to the unit circle which would otherwise produce large amplification factors.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: August 27, 2002
    Assignee: Creative Technologies Ltd.
    Inventor: Jean Laroche
  • Limit-cycle-absent allpass filter lattice structure
    Publication number: 20020052904
    Abstract: A lattice-based second-order allpass filter (200) providing a digital filter, absent of limit cycles, includes interconnected quantizers(214, 224), delays (232, 240), multipliers (210, 220), and adders (208, 216, 228) for defining a transfer function, where the circuit corresponds in order and values to intrinsic values of the transfer function. The quantizers are connected in series after the multipliers to eliminate any double precision additions which give rise to the appearance of parasitic oscillations. The savings in hardware results from locating the quantizers after the multipliers; thus, eliminating all double precision additions that are mandatory in the classical second-order lattice structure. The second-order allpass filter coefficients that retain the limit-cycle-absent property of the filter correspond to specific guidelines.
    Type: Application
    Filed: November 29, 2000
    Publication date: May 2, 2002
    Inventor: Zhongnong Jiang
  • Method of updating reflection coefficients of lattice filter and apparatus for updating such reflection coefficients
    Publication number: 20010021940
    Abstract: A method of updating reflection coefficients of a lattice filter is provided, which method includes the step of updating backward reflection coefficients by employing forward reflection coefficients which are updated so that a forward prediction error of a last stage of the lattice filter is minimized.
    Type: Application
    Filed: January 23, 2001
    Publication date: September 13, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Kensaku Fujii, Juro Ohga
  • System and method for filtering using an interleaved/retimed architecture
    Patent number: 6108680
    Abstract: An interleaved all-pass section for a lattice wave digital filter, comprises a first input carrying an interleaved signal, a first adder/multiplier network (AMN) connected to said first input, a second adder/multiplier network (AMN), and a delay element connected between said first AMN and said second AMN, wherein said delay element causes the propagation of signals from said first AMN to said second AMN to be delayed sufficiently to enable said second AMN and said first AMN to process separate signals in parallel.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: August 22, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Lynette C. Liu, Toshiaki Yoshino
  • Low-power digital filtering utilizing adaptive approximate filtering
    Patent number: 5999954
    Abstract: A method of digital filtering and a digital filter having a filter response with a predetermined filter order. The filter response produces a predetermined set of filtered output samples defining an output signal from a received input signal. The difference between the power associated with the input signal and the power associated with the output signal is calculated. The filter order of the filter response is varied based on the calculated difference of power in order to change the filter response.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: December 7, 1999
    Assignees: Massachusetts Institute of Technology, Trustees of Boston University
    Inventors: Jeffrey T. Ludwig, S. Hamid Nawab, Anantha P. Chandrakasan, James M. Ooi, Shawn M. Verbout