Abstract: An image processing apparatus supporting both discrete wavelet transform and discrete cosine transform with reduced hardware resources. The image processing apparatus is composed of an input unit receiving a plurality of pixel data, a controlling unit selecting a desired transform from among discrete wavelet transform and discrete cosine transform, and providing a plurality of coefficients depending on the desired transform, and a processing unit which processes the pixel data using the plurality of coefficients to achieve the desired transform.

Abstract: A method and an apparatus for calculating a scan signal so that the scan region becomes a scan region which is based on magnification ratio between desired magnification in a scan-line interval direction and desired magnification in a scan-line direction, and performing a calculation for rotating the scan direction with respect to the scan signal in order to suppress a distortion which is caused to occur when the technology where the scan direction of a charged particle beam is rotated is applied to the technology where the charged particle beam is scanned such that the scan-line interval is enlarged.

Abstract: A system for frequency-domain scaling for DCT computation. Scale factors are applied to coefficients during the final steps of composition of 2-point DCTs. The number of multiplications and required precision are reduced. Fixed values for various scale factors can be computed and stored prior to executing the DCT so that performance can be improved. The fixed values are derived by knowing the length of the time-domain sequence. Some fixed values can be derived independently of the length of the time-domain sequence. The approach of the invention can also reduce the number of multiplications to compute the transform, and allow smaller bit-width sizes by reducing the number of required high-precision calculations.

Abstract: Systems and methods that facilitate dimensional transformations of data points are disclosed. In particular, the subject invention provides for a system and methodology that simplifies dimensional transformations while mitigating variations of a distance property between pairs of points. A set of n data points in d dimensional space is represented as an n×d input matrix, where d also corresponds to the number of attributes per data point. A transformed matrix represents the n data points in a lower dimensionality k after being mapped. The transformed matrix is an n×k matrix, where k is the number of attributes per data point and is less than d. The transformed matrix is obtained by multiplying the input matrix by a suitable projection matrix. The projection matrix is generated by randomly populating the entries of the matrix with binary or ternary values according to a probability distribution.

Abstract: The present in invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transform (FFT) of a multidimensional array comprising a plurality of elements initially distributed in a multi-node computer system comprising a plurality of nodes in communication over a network, comprising: distributing the plurality of elements of the array in a first dimension across the plurality of nodes of the computer system over the network to facilitate a first one-dimensional FFT; performing the first one-dimensional FFT on the elements of the array distributed at each node in the first dimension; re-distributing the one-dimensional FFT-transformed elements at each node in a second dimension via “all-to-all” distribution in random order across other nodes of the computer system over the network; and performing a second one-dimensional FFT on elements of the array re-distributed at each node in the second dimension, wherein the random order facilitates eff

Abstract: The transposition circuit includes N input terminals (where N is an integer of 2 or greater) and N output terminals. This transposition circuit is configured such that when N packets of data for each matrix row are inputted in parallel to the corresponding input terminals, N packets of data are output in parallel for each matrix column from the corresponding output terminals. This transposition circuit generates data packets arranged as a transposed matrix and obtained from data packets in the form of an N×N matrix by interchanging the rows and columns of the original matrix.

Abstract: An arithmetic processing apparatus includes a first data storage unit, two-dimensional arithmetic unit, and main control unit. The first data storage unit stores data to be processed. The two-dimensional arithmetic unit performs two-dimensional operation. The main control unit controls the two-dimensional arithmetic unit. The two-dimensional arithmetic unit includes an input address calculation unit which calculates the addresses of a set of input data necessary for a designated type of operation in the first data storage unit in accordance with an execution start instruction which designates the type of operation and a parameter from the main control unit, and an arithmetic execution unit which performs the designated type of operation for the set of input data which are stored at the calculated addresses in the first data storage unit.

Abstract: An inverse discrete cosine transform (IDCT) apparatus is disclosed. The inverse discrete cosine transform (IDCT) apparatus can satisfy the bit accuracy of the standard recommendation and enable implementation of the ASIC by a smaller logic circuit, and simplify an interface between another sections of a video decoder. According to the present invention the image recovering performance of the video decoder installed to a digital TV receiver can be enhanced.

Abstract: The present invention provides a device and method for applying 1-D and 2-D DCT and IDCT transforms to sets of input data, typically 8×8 or 16×16 matricies of coefficients. In one embodiment, the present invention provides input lines, logic to pre-add input values and generate operands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the present invention may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic to pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.

Abstract: The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are loaded into a memory area of a core transform device and a variety of coding standards can thereby be handled by the same programmable core device. The core device is configured to process a certain sized data block, and the incoming source blocks are converted to conform to this size. After transformation, the proper sized result can be extracted from the transform device output. A switchable speed-up mode provides for 4-point transforms, rather than 8-point transforms. Alternatively, the invention also provides for dedicated transform hardware to be switchably used in conjunction with programmable transform hardware, depending upon the type of coding being used, and the speed of inverse transform desired.

Abstract: Systems and methods that facilitate dimensional transformations of data points are disclosed. In particular, the subject invention provides for a system and methodology that simplifies dimensional transformations while mitigating variations of a distance property between pairs of points. A set of n data points in d dimensional space is represented as an n×d input matrix, where d also corresponds to the number of attributes per data point. A transformed matrix represents the n data points in a lower dimensionality k after being mapped. The transformed matrix is an n×k matrix, where k is the number of attributes per data point and is less than d. The transformed matrix is obtained by multiplying the input matrix by a suitable projection matrix. The projection matrix is generated by randomly populating the entries of the matrix with binary or ternary values according to a probability distribution.

Abstract: A method, apparatus, computer medium, and other embodiments for discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) of image signals are described. A DCT/IDCT module includes a plurality of different cores. One embodiment of a core includes two sets of lookup tables to provide multiplication and add operations for the DCT and IDCT functions. Another embodiment of a core include one set of lookup tables, while another embodiment of a core includes no lookup table. The DCT/IDCT module provides forward DCT and IDCT functionality without the use of additional multipliers.

Abstract: Improved transposition of a matrix in a computer system may be accomplished while utilizing at most a single permutation vector. This greatly improves the speed and parallelability of the transpose operation. For a standard rectangular matrix having M rows and N columns and a size M×N, first n and q are determined, wherein N=n*q, and wherein M×q represents a block size and wherein N is evenly divisible by p. Then, the matrix is partitioned into n columns of size M×q. Then for each column n, elements are sequentially read within the column row-wise and sequentially written into a cache, then sequentially read from the cache and sequentially written row-wise back into the matrix in a memory in a column of size q×M. A permutation vector may then be applied to the matrix to arrive at the transpose. This method may be modified for special cases, such as square matrices, to further improve efficiency.

Abstract: Compressed data are decompressed using an inverse discrete cosine transform (IDCT). A first one directional (1D) IDCT is performed resulting in a plurality of first 1D IDCT coefficients followed by a second 1D IDCT resulting in a plurality of second 1D IDCT coefficients. In performing the first 1D IDCT and the second 1D IDCT a first plurality of intermediate butterfly computations are performed which include performing a plurality of intermediate multiplications resulting in a plurality of initial products and performing a plurality of intermediate additions resulting in intermediate product which are maintained at no more than 16-bits utilizing a round near positive (RNP) rounding scheme. Following the second 1D IDCT a rounding and shifting of the plurality of second 1D IDCT coefficients is performed utilizing a round away from zero (RAZ) rounding scheme resulting in a plurality of output coefficients which comply with the IEEE 1180 standard.

Abstract: A fast and precise method to perform inverse and forward Discrete Cosine Transform (DCT) is disclosed. The method may be used for implementing a two-dimensional (2D) inverse or forward DCT that operates on an N×M coefficient block and has a higher accuracy than is specified by the IEEE 1180-1990 standard (for the inverse operation). The disclosed method includes the following stages: based on integer operations, a fixed point one dimensional (1D) DCT may be performed on each row of an input coefficient block, an integer-to-single-precision floating point result conversion may be performed, and a single precision floating point 1D DCT may be performed on each column of the coefficient block resulting from the previous stages.

Abstract: Three-dimensional data that is processed is divided by the number of threads in the third dimensional direction and stored to respective secondary cache memories of the threads. Each thread Fourier transforms data stored in the secondary cache in the first dimensional direction and the second dimensional direction. As a result, a two-dimensional Fourier transform can be performed in parallel at a time. The resultant data that has been two-dimensionally transformed is restored to a shared memory. Each thread Fourier transforms the data in the third dimensional direction.

Abstract: A device and method are described that apply 1-D and 2-D discrete cosine transforms (DCT) and inverse discrete cosine transforms (IDCT) to sets of input data, typically 8×8 or 16×16 matricies of coefficients. One device includes input lines, logic to pre-add input values and generate opcrands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the device may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic or pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.

Abstract: A system and method for carrying out a two-dimensional forward and/or inverse discrete cosine transform is disclosed herein. In one embodiment, the method includes, but is not necessarily limited to: (1) receiving multiple data blocks; (2) grouping together one respective element from each of the multiple data blocks to provide full data vectors for single-instruction-multiple-data (SIMD) floating point instructions; and (3) operating on the full data vectors with SIMD instructions to carry out the two dimensional transform on the multiple data blocks. Preferably the two dimensional transform is carried out by performing a linear transform on each row of the grouped elements, and then performing a linear transform on each column of the grouped elements. The method may further include isolating and arranging the two dimensional transform coefficients to form transform coefficient blocks that correspond to the originally received multiple data blocks.

Abstract: A transpose of data appearing in a plurality of processing elements comprises shifting the data along diagonals of the plurality of processing elements until the processing elements in the diagonal have received the data held by every other processing element in that diagonal. Shifting along diagonals can be accomplished by executing pairs of horizontal and vertical shifts in the x-y directions or pairs of shifts in perpendicular directions, e.g. x-z. Each processing element stores data as its final output data as a function of the processing element's position. In one embodiment, an initial count is either loaded into each processing element or calculated locally based on the processing element's location.

Abstract: An apparatus and a method for carrying out a fast discrete cosine transform (DCT) with same positions of input and output data, and also a recording medium which is readable by a computer with a program loaded thereon, are disclosed. In the intermediate arithmetic procedure of the one-dimensional or two-dimensional forward or inverse DCT, the positions of the input and output data are made same, and therefore, an additional memory is not required. Specifically, the apparatus for carrying out the fast discrete cosine transform (DCT) with same positions of input and output data includes an input data sequence transposing means for transposing a sequence of an externally inputted input data by using a transposing matrix E. A butterfly arithmetic means carries out a butterfly arithmetic operation by using a Gt−1Bt−1. Gt−2Bt−2 . . . G0B0 matrix on a data obtained as a result of transposing the sequence of the input data by the input data sequence transposing means.

Abstract: A system and method for carrying out a two-dimensional forward and/or inverse discrete cosine transform is disclosed herein. In one embodiment, the method comprises: (1) receiving multiple data blocks; (2) grouping together one respective element from each of the multiple data blocks to provide full data vectors for single-instruction-multiple-data (SIMD) floating point instructions; and (3) operating on the full data vectors with SIMD instructions to carry out the two dimensional transform on the multiple data blocks. Preferably the two dimensional transform is carried out by performing a linear transform on each row of the grouped elements, and then performing a linear transform on each column of the grouped elements. The method may further include isolating and arranging the two dimensional transform coefficients to form transform coefficient blocks that correspond to the originally received multiple data blocks. The multiple data blocks may consist of exactly two data blocks.

Abstract: A data processing apparatus and method for quickly and efficiently producing a diagonally (170) mirrored image of a block of data (168). The apparatus comprises a first input operand (182) consisting of a first half of an N×N bit data block and a second input operand (184) consisting of a second half of an N×N bit data block. A first hardware bit transformation (188) forms an upper half of an N-way bit deal of the two operands (186), and a second hardware bit transformation (192) forms a lower half of the N-way bit deal (190). The upper and lower halves of the N-way bit deal represent a diagonally mirrored image (172) of the N×N bit data block. The method retrieves a data block from memory and packs it into two input operand registers. The two hardware bit transformations fill respective destination registers. The data is unpacked from the destination registers and stored to memory.

Abstract: An arithmetic processing apparatus includes a first data storage unit, two-dimensional arithmetic unit, and main control unit. The first data storage unit stores data to be processed. The two-dimensional arithmetic unit performs two-dimensional operation. The main control unit controls the two-dimensional arithmetic unit. The two-dimensional arithmetic unit includes an input address calculation unit which calculates the addresses of a set of input data necessary for a designated type of operation in the first data storage unit in accordance with an execution start instruction which designates the type of operation and a parameter from the main control unit, and an arithmetic execution unit which performs the designated type of operation for the set of input data which are stored at the calculated addresses in the first data storage unit.

Abstract: A one-dimensional (1D) Inverse Discrete Cosine Transform (IDCT) is applied to an input two-dimensional (2D) transform block along the axis to be modified. Since the one-dimensional IDCT is not performed on the other axis, each block is left in a one-dimensional transform space (called hybrid space). For a shift (merge), the appropriate “m” elements are picked up from one block and the “8−m” elements are picked up from the other block and are used as input to the one-dimensional forward DCT (FDCT) along that same axis. For two-dimensional shifts or merges, the results of the first one-dimensional IDCT and FDCT can be stored with extra precision to be used as input to a second one-dimensional IDCT and FDCT along the other axis. The execution time worst case conditions are approximately constant for all shift/merger amounts. Taking advantage of fast paths can improve the execution times for typical blocks.

Abstract: A system and method for multi-level iterative filtering of a data structure, e.g., an image, wherein elements of the data structure form the zero layer in the zero level and the data layer in each subsequent level is given by the results of one iteration. First, the method of the present system includes subdividing each level into a plurality of regions, there being data dependency between the data in one data layer in one level and the data layers in any other level of a region. Second, the method includes filtering each level by lapped-region processing. Lastly., the method includes scheduling the data processing of each level to provide substantially regional synchronization of the filtering at each level. In one embodiment, the sequence for traversing the regions is selected so that outputs from processing the regions are scheduled to occur at substantially equal time intervals.

Abstract: Data elements, preferably representative of video data, are logically divided into blocks. In a bit-wise fashion, each block is inspected to determine whether the data elements for that block may be represented in a highly compact format. If a given block may not be represented in this manner, it is sub-divided into blocks having smaller dimensions. This process of identifying suitable blocks and sub-dividing is recursively repeated until minimum block dimensions are reached. The same result may be achieved through the use of a plurality of ascending tables that are constructed by repetitively forming tables of reduced data elements. The plurality of ascending tables is traversed and, based on the reduced data elements, blocks of data are identified that are susceptible to the highly compact format. Wavelet transforms are preferably used to provide video data to be compressed.

Abstract: There is provided a DCT processor for performing at least one of DCT operation and inverse DCT operation for image data in unit blocks having different sizes. This DCT processor is provided with a bit slice circuit (102) for outputting, bit by bit, the pixel data inputted for each column or row; a first butterfly operation circuit (103) for subjecting the output data of the bit slice circuit (102) to butterfly operation; a ROM address generation circuit (104) for generating continuous ROM addresses; an RAC (105) for reading the data corresponding to the ROM addresses from ROMs (ROM0˜ROM7) and accumulating the data by accumulation circuits (51a˜51h); and a second butterfly operation circuit 106 for subjecting the output data of the RAC 105 to butterfly operation.

Abstract: The present invention relates to a distributed arithmetic module employing a zero input detection circuit that reduces electric power consumption by avoiding unnecessary calculation. An apparatus for performing a discrete cosine transform (DCT) on a video signal, including; input unit for receiving the video signal in a block by block basis; discrete cosine transform (DCT) unit for receiving each image data block from the input unit and conducting a discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) operation on the received image data block to generate a transformed image data block containing N×M pixel value; zero input detect unit for determining whether pixel values of a current image data block are all “0” and generating a detection signal in order to bypass the DCT/IDCT performing on the current image block; and output unit for outputting the transformed image data block as a transformed video signal.

Abstract: Architecture and method for performing discrete wavelet transforms An architecture component an a method for use in performing a 2-dimensional discrete wavelet transform of 2-dimensional input data is disclosed. The architecture component comprises a serial processor for receiving the input signal row-by-row, a memory for receiving output coefficients from the serial processor, and a parallel processor for processing coefficients stored in the memory and a serial processor for processing further octaves. The parallel processor is operative to process in parallel coefficients previously derived from one row of input data by the serial processor.

Abstract: Two-dimensional discrete wavelet transform analysis and synthesis banks. In various embodiments, a cascade combination of two one-dimensional wavelet transforms is implemented, along with a set of memory buffers between the two stages. The memory buffers store intermediate results between the stages of the two-dimensional discrete wavelet transform, thereby eliminating off-chip memory references.

Abstract: An ASIC-implemented wavelet transformation engine (circuit) providing a wavelet filter is described. The wavelet filter itself provides up to a 9-stage FIR (finite impulse response) filter with symmetrical coefficients. The architecture of the filter includes data inputs, a bank of shift registers (register bank), coefficient registers, a multiplier/accumulator, a sub-sampling component, and output (results) registers. The filter provides a wavelet-based compression solution that may be implemented in less-costly, page-based memory architecture (e.g., SDRAM), and does so in a manner that overcomes the inherent speed disadvantage encountered due to the horizontal-optimized access strategy employed by page-based memory architectures.

Abstract: A circuit arrangement and method for performing the 2-D DCT. An input permutation processor reorders input samples, constructing a logical matrix of input samples. A plurality of 1-D DCT processors are arranged to receive the reordered data and apply the 1-D DCT along extended diagonals of the matrix. The output polynomials from the 1-D DCT processors are provided to a polynomial transform processor, and the output data from the polynomial transform processor are reordered, by an output permutation processor. The 1-D DCT processors and polynomial transform are multiplier free, thereby minimizing usage of FPGA resources in an FPGA implementation.

Abstract: A signal analysis system and method for analyzing an input signal acquired from a mechanical system. The mechanical system may include at least one rotating apparatus. The signal analysis system may include an input for receiving samples of an input signal acquired from the mechanical system, wherein the input signal is sampled in time, and wherein the input signal comprises a plurality of order components. The signal analysis system may also include a processor coupled to the input and a memory medium coupled to the processor which stores analysis software.

Abstract: The invention comprises an efficient system and method for performing the modified discrete cosine transform (MDCT) in support of time-domain aliasing cancellation (TDAC) perceptive encoding compression of digital audio. In one embodiment, an AC-3 encoder performs a required time-domain to frequency-domain transformation via a MDCT. The AC-3 specification presents a non-optimized equation for calculating the MDCT. In one embodiment of the present invention, an MDCT transformer is utilized which produces the same results as carrying out the calculations directly as in the AC-3 equation, but requires substantially lower computational resources. Because the TDAC scheme requires MDCT calculations on differing block sizes, called the long and short blocks, one embodiment of the present invention utilizes complex-valued premultiplication and postmultiplication steps which prepare and arrange the data samples so that both the long and short block transforms may be computed with a computationally efficient FFT.

Abstract: A system (10) for generating a transform includes a first transform lookup table (12) and second transform lookup table (28). A transform exclusive OR array (26) is connected to an output (24) of the first transform lookup table (12) and an output (32) of the second transform lookup table (28). The system (10) allows transforms (polynomial codes, CRCs) to be generated using two or more tables.

Abstract: Three-dimensional data that is processed is divided by the number of threads in the third dimensional direction and stored to respective secondary cache memories of the threads. Each thread Fourier transforms data stored in the secondary cache in the first dimensional direction and the second dimensional direction. As a result, a two-dimensional Fourier transform can be performed in parallel at a time. The resultant data that has been two-dimensionally transformed is restored to a shared memory. Each thread Fourier transforms the data in the third dimensional direction.

Abstract: A data processing device provides for registers which can be formatted as segments containing numbers to which operations can be applied in SIMD fashion. In addition it is possible to perform operations which combine different segments of one register or segments at different positions in the different registers. By providing specially selected it is thus made possible to perform multidimensional separable transformations (like the 2-dimensional IDCT) without transposing the numbers in the registers.

Abstract: Data elements, preferably representative of video data, are logically divided into blocks. In a bit-wise fashion, each block is inspected to determine whether the data elements for that block may be represented in a highly compact format. If a given block may not be represented in this manner, it is sub-divided into blocks having smaller dimensions. This process of identifying suitable blocks and sub-dividing is recursively repeated until minimum block dimensions are reached. The same result may be achieved through the use of a plurality of ascending tables that are constructed by repetitively forming tables of reduced data elements. The plurality of ascending tables is traversed and, based on the reduced data elements, blocks of data are identified that are susceptible to the highly compact format. Wavelet transforms are preferably used to provide video data to be compressed.

Abstract: An invention about inverse discrete cosine transformer of MPEG decoder is disclosed. By using the symmetry of N×N IDCT kernel matrix, the invention reduces the number of multipliers to N/4, the number of accumulators to N/2 in IDCT block without loss of decoding speed. This invention include memory parts, N/4 multipliers, M/2 accumulators and transposing means. Memory parts store absolute values of kernel matrix of inverse discrete cosine transform. N/4 multipliers receive elements of discrete cosine transform coefficient matrix or of transpose matrix of one-dimensional inverse discrete cosine transform coefficient matrix, as their multiplicand input, and elements of kernel matrix of inverse discrete cosine transform as their multiplier input. N/2 accumulators accumulate data outputted from multiplier.

Abstract: Methods and apparatus for performing a fast two-dimensional inverse discrete cosine transform (IDCT) in a media processor are disclosed. A processor receives discrete cosine transform data and combines, in a first stage, the discrete cosine transform data with a first set of constants. In a media processor with a partitioned SIMD architecture, the discrete cosine transform data and first set of constants may be combined, for example, by multiplying the at least one input component with a first set of constants using a complex multiplication instruction. The output is transposed in a second stage and combined with constants in a third stage to obtain the pixel information of an image.

Abstract: In order to execute a rapid and effective DCT and IDCT and embody DCT and IDCT in one processor, in an inventive DCT/IDCT processor, an input multiplexer selects DCT or IDCT coefficients and transfers the coefficients to a matrix multiplier, and DCT/IDCT deciding unit within the matrix multiplier controls a flow of the DCT and IDCT coefficients. An output multiplexer decides an output of the DCT and the IDCT, to thereby embody the DCT and the IDCT in one processor, and perform the DCT and the IDCT at a high speed by reducing the number of multiplication calculation, namely through a decrease of the calculation number.

Abstract: A method and apparatus is presented for video image compression using a unique operand decomposition technique combined with an innovative data scatter and retrieve process. This combination of features allows the use of single ported RAM structures where multiported RAMS would normally be used, such as when retrieving two operands in the same time cycle. As applied to the Discrete Cosine Transformation this method and appatatus additionally allows elimination of the usual prior art use of a separate transpose matrix buffer. The elimination of the separate transpose matrix buffer is accomplished by combining the transpose matrix intermediate results memory storage with the memory buffer used for the other intermediate results in a double buffer system.

Abstract: A two-dimensional discrete cosine transform processor (two-dimensional DCT processor) includes two one-dimensional DCT circuits and a transposition memory interposed therebetween. Each of the two one-dimensional DCT circuits includes a butterfly operation circuit and a distributed arithmetic circuit at the subsequent level. Partial sums of vector inner products based on a constant matrix obtained by multiplying respective elements of a discrete cosine matrix by frequency-depending weighting according to human visual sense are stored in ROMs included in the distributed arithmetic circuit, and the contents of the ROMs are used to obtain a one-dimensional DCT result with weighting given. In this manner, arbitrary weighting can be given to the transform result without using a multiplier. Thus, for example, in a compressing and coding system for image data, the compression efficiency can be improved as compared with the case where weighting is not given to the transform result.

Abstract: Methods and apparatus for performing a fast two-dimensional inverse discrete cosine transform (IDCT) in a media processor are disclosed. A processor receives at least one input component representing discrete cosine transform data and combines, in a first stage, the at least one input component with a first set of constants. In a media processor with a partitioned SIMD architecture, the input data and first set of constants may be combined, for example, by multiplying the at least one input component with a first set of constants using a complex multiplication instruction. The output is transposed in a second stage and combined with constants in a third stage.

Abstract: Methods and apparatus for performing a fast two-dimensional inverse discrete cosine transform (IDCT) in a media processor are disclosed. A processor receives discrete cosine transform data and combines, in a first stage, the discrete cosine transform data with a first set of constants. In a media processor with a partitioned SIMD architecture, the discrete cosine transform data and first set of constants may be combined, for example, by multiplying the at least one input component with a first set of constants using a complex multiplication instruction. The output is transposed in a second stage and combined with constants in a third stage to obtain the pixel information of an image.

Abstract: An orthogonal transform apparatus has: orthogonal transform circuit for performing n-dimensional s-order (n and s are natural numbers) orthogonal transform, modified-information control circuit for performing control in accordance with modified information for outputting n-dimensional m-order data as n-dimensional p-order data (m and p are natural numbers), and rearrangement circuit for performing the following in accordance with the control by said modified-information control circuit: (1) m-p data values from the high-order side out of m-order input data values are set to 0 when m is equal to s and m is larger than p, p-m data values are added to the high-order side among m-order input data values to rearrange the data values when m is smaller than p, or data values are left as they are when m is equal to p; (2) the data values in said Item (1) are rearranged after discarding m-s data values from the high-order side of said m-order input data values before rearranging the data values in said Item (1) whe

Abstract: An apparatus and a method for performing discrete cosine transformation (DCT) are presented. The apparatus includes an arithmetic circuit interconnected with a transpose memory. The arithmetic circuit includes a combinatorial circuit for calculating a DCT without using an intermediate clocked storage unit. The combinatorial circuit includes a predetermined number of sequentially arranged stages for implementing the DCT. The apparatus may optionally include a controller for controlling operation of the apparatus and a multiplexer for multiplexing data input to the apparatus and data from the transpose memory. An apparatus and a method for performing inverse discrete cosine transformation (IDCT) are also presented.

Abstract: A set of scaled weighing coefficients is employed in the intrinsic multiplication stage of a six-stage DCT/IDCT fast algorithm for one of two one-dimensional DCT/IDCT operations so that a corresponding stage of the DCT/IDCT fast algorithm for the other one of the one-dimensional DCT/IDCT operations can be omitted. Accordingly, the number of multiplication operations for two-dimensional DCT/IDCT processing is reduced in order to achieve a higher processing speed.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU.

Abstract: An 8.times.8 two-dimensional discrete inverse cosine transform circuit includes two row arithmetic sections each of which implement an 8-point one-dimensional inverse discrete cosine transform in a row direction, a replacement section which replaces the arithmetic results of the row arithmetic sections with replacement data, and two column arithmetic sections each of which receive parts of the replacement data from the replacement section and implement an 8-point one-dimensional inverse discrete cosine transform in a column direction. Each of the arithmetic sections include a 16-bit four parallel adder and subtracter and a 16-bit four parallel multiply-accumulate unit with polarity symmetric rounding function.