Abstract: A signal processing device and an image processing device are provided. The signal processing device includes a matrix calculator for performing a matrix operation selected by a switch part among a DCT matrix operation, a Haar matrix operation, and a Slant matrix operation, with respect to an input signal. Thus, the signal processing device can be implemented in a hybrid architecture capable of selectively processing the DCT-II transform, the Haar transform, and the Slant transform with a single chip.

Abstract: A video codec method is provided, for processing video data processed by a Discrete Cosine Transformation (DCT) operation, comprising: (a) if a transformation matrix having a plurality of coefficients comprises at least one non-integer coefficient among the coefficients, multiplying the transformation matrix by a multiplication factor ? to make all coefficients of the transformation matrix integers, (b) estimating a compensation set, (c) performing a Column in Row out IDCT two-dimensional operation on the video data according to the transformation matrix and the compensation set, to obtain a compensated two-dimension operation result, (d) selectively dividing the compensated two-dimension operation result by ?2 to obtain an IDCT operation result.

Abstract: A more efficient encoder/decoder is provided in which an N-point MDCT transform is mapped into smaller sized N/2-point DCT-IV, DST-IV and/or DCT-II transforms. The MDCT may be systematically decimated by factor of 2 by utilizing a uniformly scaled 5-point DCT-II core function as opposed to the DCT-IV or FFT cores used in many existing MDCT designs in audio codecs. Various transform factorizations of the 5-point transforms may be implemented to more efficiently implement a transform.

Abstract: A method for computing a fast Fourier transform (FFT) in a parallel processing structure uses an interleaved computation process. In particular, the interleaved FFT computation process intertwines the output of two different shifted Fourier matrices to obtain a Fourier transform of an input vector. Next, an even-odd extension process is applied to the transformed input vector, whereupon various terms are grouped in a computational tree. As such, the resulting segmentation of the computation allows the fast Fourier transform to be computed in a parallel manner.

Abstract: Systems and methods for generating updates of large scale 3D geological models with multi-model facies, permeability or porosity distribution.

Abstract: Techniques for efficiently performing transforms on data are described. In one design, an apparatus performs multiplication of a first group of at least one data value with a first group of at least one rational dyadic constant that approximates a first group of at least one irrational constant scaled by a first common factor. The apparatus further performs multiplication of a second group of at least one data value with a second group of at least one rational dyadic constant that approximates a second group of at least one irrational constant scaled by a second common factor. Each rational dyadic constant is a rational number with a dyadic denominator. The first and second groups of at least one data value have different sizes. The first and common factors may be selected based on the number of logical and arithmetic operations for the multiplications, the precision of the results, etc.

Abstract: A semiconductor device including a first processing unit processing an input signal based on a plurality of image compression standards, a signal generation unit outputting a switching signal to the first processing unit, a first calculation unit performing an operation on the input signal in accordance with a first coefficient that is based on the switching signal, a second calculation unit performing an operation on an output of the first calculation unit in accordance with a second coefficient that is based on the switching signal, a selection unit selecting one of the output of the first calculation unit and an output of the second calculation unit based on the switching signal, and a third calculation unit selecting one or both of the input signal and the output of the first calculation unit based on the switching signal and performing a predetermined calculation on the selected signal.

Abstract: A recursive type-IV discrete cosine transform system includes a first permutation device, a recursive type-III discrete cosine/sine transform device, a cosine/sine factor generation device, a recursive type-II discrete cosine/sine transform device, a second permutation device. The first permutation device performs two-dimensional order permutation operation on N digital signals for generating N two-dimensional first temporal signals. The recursive type-III discrete cosine/sine transform device repeats a type-III discrete cosine/sine transform for generating second temporal signals. The cosine/sine factor generation device sequentially performs cosine/sine factor multiplication and corresponding addition operations for generating third temporal signals. The recursive type-II discrete cosine/sine transform device repeats a type-II discrete cosine/sine transform for generating fourth temporal signals.

Abstract: In general, techniques are described for implementing an 8-point discrete cosine transform (DCT). An apparatus comprising an 8-point discrete cosine transform (DCT) hardware unit may implement these techniques to transform media data from a spatial domain to a frequency domain. The 8-point DCT hardware unit includes an even portion comprising factors A, B that are related to a first scaled factor (?) in accordance with a first relationship. The 8-point DCT hardware unit also includes an odd portion comprising third, fourth, fifth and sixth internal factors (G, D, E, Z) that are related to a second scaled factor (?) in accordance with a second relationship. The first relationship relates the first scaled factor to the first and second internal factors. The second relationship relates the second scaled factor to the third internal factor and a fourth internal factor, as well as, the fifth internal factor and a sixth internal factor.

Abstract: A method and system for adaptive matrix trimming in an inverse discrete cosine transform (IDCT) operation. At least one row of an input matrix is accessed. At least one matrix element of the row having a value of zero is detected. During execution of an IDCT multiplication operation on the row for generating an output row, IDCT multiplication operation for a matrix element having a value of zero is skipped.

Abstract: Methods and apparatus for relative pitch tracking of multiple arbitrary sounds. A probabilistic method for pitch tracking may be implemented as or in a pitch tracking module. A constant-Q transform of an input signal may be decomposed to estimate one or more kernel distributions and one or more impulse distributions. Each kernel distribution represents a spectrum of a particular source, and each impulse distribution represents a relative pitch track for a particular source. The decomposition of the constant-Q transform may be performed according to shift-invariant probabilistic latent component analysis, and may include applying an expectation maximization algorithm to estimate the kernel distributions and the impulse distributions. When decomposing, a prior, e.g. a sliding-Gaussian Dirichlet prior or an entropic prior, and/or a temporal continuity constraint may be imposed on each impulse distribution.

Abstract: The present invention relates to a efficient implementation of integer and fractional 8-length or 4-length, or 8×8 or 4×4 DCT in a SIMD processor as part of MPEG and other video compression standards.

Abstract: In a data processing system, a method and system employing high fidelity inverse discrete cosine transform (IDCT) and discrete cosine transform (DCT) algorithms are provided. The values of the coefficients in a two-dimensional (2D) transform utilized in the IDCT and DCT algorithms may approximate the ideal integer output with sufficient visual quality. The transform coefficients may match a portion of the most significant bits (MSBs) or properly rounded bits of the coefficients of a reference transform matrix within an upper bound. The IDCT and DCT algorithms may specify constraints based on separating the 2D transform operation into two 1D transform operations in order to determine a minimum-bit width for each of the transform coefficients. The minimum-bit width may also be based on integer-bit precision of the data to be processed by the IDCT and DCT algorithms.

Abstract: A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.

Abstract: A discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuit includes a microcode memory, a processor, and a butterfly operation circuit. The microcode memory stores multiple microcode groups corresponding to DCT/IDCT operations and each of the microcode groups includes a series of microcodes. The processor obtains one of the microcode groups corresponding to one of the DCT/IDCT operations to be performed and retrieves microcodes in the obtained microcode group in sequence. The butterfly operation circuit performs butterfly operations according to the retrieved microcodes to execute one of the DCT/IDCT operations.

Abstract: A hardware implementation method for concurrently realizing overlap filter and core transform and an operation method thereof are provided. The overlap filter and core transform can be adjusted according to different specifications, processes, and operation frequencies. The hardware implementation method and the operation method thereof adopt a transform-level hardware sharing architecture and multi-port input/output register array, thereby efficiently realizing overlap filter and core transform.

Abstract: A method for receiving a pilot symbol in a receiver is disclosed. In one embodiment, the method includes removing a cyclic prefix from a received sequence to produce a modified sequence, transforming the modified sequence to a first frequency domain sequence according to a first transform, demapping a plurality of distributed subcarriers in the transformed modified sequence to extract a plurality of received symbols, deriving an intermediate channel estimate for each of the plurality of received symbols, and interpolating a final channel estimate based on the plurality of derived intermediate channel estimates. In one exemplary embodiment, the received symbols have one or more predefined characteristics such as a constant amplitude, and zero autocorrelation (CAZAC sequence).

Abstract: The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

Abstract: For converting first and second blocks of discrete values into a transformed representation, the first block is transformed according to a first transformation rule and then rounded. Then, the rounded transformed values are summed with the second block of original discrete values, to then process the summation result according to a second transformation rule. The output values of the transformation via the second transformation rule are again rounded and then subtracted from the original discrete values of the first block of discrete values to obtain a block of integer output values of the transformed representation. By this multi-dimensional lifting scheme, a lossless integer transformation is obtained, which can be reversed by applying the same transformation rule, but with different signs in summation and subtraction, respectively, so that an inverse integer transformation can also be obtained.

Abstract: A signal processing device and an image processing device are provided. The signal processing device includes a matrix calculator for performing a matrix operation selected by a switch part among a DCT matrix operation, a Haar matrix operation, and a Slant matrix operation, with respect to an input signal. Thus, the signal processing device can be implemented in a hybrid architecture capable of selectively processing the DCT-II transform, the Haar transform, and the Slant transform with a single chip.

Abstract: A method for transforming a digital signal from the time domain into the frequency domain and vice versa using a transformation function comprising a transformation matrix, the digital signal comprising data symbols which are grouped into a plurality of blocks, each block comprising a predefined number of the data symbols. The method includes the process of transforming two blocks of the digital signal by one transforming element, wherein the transforming element corresponds to a block-diagonal matrix comprising two sub matrices, wherein each sub-matrix comprises the transformation matrix and the transforming element comprises a plurality of lifting stages and wherein each lifting stage comprises the processing of blocks of the digital signal by an auxiliary transformation and by a rounding unit.

Abstract: The present invention provides a unified inverse discrete cosine transform (IDCT) microcode processor engine, which is able to process IDCT with different video standards and also achieves the processing speed requirement. The microcode processor engine comprises a read unit for reading input data; a shift left unit comprising: a first shift left block for left-shifting input data; and a second shift left block for left-shifting input data; an add unit for adding data output from the shift left unit; and a shift right unit for right-shifting data output from the add unit. The present invention also provides a system of inverse discrete cosine transform.

Abstract: A method for performing a domain transformation of a digital signal from the time domain into the frequency domain and vice versa, the method including performing the transformation by a transforming element, the transformation element comprising a plurality of lifting stages, wherein the transformation corresponds to a transformation matrix and wherein at least one lifting stage of the plurality of lifting stages comprises at least one auxiliary transformation matrix and a rounding unit, the auxiliary transformation matrix comprising the transformation matrix itself or the corresponding transformation matrix of lower dimension. The method further comprising performing a rounding operation of the signal by the rounding unit after the transformation by the auxiliary transformation matrix.

Abstract: A video codec method is provided, for processing video data processed by a Discrete Cosine Transformation (DCT) operation, comprising: (a) if a transformation matrix having a plurality of coefficients comprises at least one non-integer coefficient among the coefficients, multiplying the transformation matrix by a multiplication factor ? to make all coefficients of the transformation matrix integers, (b) estimating a compensation set, (c) performing a Column in Row out IDCT two-dimensional operation on the video data according to the transformation matrix and the compensation set, to obtain a compensated two-dimension operation result, (d) selectively dividing the compensated two-dimension operation result by ?2 to obtain an IDCT operation result.

Abstract: The present invention provides method and apparatus of a fast DCT implementation. DCT calculation is combined with quantization scales by a procedure of pre-processing. During DCT coefficient calculation, only non-zero coefficients are calculated. If pixel variance range is smaller than a first predetermined threshold, a predetermined lookup table is compared to decide the DCT coefficients. When a pixel variance range of a block pixels is within the second threshold, coupled with the quantization scales, the pre-processing determines the amount of non-zero DCT coefficients need to be calculated. Only a limited amount of LSB bits within a block is applied in the calculation of DCT coefficients. A previously saved pixel with equal or closest pixel value is used to replace the operation of current pixel's multiplication.

Abstract: Techniques are described herein for privately aggregating distributed time-series data. A requestor provides a query sequence to users. Each user evaluates the query sequence on the user's time-series data to determine an answer sequence. Each user transforms its answer sequence to another domain, adds noise, and encrypts it for further processing by the requestor. The requestor combines these encrypted sequences in accordance with a homomorphic encryption technique to provide an encrypted summation sequence. The requestor provides the encrypted summation sequence to at least some of the users, who may in turn provide respective decryption shares to the requestor. The requestor combines the decryption shares in an effort to decrypt the encrypted summation sequence. Decrypting the encrypted summation sequence provides a summation of the encrypted sequences from the users, which may be transformed back to the original domain to estimate a summation of the answer sequences of the users.

Abstract: A system and method for successively transposing a matrix is disclosed. The device includes a plurality of data storage elements arranged as a two dimensional (2D) structure including X rows and Y columns. The device further includes write control logic coupled to the input of plurality of data storage elements for writing data in at least one virtual row. The device also includes read control logic coupled to the output of the plurality of data storage elements for reading the data from at least one virtual column, where the data write to the at least one virtual row and the data read from the at least one virtual column are performed substantially simultaneously during each cycle of operation such that the 2D structure is transposed successively with zero cycle delay between successive transposes.

Abstract: The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are loaded into a memory area of a core transform device and a variety of coding standards can thereby be handled by the same programmable core device. The core device is configured to process a certain sized data block, and the incoming source blocks are converted to conform to this size. After transformation, the proper sized result can be extracted from the transform device output. A switchable speed-up mode provides for 4-point transforms, rather than 8-point transforms. Alternatively, the invention also provides for dedicated transform hardware to be switchably used in conjunction with programmable transform hardware, depending upon the type of coding being used, and the speed of inverse transform desired.

Abstract: The present invention relates to a method and apparatus for calculating the Sum of Squared Differences (SSD) between a source block and a reconstructed block of image or video data encoding according to an encoding scheme such as H.264/AVC. In a preferred embodiment, the method computes the SSD by finding the SSD between coefficients of an integer transformed residual block and the corresponding inverse-quantized coefficients. Preferably the inverse quantized coefficients are found with the aid of a look up table. This method may save computing time and processing power compared to calculating the SSD directly from the source and reconstructed blocks. The SSD is related to the distortion caused by encoding and the method may be used in calculating the rate-distortion of a particular encoding mode. One embodiment of the invention encodes a block of data by selecting the encoding mode with the least rate-distortion.

Abstract: A method, system and computer program product that involves receiving and initializing a digital image. Quantization is preformed on the digital image using at least two multiplication operations. Finally, a compressed version of the digital image is presented for viewing and/or storage or transport.

Abstract: In general, techniques are described for implementing a 16-point inverse discrete cosine transform (IDCT) that is capable of applying multiple IDCTs of different sizes. For example, an apparatus comprising a 16-point inverse discrete cosine transform of type II (IDCT-II) unit may implement the techniques of this disclosure. The 16-point IDCT-II unit performs these IDCTs-II of different sizes to transform data from a spatial to a frequency domain. The 16-point IDCT-II unit includes an 8-point IDCT-II unit that performs one of the IDCTs-II of size 8 and a first 4-point IDCT-II unit that performs one of the IDCTs-II of size 4. The 8-point IDCT-II unit includes the first 4-point DCT-II unit. The 16-point IDCT-II unit also comprises an inverse 8-point DCT-IV unit that includes a second 4-point IDCT-II unit and a third 4-point IDCT-II unit. Each of the second and third 4-point IDCT-II units performs one of the IDCTs-II of size 4.

Abstract: A method of implementing a two-dimensional Inverse Discrete Cosine Transform on a block of input data. The method includes 1) generating a performance array for the columns of the input data; 2) performing a column-wise IDCT upon the input data, the IDCT performed in accordance with cases given for each of the columns by the performance array; (3) generating a row performance offset for rows of the input data; and 4) performing a row-wise IDCT upon the result data from the performing of the column-wise IDCT.

Abstract: An apparatus and circuit for performing a discrete cosine transformation of input signals. A discrete cosine transformation (DCT) apparatus includes a forward adder-tree module, a first set of multiplexers, a shared flow-graph module, an inverse adder-tree module, and a second set of multiplexers coupled in series. In operation, the multiplexers are configured to process input signals via the forward adder-tree module and the shared flow-graph module to perform a forward DCT of the input signals or via the shared flow-graph module and the inverse adder-tree module to perform an inverse discrete cosine transform of the input signals.

Abstract: The present invention relates to a efficient implementation of integer and fractional 8-length or 4-length, or 8×8 or 4×4 DCT in a SIMD processor as part of MPEG and other video compression standards.

Abstract: A method for reducing operations in a processing environment is provided that includes generating one or more binary representations, one or more of the binary representations being included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and then performing kernel extraction and optimization on one or more of the polynomials. One or more common subexpressions associated with the polynomials are identified in order to reduce one or more of the operations.

Abstract: A discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuit includes a microcode memory, a processor, and a butterfly operation circuit. The microcode memory stores multiple microcode groups corresponding to DCT/IDCT operations and each of the microcode groups includes a series of microcodes. The processor obtains one of the microcode groups corresponding to one of the DCT/IDCT operations to be performed and retrieves microcodes in the obtained microcode group in sequence. The butterfly operation circuit performs butterfly operations according to the retrieved microcodes to execute one of the DCT/IDCT operations.

Abstract: A discrete cosine transformation circuit comprising a pipeline with a memory stage and an arithmetic stage. The arithmetic stage comprises first and second arithmetic logic units (ALU). Each of the ALUs receives from the memory a set of image data, performs a first calculation on the set of image data and outputs calculation result thereof in a first clock cycle. A path in the circuit directs the result to the memory stage, such that at least one ALU can selectively receive the result from the path in a clock cycle subsequent to the first clock cycle.

Abstract: Reduced complexity inverse discrete cosine transform (IDCT) masks and a method for reducing the number of IDCT calculations in video decoding are provided. The method comprises: accepting an n×m matrix of DCT coefficients; performing (n?y) horizontal IDCT operations, where y is greater than 0; performing y scaling operations; and, generating an n×m block of pixel information. Some aspects of the method further comprise: performing (m?z) vertical IDCT operations, where z is in the range between 0 and m/2. In some aspects, performing (n?y) horizontal ICDT operations includes performing IDCT operations for the first (n?y) horizontal rows. Then, performing y scaling operations includes: selecting the DC component from the first position of each horizontal row; scaling the selected DC component; and, copying the scaled DC component into the remaining positions of each of horizontal row.

Abstract: In general, techniques are described that provide for 4×4 transforms for media coding. A number of different 4×4 transforms are described that adhere to these techniques. As one example, an apparatus includes a 4×4 discrete cosine transform (DCT) hardware unit. The DCT hardware unit implements an orthogonal 4×4 DCT having an odd portion that applies first and second internal factors (C, S) that are related to a scaled factor (?) such that the scaled factor equals a square root of a sum of a square of the first internal factor (C) plus a square of the second internal factor (S). The 4×4 DCT hardware unit applies the 4×4 DCT implementation to media data to transform the media data from a spatial domain to a frequency domain. As another example, an apparatus implements a non-orthogonal 4×4 DCT to improve coding gain.

Abstract: A device to perform DFT calculations, for example in a GNSS receiver, including two banks of multipliers by constant integer value, the values representing real and imaginary part of twiddle factors in the DFT. A control unit selectively routes the data through the appropriate multipliers to obtain the desired DFT terms. Unused multipliers are tied to constant input values, in order to minimize dynamic power.

Abstract: Fast digital implementations of the second generation curvelet transform for use in data processing are disclosed. One such digital transformation is based on unequally-spaced fast Fourier transforms (USFFT) while another is based on the wrapping of specially selected Fourier samples. Both digital transformations return a table of digital curvelet coefficients indexed by a scale parameter, an orientation parameter, and a spatial location parameter. Both implementations are fast in the sense that they run in about O(n2 log n) flops for n by n Cartesian arrays or about O(N log N) flops for Cartesian arrays of size N=n3; in addition, they are also invertible, with rapid inversion algorithms of about the same complexity.

Abstract: Methods (500, 800) and corresponding systems (100, 200, 300, 400, 900) for generating a pilot symbol (330) include providing an M-point parallel transform sequence that is a discrete Fourier transform of a CAZAC sequence (312, 504-508). The M-point parallel transform sequence (312) is distributed (316, 510) to a set of M subcarriers among N subcarriers to form an N-point frequency-domain sequence (318) wherein the M subcarriers are evenly spaced apart. An N-point inverse fast Fourier transform (320, 512) is performed to convert the N-point frequency-domain sequence to an N-point time-domain sequence (322). The N-point time-domain sequence is converted (324, 514) to a serial sequence (326), and a cyclic prefix is added (328, 516) to the serial sequence to form a pilot symbol (330).

Abstract: The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

Abstract: A single stage computation method to perform a discrete cosine transform operation is provided. The discrete cosine transform operation is performed by executing a plurality of very large instruction words (VLIW) using a digital signal processor. The plurality of very large instruction words includes a first number of multiplications and a second number of additions, where the first number of multiplications is greater than the second number of additions.

Abstract: Systems and methods are disclosed to perform fast discrete cosine transform (DCT) by computing the DCT in five stages using three coefficients, and scaling the outputs using a plurality of scaling coefficients.

Abstract: First and second integer transform matrices can be used to approximate the discrete cosine transform. An input matrix of data is multiplied by a first transform matrix of integers to produce an intermediate matrix of data. The intermediate matrix is multiplied by a second transform matrix of integers to produce a transform result matrix of data. The multiplications by the first and second transform matrices can be pipelined to increase throughput. A plurality of transform data paths can also be provided in parallel to increase throughput.

Abstract: A processor includes a multi-stage pipeline having a plurality of stages. Each stage is capable of receiving input values and providing output values. Each stage performs one of a plurality of data transformations using the input values to produce the output values. The data transformations collectively approximate at least one of: a discrete cosine transform and an inverse discrete cosine transform. The stages do not use any multipliers to perform the data transformations.

Abstract: A single stage computation method to perform a discrete cosine transform operation is provided. The discrete cosine transform operation is performed by executing a plurality of very large instruction words (VLIW) using a digital signal processor. The plurality of very large instruction words includes a first number of multiplications and a second number of additions, where the first number of multiplications is greater than the second number of additions.

Abstract: A system provides lossless split and merge processes of integer discrete cosine transform (DCT) transformed data such that the discrete cosine transform of one data block may be split into two half length DCT odd and even blocks for merging, with split and merge processes being lossless and are generated in the discrete cosine transformed domain. After splitting, the redundancy existing between the two integer discrete cosine transformed half data blocks allows one to approximately reconstruct the original data block in case one of the discrete cosine transformed half data block is lost during transmission.

Abstract: The present invention performs a lossless four-point orthogonal transformation with reduced rounding errors using a simple configuration. A data transformation apparatus receives four items of vector data X0, X1, X2, and X3, ( Y 0 Y 1 Y 2 Y 3 ) = 1 1 + a 2 ? ( 1 a a a 2 a - 1 a 2 - a a a 2 - 1 - a a 2 - a - a 1 ) ? ( X 0 X 1 X 2 X 3 ) and determines D0 to D3 as: D0=X0+aX1+aX2+a2X3; D1=aX0?X1+a2X2?aX3; D2=aX0+a2X1?X2?aX3; and D3=a2X0?aX1?aX2+X3. Integer data smaller than half a divisor {1+a2} is added to D1 to determine D1?, and a value equal to half the divisor is added to D0, D2, and D3 to determine D0?, D2?, and D3?, respectively. D0?, D1?, D2?, and D3? are divided by the divisor and the results are rounded such that resulting integers are smaller than the results of division, and outputting the resulting integers.