Abstract: Circuitry performing Discrete Fourier Transforms. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. The circuitry includes a floating-point addition stage for adding mantissas of input values of the Discrete Fourier Transform operation, and a fixed-point stage for multiplying outputs of the floating-point addition stage by twiddle factors. The fixed-point stage includes memory for storing a plurality of sets of twiddle factors, each of those sets including copies of a respective twiddle factor shifted by different amounts, and circuitry for determining a difference between exponents of the outputs of the floating-point stage, and for using that difference as an index to select from among those copies of that respective twiddle factor in each of the sets.

Abstract: Methods (500, 800) and corresponding systems (100, 200, 300, 400, 900) for generating a pilot symbol (330) include providing an M-point parallel transform sequence that is a discrete Fourier transform of a CAZAC sequence (312, 504-508). The M-point parallel transform sequence (312) is distributed (316, 510) to a set of M subcarriers among N subcarriers to form an N-point frequency-domain sequence (318) wherein the M subcarriers are evenly spaced apart. An N-point inverse fast Fourier transform (320, 512) is performed to convert the N-point frequency-domain sequence to an N-point time-domain sequence (322). The N-point time-domain sequence is converted (324, 514) to a serial sequence (326), and a cyclic prefix is added (328, 516) to the serial sequence to form a pilot symbol (330).

Abstract: A pipeline Fast Fourier Transform (“FFT”) architecture for a programmable device is described. A first Radix-2 butterfly stage is coupled to receive a first input, configured to provide a first output responsive thereto, and configured to truncate at least one Least Significant Bit of the first output. A delay and swap stage is coupled to receive the first output and configured to provide a second output. A second Radix-2 butterfly stage is coupled to receive the second output and a second input, configured to provide a third output responsive thereto, and configured to truncate at least one Most Significant Bit of the third output. The first Radix-2 butterfly stage and the second Radix-2 butterfly stage are implemented in digital signal processing slices of a programmable device.

Abstract: A method and apparatus for performing complex mathematical calculations. The apparatus includes a multicore processor 10 where the cores 15 are connected 20 into a net with the processors on the periphery 15a primarily dedicated to input/output functions and distribution of tasks to the central processors 15b-h of the net. The central processors 15b-h perform calculations substantially simultaneously, far exceeding the speed of conventional processors. The method 100, which may be implemented by an instruction set to the processor nodes, informs the processor nodes how to divide the work and conduct the calculations. The method includes steps dividing the data into subsets 110 directing the subsets to predetermined nodes 115, performing the calculations 120 and outputting the results 125.

Abstract: FFT butterfly data sets may be stored in memory in a predetermined order. Such an order may allow a butterfly data set to be read from a single memory address location. The memory addressed may be computed by an address rotary function depending on the butterfly and stage of the FFT. Addressing the memory in such a manner may allow each butterfly data set of a subsequent FFT stage to be stored to a single memory location. Shuffle registers may delay the writing of FFT butterfly results to the memory until most of the data corresponding to a particular butterfly operation has been computed. The shuffle registers may rearrange and combine the results of one or more butterfly operations in a different manner from which they have been computed. Combining the results in this manner may allow a subsequent FFT stage to access data by addressing a single memory location.

Abstract: A transformation engine includes an address generator; a butterfly unit coupled to the address generator; a twiddle LUT coupled to the address generator; and a multiplier having a first input coupled to the butterfly unit and a second input coupled to the twiddle LUT.

Abstract: A circuit for a fast Fourier transform (FFT) operation is provided. The FFT operation circuit includes a plurality of butterfly operation units connected in series. Each of the plurality of butterfly operation units reads a signal in the order in which the plurality of butterfly operation units perform complex multiplication, addition, and subtraction, performs complex multiplication of each sequentially read signal by a complex coefficient corresponding to an FFT length and the stage number of the butterfly operation unit, and performs complex addition and subtraction with the complex multiplied signal. In this way, without disposing a plurality of operation circuits corresponding to a radix, FFT operations corresponding to a plurality of FFT lengths can be performed.

Abstract: A fast Fourier transform (FFT) architecture operable to transform data of variable point size includes a plurality of input ports, a plurality of memory elements, a crosspoint switch, a plurality of processing elements, and a plurality of output ports. The inputs ports read time-domain data from an external source. The memory elements store input data, intermediate calculation results, and output data. The crosspoint switch allows data to flow from any one architecture component to any other architecture component. The processing elements perform the FFT calculation. The output ports write frequency-domain data to an external source.

Abstract: A method for determining the position of impacts on an object comprising two acoustic sensors, and N active areas of said object, comprises the steps of: (a) receiving two acoustic signals S1(t) and S2(t); (b) calculating a sample signature function SIGS(?)=S1(?)?S2(?)*, where S1(?) and S2(?) are the respective Fourier transforms of S1(t) and S2(t), (c) comparing SIGS(?) with N predetermined reference signature functions SIGR,(?) corresponding to the predetermined area j for j from 1 to N; (d) determining the active area in which the impact occurred, on the basis of the comparison of step (c).

Abstract: A method and a system are provided for matching a fingerprint, for example, an audio fingerprint. In one example, the system receives, from a user device, a chapter and a query about the chapter. The chapter includes computer readable data generated from a waveform of an audio signal. The query is a request to receive data related to the chapter. The system generates, at a computer, a fingerprint of the chapter. The fingerprint includes at least a digital measure of certain properties of the waveform of the audio signal. The system generates, at a computer, a hash value of the fingerprint by applying a hash function to at least a portion of the fingerprint of the chapter. The hash value serves as an identifier for the fingerprint. The system looks up, in a database system, a matching hash value for the hash value of the fingerprint.

Abstract: A configurable fast Fourier transforms (FFT) apparatus to compute radix-2 and non-radix-2 calculations. The configurable FFT apparatus includes a data input, a data output, an interconnect, and a configuration manager. The data input retrieves an input data segment from a memory device. The data output stores processed data to the memory device. The interconnect routes radix FFT signals of multi-type radix configurations from the data input to the data output. The configuration manager dynamically configures the interconnect according to a determination of a current radix configuration.

Abstract: The present invention discloses a method of producing a multi-layered OFDM symbol using a plurality of small IFFT blocks. The produced OFDM symbol is able to reduce complexity in performing IFFT or FFT while maintaining orthogonality of a related art OFDM symbol. In particular, by avoiding the related art scheme using the N-sized IFFT, the layered IFFT is executed in a manner of grouping N data symbols into P groups each of which includes Q data symbols (N=P?Q). In order to produce an OFDM signal equal to that of the related art N-sized IFFT, it is preferable that phases are aligned for the data symbols on which Q-sized IFFT has been performed.

Abstract: The invention comprises an encoder for encoding a stegotext and a decoder for decoding the encoded stegotext, the stegotext being generated by modulating the log power spectrogram of a covertext signal with at least one key, the or each key having been added or subtracted in the log domain to the covertext power spectrogram in accordance with the data of the watermark code with which the stegotext was generated, and the modulated power spectrogram having been returned into the original domain of the covertext. The decoder carries out Fast Fourier Transformation and rectangular polar conversion of the stegotext signal so as to transform the stegotext signal into the log power spectrogram domain; subtracts in the log power domain positive and negative multiples of the key or keys from blocks of the log power spectrogram and evaluates the probability of the results of such subtractions representing an unmodified block of covertext in accordance with a predetermined statistical model.

Abstract: A system and method of performing acoustic thermography in which invalid data is filtered from data used to detect defects on a structure. An ultrasonic sound input signal is provided to a structure to produce a thermal image output. A sensor senses an input energy corresponding to the sound input signal and produces an input energy signal. The input energy signal is transformed to a test spectrum and is compared to a reference spectrum. The comparison of the test spectrum to the reference spectrum is used to determine whether to include the thermal image output in an analysis for detecting defects in the structure.

Abstract: The invention concerns a method for detecting a fault in a rotating field machine, in which current components are analysed in a flux-based, particularly rotor-flux-based, coordinate system a flux-forming current component being subjected to a frequency analysis in the flux-based, particularly rotor-flux-based, coordinate system. It is endeavoured to provide a simple method for an early detection of faults. For this purpose, a current operating point is detected for at least one predetermined supply frequency (fsp), said operating point being compared to a former operating point.

Abstract: The embodiments of the present invention provide a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements, comprising computing each butterfly of the first “log2P” stages on either a single processor or each of the “P” processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the “P” processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.

Abstract: A system described herein includes a receiver component that receives a query that pertains to a raw time-series signal. A query executor component selectively executes the query over at least one of multiple available compressed representations of the raw time-series signal, wherein the query pertains to at least one of one of determining a trend pertaining to the raw time-series signal, generating a histogram pertaining to the raw time-series signal, or determining a correlation pertaining to the raw time-series signal.

Abstract: A method for removing cyclic noise from a borehole image includes transforming the image into the frequency domain using a two-dimensional (2-D) Fourier Transform, removing cyclic noise components from the transformed image, and inverse transforming the image back into the spatial domain using an inverse 2-D Fourier Transform. The cyclic noise component may also be isolated by subtracting the corrected image from the original image or by removing all non-cyclic noise components from the transformed image prior to inverse transforming. Removal of the cyclic noise from a borehole image tends to enable the identification of borehole features and provide for improved accuracy in formation parameter evaluation. Evaluation of the cyclic noise component may also enable the source of the noise to be identified and mitigated.

Abstract: Embodiments of a hardware accelerator having a circuit configurable to perform a plurality of matrix operations and Fast Fourier Transforms (FFT) are presented herein.

Abstract: An orthogonal frequency division multiplexing (OFDM) transmitting apparatus including a signal processing unit, a subcarrier orthogonalization processing unit, and a transmitting unit is provided. The signal processing unit divides a received signal into several real parts and several corresponding imaginary parts. The subcarrier orthogonalization processing unit is coupled to the signal processing unit for receiving the real and the imaginary parts of the signal, and for making the real and the imaginary parts respectively carried by a plurality of different and orthogonal subcarriers. The transmitting unit is coupled to the subcarrier orthogonalization processing unit to transmit the subcarriers.

Abstract: The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.

Abstract: A pipelined FFT circuit used for processing a sequential input data with a set of N samples comprises a data division unit, a data-preprocessing unit and M sets of data computation unit. The data division unit is used for dividing the sequential input data into a first input data stream and a second input data stream. The data-preprocessing unit receives the first and second input data streams and orders the first input data stream to an odd number-index data stream, the second input data stream to an even number-index data stream respectively. Each of the data computation units has a data switch and a butterfly computator connected with the data switch, where M=log2N, the data switch of the first data computation unit is connected with the data-preprocessing unit.

Abstract: A method for finite impulse response (FIR) digital filtering is provided that includes generating a frequency domain sample block from an input sample block of length L, adding the computed frequency domain sample block to a reverse time-ordered set of previously generated frequency domain sample blocks as a newest frequency domain sample block, computing a spectral multiplication of each of K newest frequency domain sample blocks in the reverse time-ordered set with a corresponding frequency domain filter block in a time-ordered set of K frequency domain filter blocks of a FIR filter, adding the K results of the K spectral multiplications to generate an output spectral block, inverse transforming the output spectral block to generate a time domain output block, and outputting L filtered output samples from the time domain output block.

Abstract: A linear transform such as a Fast Fourier Transform (FFT) is performed on an input data set having a number of points using one or more arrays of concurrent threads that are capable of sharing data with each other. Each thread of one thread array reads two or more of the points, performs an appropriate “butterfly” calculation to generate two or more new points, then stores the new points in a memory location that is accessible to other threads of the array. Each thread determines which points it is to read based at least in part on a unique thread identifier assigned thereto. Multiple transform stages can be handled by a single thread array, or different levels can be handled by different thread arrays.

Abstract: Provided is a method for transforming data using a look-up table. The method includes the steps of: (a) mapping pre-processed input binary data to a constellation diagram divided into four quadrants to output a first complex number; (b) performing addition/subtraction operations between real numbers and between imaginary numbers with respect to the first complex number and a second complex number; and (c) reading a fourth complex from a look-up table in response to the first complex number, the second complex number and a third complex number, the look-up table outputting the fourth complex by performing a subtraction operation on multiplication results between real numbers and between imaginary numbers and an addition operation on multiplication results between the real numbers and the imaginary numbers with respect to the result value of the step (b) and the third complex number.

Abstract: In at least some embodiments, a method is provided. The method includes receiving samples from a first input channel and a second input channel. The method further includes controlling commutators to selectively switch samples between the first and second input channels for input to a radix-2 butterfly. The method further includes continuously activating the radix-2 butterfly while processing samples received from the first input channel followed by samples received from the second input channel.

Abstract: A system (100) and method (400) for peak limiting suitable for use in a communication system is provided. The method can include modulating (402) a symbol vector to produce a modulated waveform (500), wherein the symbol vector contains at least one symbol in at least one subcarrier (130), computing (404) at least one symbol adjustment that is based on at least one peak overshoot (512) of the modulated waveform, and applying (406) the at least one symbol adjustment to the symbol vector in accordance with an assigned weighting for reducing a peak power of the modulated waveform. The method limits an energy in the at least one subcarrier to a prespecified level of distortion.

Abstract: A processor for performing a Fast Fourier Transform and/or an Inverse Fast Fourier Transform of a complex input signal comprises a first stage for passing the input signal to a second stage when a Fast Fourier Transform procedure is to be performed and for swapping the real and imaginary components of the complex input signal before passing the signal to the second stage if an Inverse Fast Fourier Transform procedure is to be performed. The second stage has first and second radix-4 butterfly elements. A third stage is arranged to switch between first and second operating modes, the second operating mode being for processing a complex conjugate symmetrical input signal. A fourth stage has a plurality of processing units, one or more of the processing units comprising a radix-2 pipelined Fast Fourier Transform processor.

Abstract: An information processing system for performing a transform of a multidimensional matrix in a distributed memory network. The method includes storing a multidimensional matrix of side N in a distributed memory network with a plurality of nodes and distributing work associated with a calculation of a transform of the matrix among N2 of the plurality of nodes. The system further includes a receiver for receiving results of the calculation of the transform of the matrix by the nodes.

Abstract: Methods (500, 800) and corresponding systems (100, 200, 300, 400, 900) for generating a pilot symbol (330) include providing an M-point parallel transform sequence that is a discrete Fourier transform of a CAZAC sequence (312, 504-508). The M-point parallel transform sequence (312) is distributed (316, 510) to a set of M subcarriers among N subcarriers to form an N-point frequency-domain sequence (318) wherein the M subcarriers are evenly spaced apart. An N-point inverse fast Fourier transform (320, 512) is performed to convert the N-point frequency-domain sequence to an N-point time-domain sequence (322). The N-point time-domain sequence is converted (324, 514) to a serial sequence (326), and a cyclic prefix is added (328, 516) to the serial sequence to form a pilot symbol (330).

Abstract: A receiver including a processor. A plurality of Fast Fourier Transforms of a plurality of signal segments of a signal can be determined by the processor. The plurality of Fast Fourier Transforms are stored. A frequency shift of the signal can be determined recursively based on the stored plurality of Fast Fourier Transforms of the plurality of signal segments.

Abstract: Disclosed are apparatus and methods for dynamic data-based scaling of data. The disclosed methods and apparatus involve storing one or more input data samples, which are to be scaled and input to a processing function such as a Fast Fourier Transform. A scaling value operable for scaling the one or more data samples is determined based on the one or more input data samples, and then the stored data samples are scaled based on the computed scaling value when read out of storage prior to the processing function. The scaling of data based on the input data allows the data to be scaled dynamically, not statically, and ensures that the data fits within a desired bit width constraint of the processing function thereby economizing processing resources.

Abstract: A signal converter having a memory bank and radix-2 Fast Fourier Transform (FFT) transforms an Orthogonal Frequency Division Multiplexing (OFDM) signal having a long preamble and data into an OFDM signal in the frequency domain, and outputs the transformed OFDM signal. The radix-2 FFT has a linear systolic array architecture, transforms the long preamble stored in the memory bank by FFT, then stores the transformed long preamble into the memory bank, transforms data input through a buffering process and data input directly by FFT, and stores the transformed data in the memory bank. The memory bank has four memories, stores the long preamble transformed or not transformed and outputs the stored long preambles or the transformed data for the purpose of demodulation as the transformed data is input. Data-processing delay and/or power consumption may be reduced during the operation of the FFT processor.

Abstract: A filtering apparatus for obtaining an output in a case where a discrete-time signal having a length of N (N is an integer) is input to an FIR filter with a filter coefficient having a length of M (M is an integer, N?M?1), including: a division unit for dividing the discrete-time signal; a first zero padding unit for padding zero after the discrete-time signals; a first fast Fourier transform unit for performing FFT on the zero padded data; a second zero padding unit for padding zero after the filter coefficient; a second fast Fourier transform unit for performing FFT on the zero padded data; a multiplication unit for multiplying the frequency domain data by the frequency domain data; an inverse fast Fourier transform unit for performing IFFT on the multiplication results; and an adder unit for adding the discrete-time signals.

Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Abstract: An FFT operational device includes memory banks, an FFT operational circuit, and an FFT memory control circuit. The memory banks can overwrite pieces of data to specified address locations simultaneously or read out the data from the locations simultaneously. The operational circuit receives operands read out from the banks simultaneously to perform an FFT operation processing on the operands to output operation results simultaneously, and repeats the FFT operation processing a predetermined number of times. The memory control circuit receives the operation results output from the operational circuit simultaneously, and changes the order of the data in such a way that the pieces of data required for the operational circuit in the successive operation processing will be provided simultaneously. The resultant data are overwritten to the memory banks. The operational device thereby performs FFT or IFFT processing on hardware, the storage capacity thus being reduced with operational speed increased.

Abstract: The linear equalizer (LE) coefficients for code-division-multiplexed (CDM) pilot systems can be determined based upon frequency-domain calculations involving channel impulse responses. A channel impulse response can be formed at the mobile terminal by suitably filtering and despreading the received baseband signal with respect to the pilot Walsh channel. The channel frequency response is then determined based on the fast Fourier transform (FFT) of the channel impulse response. Frequency-domain equalizer coefficients can be determined from the channel frequency response. The frequency-domain equalizer coefficient can be utilized to determine time-domain equalizer coefficients to implement the equalizer in time domain, or be utilized to implement the equalizer in frequency domain.

Abstract: Provided two CORDIC processors, each including: two input ports representing real and imaginary input ports; and two output ports representing real and imaginary output ports; wherein real and imaginary parts of a first input signal are applied to the imaginary input ports of the first and second CORDIC processors; real and imaginary parts of a second input signal are applied to the real input ports of the first and second CORDIC processors; the first and second CORDIC processors rotate the respective input signals applied thereto by 45 degrees in the clockwise direction; respective data from the real output ports of said first and second CORDIC processors constitute real and imaginary parts of a first output signal; and respective data from the imaginary output ports of said first and second CORDIC processors constitute real part and imaginary part of a second output signal.

Abstract: A method, information processing system and computer readable medium for performing a transform of a multidimensional matrix in a distributed memory network. The method includes storing a multidimensional matrix of side N in a distributed memory network comprising a plurality of nodes and distributing work associated with a calculation of a transform of the matrix among N.sup.2 of the plurality of nodes. The method further includes receiving results of the calculation of the transform of the matrix by the nodes.

Abstract: A method and an apparatus for digital up-down conversion using an Infinite Impulse Response (IIR) filter are provided. The method for digital up-down conversion for frequency conversion in a mobile communication system using plural frequency converts, includes IIR-filtering, by a magnitude response IIR filter having the same magnitude response as in Finite Impulse Response (FIR) filtering, an input signal and a stable filter coefficient calculated according to a Levinson polynomial; and receiving, by the magnitude response IIR filter, the IIR filtered signal, and performing IIR filtering by a phase compensation IIR filter having a filter coefficient compensating for a non-linear phase to a linear phase.

Abstract: A method and apparatus for decoding digital quadrature phase shift keying data includes converting and intermediate frequency signal from an analog signal to a digital signal and digitally processing the digital signal to detect and decode the digital quadrature phase shift keying and extract encoded data.

Abstract: Audio/music visualizers have become standard features in most music/video software applications available for music/video players. The music visualizer presents the user with a beautiful presentation of music coupled with visuals that are synchronized to the music to create a compelling experience. The presented music visualizer provides a new ability to create a synchronized and personalized music visualization experience by a user without the need for programming. There are no preset effects, rather the user interacts with the visualizer system through a User Interface to create a visualization design through the use of video effects available through the UI. Once the design has been completed the system will synchronize the user's customized visualization design with an input musical selection. In this manner, the user has created their own customized music/video visualization which may also be stored for later playback or modification.

Abstract: A set of complex rotations are used to implement a unitary “Q” matrix in which each complex rotation is a set of real rotations, where the minimum number of real rotations to perform the complex rotation is three, and where the minimum number of angles to characterize the real rotations is two. The index-angle sets for each successive rotation can be provided by a complex rotor calculation unit, which may be collocated with the complex rotor computational unit, located in a controller such as a DSL optimizer, or located in any other suitable device or apparatus that has performed the QR factorization upon supplied matrix MIMO transfer functions for the vectored channel.

Abstract: An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.

Abstract: Among other things, a combination comprises interaction with a system that has a perturbation. In such perturbed system, a non-directional input is applied to a first variable of the system. Based on an asymmetry of the perturbed system, a directional effect is achieved in a second variable of the system, the first and second variables comprising a conjugate pair of variables. At least one of the following pertains: the interaction occurs other than by an apparatus and other than in a way that actually achieves the directional effect, or the conjugate pair is other than position and momentum, or the input or the asymmetry are in a dimension other than spatial coordinates, or the directional effect is other than translational motion and other than rotary motion.

Abstract: The ability to examine the frequency content of a signal is critical in a variety of fields, and many techniques have been proposed to fill this need, including the Fourier and wavelet family of transforms. One of these, the S-transform, is a Fourier based transform that provides simultaneous time and frequency information similar to the wavelet transform but uses sinusoidal basis functions to produce true frequency and globally referenced phase measurements. It has been shown to be useful in several medical imaging applications but its use is limited due to high computational requirements of the original, continuous form. The described embodiments include a general framework for describing linear time-frequency transforms, using the Fourier, wavelet and S-transforms as examples. As an illustration of the utility of this formalism, a fast discrete S-transform algorithm is developed that has the same computational complexity as the fast Fourier transform.

Abstract: A method of operating a data-processing unit to produce a transform comprises calculating first and second output data values based at least on first and second input data values. The method comprises reading the first and second input data values from locations of a first buffer, the locations being determined by first and second read addresses based on first and second read indices. The method also comprises writing the first and second output data values to adjacent memory locations of a second buffer during a single write cycle. Furthermore, the method comprises reading third and fourth input data values from locations of the second buffer, the locations being determined by third and fourth read addresses determined by swapping at least two of the bits of the first and second read indices respectively. A data-processing unit for producing a transform, a transform-computation unit and an electronic apparatus are also described.

Abstract: The present invention is two-iteration Fourier transform processor for performing Fourier transform of N data inputs into N data outputs. The processor comprises a plurality of two-iteration radix-r modules and a combination phase element. Each radix-r module comprises r radix-r butterflies, a feedback network and a plurality of switches. Each radix-r butterfly comprises r inputs and outputs and a butterfly processing element. The butterfly processing element includes a plurality of multipliers for multiplying the input data and corresponding coefficients and an adder for summing the multiplication outputs from the multipliers. The feedback network feeds outputs of the radix-r butterflies to the corresponding inputs of the radix-r butterfly and the switches selectively pass the input data or the feedback, alternately, to the corresponding radix-r butterfly. The combination phase element includes at least one stage of butterfly computing elements for combining the outputs from the r radix-r butterfly.

Abstract: A method may include storing N number of Fast Fourier Transform (FFT) data points into x-memories, N and x being integers greater than one, and the x-memories having a total memory capacity equivalent to store the N number of FFT data points, and reading K FFT data points of the N number of FFT data points from each of the x-memories so that the N number of FFT data points are read, K being an integer greater than one. The method may further include performing parallel radix-m FFTs on the x*K number of FFT data points, multiplying the x*K number of FFT data points by twiddle factors to obtain resultants, shifting the resultants, and writing back the shifted resultants of the x*K number of FFT data points to the x-memories.

Abstract: An N-point Fast Fourier Transform (FFT) using mixed radix stages with in-place data sample storage may be performed by decomposing N into a product of R sequential mixed radix stages of radix-r(i). N data samples are partitioned into at least B memory banks, where B is equal to a largest radix of the R radix stages. Each input data sample to each radix-r(i) butterfly comes from r(i) different memory banks and the output data samples are written to the same memory locations in the r(i) memory banks. Determining from which memory bank the input data samples and output data samples of the butterflies are stored is done based on the radix size and sequential position of the radix stage. Determining the address of the input data samples and the output data samples within each memory bank is based on the radix size and sequential position of the radix stage.