Abstract: A fast Fourier transform (FFT) circuit with an integrated half-bin offset for performing both an FFT and a half-bin offset on an input signal. The FFT circuit is configured to receive input samples of the input signal and generate output signals via a plurality of butterfly circuits and one or more twiddle stage multiplier circuits of the FFT circuit. One or more of the butterfly circuits are configured to implement a first portion of both the half-bin offset and the FFT by integrating a first set of computations for both the half-bin offset and the FFT within the one or more of the plurality of butterfly circuits. At least one of the one or more twiddle stage multiplier circuits is configured to implement a second portion of both the half-bin offset and the FFT by integrating a second set of computations of both the half-bin offset and the FFT within the twiddle stage multiplier circuit.

Abstract: A plurality of three bit units (called triplets) are permuted by a shuffler to shuffle the positions of the triplets into different patterns which are used to specific the read/write operation of a memory. For example, the least significant triplet in a conventional counter can be placed in the most significant position of a permuted three triplet pattern. The count of this permuted counter triplet generates addresses that jump 64 positions each clock cycle. These permutations can then be used to generate read and write control information to read from/write to memory banks conducive for efficient Radix-8 Butterfly operation. In addition, one or more triplets can also determine if a barrel shifter or right circular shift is required to shift data from one data lane to a second data lane. The triplets allow efficient FFT operation in a pipelined structure.

Abstract: A method and a system is provided for Coordinate Rotation Digital Computer (CORDIC) based matrix inversion of input digital signal streams from multiple antennas using an bi-directional ring-bus architecture. The bi-directional ring bus includes a first ring bus having signals flow in a clockwise direction, and a second ring bus having signals flow in a counter-clockwise direction. An I/O controller is coupled to the first and the second ring bus, respectively. A plurality of processing elements (PEs), where each of the plurality of PEs is coupled to the first and the second ring bus, respectively, wherein each of the plurality of PEs includes at least one CORDIC core for performing CORDIC iterations on the plurality of input digital stream signals to produce inversed matrix signals.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: Disclosed are apparatus and methods for dynamic data-based scaling of data. The disclosed methods and apparatus involve storing one or more input data samples, which are to be scaled and input to a processing function such as a Fast Fourier Transform. A scaling value operable for scaling the one or more data samples is determined based on the one or more input data samples, and then the stored data samples are scaled based on the computed scaling value when read out of storage prior to the processing function. The scaling of data based on the input data allows the data to be scaled dynamically, not statically, and ensures that the data fits within a desired bit width constraint of the processing function thereby economizing processing resources.

Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: The ability to examine the frequency content of a signal is critical in a variety of fields, and many techniques have been proposed to fill this need, including the Fourier and wavelet family of transforms. One of these, the S-transform, is a Fourier based transform that provides simultaneous time and frequency information similar to the wavelet transform but uses sinusoidal basis functions to produce true frequency and globally referenced phase measurements. It has been shown to be useful in several medical imaging applications but its use is limited due to high computational requirements of the original, continuous form. The described embodiments include a general framework for describing linear time-frequency transforms, using the Fourier, wavelet and S-transforms as examples. As an illustration of the utility of this formalism, a fast discrete S-transform algorithm is developed that has the same computational complexity as the fast Fourier transform.

Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: A circuit for converting frequency domain information to time domain information includes an Inverse Fast Fourier Transform circuit having a length of N coefficients. The Inverse Fast Fourier Transform circuit is adapted to receive input data of length N coefficients and generate output data of length N coefficients that are circularly shifted by m coefficients. The circuit also includes Cyclical Prefix Insertion circuit adapted to insert a cyclical prefix of length m. The Cyclical Prefix Insertion circuit includes a first switch, connected to the Inverse Fast Fourier Transform circuit, a buffer, having an input connected to the first switch and an output, the buffer having a length m, and a second switch, coupled to the first switch and to the buffer. The first and second switches selectively couple the output of the buffer and the Inverse Fast Fourier Transform circuit to an output of the second switch. The buffer is reduced to length m.

Abstract: The invention provides an integrated systolic architecture which can perform both forward and inverse Discrete Wavelet Transforms with a minimum of complexity. A plurality of processing cells, each having an adder and a multiplier, are coupled to a set of multiplexers and delay elements to selectively receive a single input datastream in the forward DWT mode and two datastreams in the inverse DWT mode. In the forward DWT mode, the integrated architecture decomposes the input datastream into two output sequences--a high frequency sub-band output and a low frequency sub-band output. In the inverse DWT mode, the integrated architecture reconstructs the original input sequence by outputting even terms and odd terms on alternating clock cycles. As a result, the architecture can achieve 100% utilization and is suitable to be implemented in VLSI circuitry.

Abstract: A high-performance photonic chipset for computing 1-D complex fast Fourier transform (FFT) calculations. Flip-chip integration is used to combine submicron CMOS ICs with GaAs chips containing 2-D arrays of multiple-quantum wells (MQW) diode optical receivers and transmitters on each chip in the set. Centralized free-space optical interconnection offers higher throughput rates, greater external bandwidth and reduced chip count compared to conventional electronic FFT devices using hard-wired interconnection between chips. The memory addressing used provides one-to-one interconnections for memory transfers between computational stages that are compatible with several known three-dimensional free-space optoelectronic packaging technologies and dual-port memory is used to permit simultaneous read-write access to adjacent addresses in the data banks needed by each stage.