Abstract: A vector operation core and a vector processor are provided. The vector operation core use two three-input adders and four data negators, so that the data input into the input adders may be flexibly negated. In addition to being provided with the vector operation core, the vector processor also comprises a control unit, which controls a selector and the negators in the vector operation core. The vector processor may simultaneously support butterfly operations in a base 2, base 3 and base 5 fast Fourier transform. The vector operation core may be widely applied to the design of the programmable vector processor in a multimode-compatible mobile terminal chip.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: A configurable fast Fourier transforms (FFT) apparatus to compute radix-2 and non-radix-2 calculations. The configurable FFT apparatus includes a data input, a data output, an interconnect, and a configuration manager. The data input retrieves an input data segment from a memory device. The data output stores processed data to the memory device. The interconnect routes radix FFT signals of multi-type radix configurations from the data input to the data output. The configuration manager dynamically configures the interconnect according to a determination of a current radix configuration.

Abstract: Provided two CORDIC processors, each including: two input ports representing real and imaginary input ports; and two output ports representing real and imaginary output ports; wherein real and imaginary parts of a first input signal are applied to the imaginary input ports of the first and second CORDIC processors; real and imaginary parts of a second input signal are applied to the real input ports of the first and second CORDIC processors; the first and second CORDIC processors rotate the respective input signals applied thereto by 45 degrees in the clockwise direction; respective data from the real output ports of said first and second CORDIC processors constitute real and imaginary parts of a first output signal; and respective data from the imaginary output ports of said first and second CORDIC processors constitute real part and imaginary part of a second output signal.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: A data reorganizer for Fourier Transforms, both forward and inverse, of multiple parallel data streams input to an integrated circuit, and method for use thereof, are described. The data reorganizer has a k input commutator, for k a positive integer greater than zero; an address generator; memory buffers; and an output commutator.

Abstract: Provided are a high-speed Discrete Fourier Transform (DFT) apparatus and a method thereof. The high-speed DFT apparatus includes a zero padding unit, a Fast Fourier Transform (FFT) unit, and a preamble index decision unit. The zero padding unit receives a first input signal having a length of a prime number and changes the first input signal into a second input signal having a length of an exponentiation of 2. The FFT unit performs a FFT on the second input signal outputted from the zero padding unit. The preamble index decision unit detects a preamble index from an output signal from the FFT unit.

Abstract: An apparatus and method for area and speed efficient fast Fourier transform (FFT) processing comprising mapping a one-dimensional DFT to a multi-dimensional representation; re-indexing the multi-dimensional representation as a radix 23 decimation architecture; simplifying the radix 23 decimation architecture to obtain a nested butterfly architecture; acquiring N samples of a finite duration time-sampled signal; and inputting the acquired N samples into the nested butterfly architecture to obtain a N-point fast Fourier transform (FFT) output.

Abstract: A technique for performing a discrete Fourier transform (DFT) includes storing, in a single-port memory, multiple signal points. A first group of consecutive ones of the multiple signal points are fetched (from a first line of the single-port memory) to a first input register associated with a processor that includes multiple arithmetic units (AUs) that are each configured to perform multiply accumulate (MAC) operations. A second group of consecutive ones of the multiple signal points are then fetched (from a second line of the single-port memory) to a second input register associated with the processor. Selected pairs of the multiple signal points are then loaded (one from each of the first and second input registers for each pair) into the multiple arithmetic units during an initial butterfly stage. Radix-2 butterfly operations are then performed on the selected pairs of the multiple signal points (using the multiple AUs) to provide respective output elements.

Abstract: An efficient circuit and method for performing radix-3 Discrete Fourier transform (DFT) of a 3*2M size data frame are provided. The data frame is split and fast Fourier transform (FFT) processed as three sub-frames. Radix-3 operations are performed on the FFT processed sub-frames over a number of stages with time shared hardware to compute the DFT of the data-frame. FFT operations are performed on the second and third sub-frames to produce respective sub-transforms. Concurrently with FFT processing of the first sub-frame, butterfly operations are performed on the sub-transforms of the second and third sub-frames. Through the use of time-shared hardware and arranging FFT operations to correspond with radix-3 operations at various stages of processing, the DFT is performed with existing FFT processors while reducing resource requirements and/or reducing DFT transform time over the full-parallel radix-3 implementation.

Abstract: A processor for performing a fast Fourier transform or inverse fast Fourier transform comprises a radix-2 butterfly structure; and a radix-4 butterfly structure. A method of performing a fast Fourier transform or inverse fast Fourier transform comprises selectively performing a radix-2 butterfly operation on an input data stream; and selectively performing a radix-4 butterfly operation on one of a result produced by the radix-2 butterfly operation and the input data stream. Apparatus for performing a fast Fourier transform or inverse fast Fourier transform comprises means for selectively performing a radix-2 butterfly operation on an input data stream; and means for selectively performing a radix-4 butterfly operation on one of a result produced by the radix-2 butterfly operation and the input data stream.

Abstract: An N-point Fast Fourier Transform (FFT) using mixed radix stages with in-place data sample storage may be performed by decomposing N into a product of R sequential mixed radix stages of radix-r(i). N data samples are partitioned into at least B memory banks, where B is equal to a largest radix of the R radix stages. Each input data sample to each radix-r(i) butterfly comes from r(i) different memory banks and the output data samples are written to the same memory locations in the r(i) memory banks. Determining from which memory bank the input data samples and output data samples of the butterflies are stored is done based on the radix size and sequential position of the radix stage. Determining the address of the input data samples and the output data samples within each memory bank is based on the radix size and sequential position of the radix stage.

Abstract: A memory-based Fast Fourier Transform device is provided, which adopts single-port random access memory (RAM), rather than dual-port RAM, as a storage, and the circuit area of the FFT device is therefore reduced. In order to enhance the access efficiency of the memory and the use efficiency of a processor, the transformer adopts a modified in-place conflict-free addressing to achieve similar performance of a traditional Fast Fourier Transform device.

Abstract: A system and method Fast Fourier Transform (FFT) method in a multi-mode wireless processing system. The method can include loading an input vector into an input buffer, initializing a second counter and a variable N, where N=log2 (input vector size), and s is the value of the second counter, performing an FFT stage, and comparing s to N and performing additional FFT stages until s=N. Performing the FFT stage can include performing vector operations on data in the input buffer and sending results to an output buffer, the data in the input buffer comprising a plurality of segments, advancing the value of the second counter; and switching roles of the input and output buffers. The vector operations can include performing Radix-4 FFT vector operations on the four input data at a time and multiplying the resulting output vectors with a Twiddle factor.

Abstract: A circuit for converting frequency domain information to time domain information includes an Inverse Fast Fourier Transform circuit having a length of N coefficients. The Inverse Fast Fourier Transform circuit is adapted to receive input data of length N coefficients and generate output data of length N coefficients that are circularly shifted by m coefficients. The circuit also includes Cyclical Prefix Insertion circuit adapted to insert a cyclical prefix of length m. The Cyclical Prefix Insertion circuit includes a first switch, connected to the Inverse Fast Fourier Transform circuit, a buffer, having an input connected to the first switch and an output, the buffer having a length m, and a second switch, coupled to the first switch and to the buffer. The first and second switches selectively couple the output of the buffer and the Inverse Fast Fourier Transform circuit to an output of the second switch. The buffer is reduced to length m.

Abstract: The device determines the weighting coefficients to be applied to N digital source signals to form a composite signal. The first- to third-order moments of the composite signal must respectively present mean value, variance and skewness characteristics predefined by a user. The device introduces an additional variable, in the form of a weighting matrix W. The vector w being the vector of the weighting coefficients and wT the transpose of the vector w, the difference W?wwT is a positive semidefinite matrix. Moreover, the device performs linearization, around a vector wref of reference weighting coefficients, of the skewness constraint on the third-order moments using a matrix A = [ W w w T 1 ] as further intermediate variable.

Abstract: A data transform system performs FFT and IFFT computations with respect to N data points. The data transform system performs radix-R (R is an integer) butterfly computation in parallel by use of M arithmetic elements. Serial and parallel computation structures a recombined to provide a system that provides for optimal trade-off between system speed and the size of the resulting hardware.

Abstract: A data processing apparatus having data cache performs an N-point radix-R Fast Fourier Transform. If the data set is smaller than the data cache, the data processing apparatus performs the Fast Fourier Transform in logRN stages on all the data set in one pass. If the data set is larger than the data cache but smaller than R times the data cache, the data processing apparatus performs a first stage radix-R butterfly computation on all the input data producing R independent intermediate data sets. The data processing apparatus then successively performs second and all subsequent stage butterfly computations on each independent intermediate data set in turn producing corresponding output data. During the first stage radix-R butterfly computations, each of R continuous sets are separated in memory by memory locations equal to the size of a cache line.

Abstract: A high-speed radix-4 butterfly module and the method of performing Viterbi decoding using the same. The high-speed radix-4 butterfly module includes first to fourth add-compare-select (ACS) circuits. The first and the second ACS circuits receive first to fourth branch metric values and first to fourth previous-stage path metric values, and accordingly produces a first and a second path metric values. The third and the fourth ACS circuits receive fifth to eighth branch metric values and the first to the fourth previous-stage path metric values, and accordingly produces a third and a fourth path metric values. The radix-4 butterfly unit of the invention uses the symmetric relation to reduce an amount of branch computation required for each radix-4 butterfly unit to a half. Thus, the circuit complexity of the typical radix-4 butterfly module and the hardware cost of the Viterbi decoder are reduced.

Abstract: A data transform system performs FFT and IFFT computations with respect to N data points. The data transform system performs radix-R (R is an integer) butterfly computation in parallel by use of M arithmetic elements. Serial and parallel computation structures a recombined to provide a system that provides for optimal trade-off between system speed and the size of the resulting hardware.

Abstract: A method for processing a received signal at a mobile receiver of a wireless communications system is disclosed. The method comprises demodulating the received signal to obtain an analog base band signal and converting the analog base band signal into a digital base band signal. The signal strength of the digital base band signal is estimated and, using the estimation, the digital base band signal is scaled by a scaling factor. The digital base band signal is equalized into an equalized digital signal which is then rescaled by a resealing factor.

Abstract: A system for efficiently filtering interfering signals in a front end of a GPS receiver is disclosed. Such interfering signals can emanate from friendly, as well as unfriendly, sources. One embodiment includes a GPS receiver with a space-time adaptive processing (STAP) filter. At least a portion of the interfering signals are removed by applying weights to the inputs. One embodiment adaptively calculates and applies the weights by Fourier Transform convolution and Fourier Transform correlation. The Fourier Transform can be computed via a Fast Fourier Transform (FFT). This approach advantageously reduces computational complexity to practical levels. Another embodiment utilizes redundancy in the covariance matrix to further reduce computational complexity. In another embodiment, an improved FFT and an improved Inverse FFT further reduce computational complexity and improve speed.

Abstract: An FFT (Fast Fourier Transform) processor is disclosed which is a core block of an OFDM (Orthogonal Frequency Division Multiplexing) or DMT (Discrete Multi-tone) MODEM. The FFT processor simultaneously performs sequential input and output by applying an in-place algorithm for a mixed-radix multi-bank memory, thereby realizing continuous processing with only a 2N-word memory having 4 banks. The FFT processor minimizes its complexity while satisfying a high-speed calculation requirement.

Abstract: The post-processing of the transformation processing of an interleaved type is temporally nested with regards to two successive symbols, and includes storage in two separately addressable memories of identical size. The addressing of the two memories is performed successively and alternately in the natural and reverse order at the frequency with the symbol clock signal.

Abstract: A system and a method for signal processing by employing parallel paths (107 and 110) for processing separate parts of the signal. The method effectively doubles operating speed by providing at least two processing paths. Where two paths are used, each operates at approximately one-half of the data rate of the incoming data signal. By using parallel paths to process signals through a FIR filter (100), for example, the method can take full advantage of a high order encoding system, such as Radix-8. Further, because of relaxed clock speeds, a preferred embodiment allows use of smaller and faster latches (103), instead of flip-flops, for the retiming stages. Finally, when used with a FIR filter (100), the method makes use of the normal irregularity of critical path delays at various stages by borrowing retiming slacks from less time-critical taps (101) of the FIR filter (100).

Abstract: An electronic device for computing a Fourier transform having a pipeline architecture includes at least one processing stage with a radix equal to 4. Each processing stage includes elementary processing for performing process operations for Fourier transforms of size equal to 4 on data blocks. Each processing stage also includes an elementary storage that includes a random access memory. In particular, the random access memory is a single-access memory with a storage capacity equal to 3N/4 data bits. The size of the data block processed by this stage is equal to N.

Abstract: A pipelined FFT (fast Fourier transform) processor including a CBFP (convergent block floating point) algorithm, includes an inverse multiplexer for inverse-multiplexing an 8K-/2K-point input data, a first to sixth radix-4 operation circuit for receiving an output of the inverse multiplexer and performing a butterfly operation, a multiplexer connected between the first and second radix-4 operation circuits and for selectively outputting an output of the inverse multiplexer or a first butterfly unit, a radix-2 operation circuit connected to the sixth radix-4 operation circuits and for performing a butterfly operation, a convergent block floating point circuit connected to respective output terminals of the radix-4 operation circuit and the radix-2 operation circuit and for scaling a butterfly operation result, an addition circuit for accumulation and adding scaling indexes outputted from the convergent block floating point circuit, and a decoder for scaling an output of the radix-2 operation circuit in accorda

Abstract: A pipelined Fast Fourier Transform Processor includes, besides a memory arrangement, a cascade of a first arithmetic unit, a scratch memory and a second arithmetic unit. One of both arithmetic units can only perform at least one type of butterfly Fast Fourier Transform arithmetic calculations, whereas the other one can perform, besides this at least one type of butterfly Fast Fourier Transform arithmetic calculations, at least one second type of butterfly Fast Fourier Transform arithmetic calculations. This architecture optimises both timing as well as circuit restrictions.

Abstract: For each input block of N data bits received as an input to a stage for computing a Fourier transform, only three quarters of the data bits of the input block are stored in a main storage. A Fourier transform computation is performed on the basis of the stored data and of the other data of the block. Only half of the data bits received are stored in an auxiliary storage. All the data bits of the input block are reconstructed from the contents of the main and auxiliary storage to obtain a reconstructed data block, which is temporally delayed with respect to the input block.

Abstract: A real-time pipeline processor, which is particularly suited for VLSI implementation, is based on a hardware oriented radix-2.sup.2 algorithm derived by integrating a twiddle factor decomposition technique in a divide and conquer approach. The radix-2.sup.2 algorithm has the same multiplicative complexity as a radix-4 algorithm, but retains the butterfly structure of a radix-2 algorithm. A single-path delay-feedback architecture is used in order to exploit the spatial regularity in the signal flow graph of the algorithm. For a length-N DFT transform, the hardware requirements of the processor proposed by the present invention is minimal on both dominant components: Log4N-1 complex multipliers, and N-1 complex data memory.

Abstract: A fast Fourier transform (FFT) processor is constructed using discrete Fourier transform (DFT) butterfly modules having, in preferred example embodiments, sizes greater than 4. In a first example embodiment, the FFT processor employs size-8 butterflies. In a second example embodiment, the FFT processor employs size-16 butterflies. In addition, low power, fixed coefficient multipliers are employed to perform nontrivial twiddle factor multiplications in each butterfly module. The number of different, nontrivial twiddle factor multipliers is reduced by separating trivial and nontrivial twiddle factors and by taking advantage of twiddle factor symmetries in the complex plane and/or twiddle factor decomposition. In accordance with these and other factors, the present invention permits construction of an FFT processor with minimal power and IC chip surface area consumption.