Multi-valued Patents (Class 708/493)
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Patent number: 11509291Abstract: A zero-insertion FIR filter architecture for filtering a signal with a target band and a secondary band. Digital filter circuitry includes an L-tap FIR (finite impulse response) filter, with a number L filter tap elements (L=0, 1, 2, . . . (L?1)), each with an assigned coefficient from a defined coefficient sequence. The L-tap FIR filter is configurable with a defined zero-insertion coefficient sequence of a repeating sub-sequence of a nonzero coefficient followed by one or more zero-inserted coefficients, with a number Nj of nonzero coefficients, and a number Nk of zero-inserted coefficients, so that L=Nj+Nk. The L-tap FIR filter is configurable as an M-tap FIR filter with a nonzero coefficient sequence in which each of the L filter tap elements is assigned a non-zero coefficient, the M-tap FIR filter having an effective length of M=(Nj+Nk) non-zero coefficients.Type: GrantFiled: March 12, 2019Date of Patent: November 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jawaharlal Tangudu, Jaiganesh Balakrishnan
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Patent number: 11294631Abstract: An adder circuit that includes an operand input and a second operand input to an XNOR cell. The XNOR cell is configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell transforms the output of the XNOR cell into a carry out signal.Type: GrantFiled: October 23, 2019Date of Patent: April 5, 2022Assignee: NVIDIA Corp.Inventors: Ilyas Elkin, Ge Yang, Xi Zhang
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Patent number: 11169779Abstract: An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.Type: GrantFiled: February 27, 2020Date of Patent: November 9, 2021Assignee: NVIDIA Corp.Inventors: Ilyas Elkin, Ge Yang, Xi Zhang
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Patent number: 10853721Abstract: According to an embodiment, a multiplier accumulator includes a controller, a high-order multiplier, a high-order accumulator, a low-order multiplier, and an output unit. The controller is configured to designate each digit within a range of the most significant digit in a coefficient for an input value to a stop digit as a target digit. The high-order multiplier is configured to calculate a high-order multiplication value by multiplying the input value, and a value and a weight of the target digit. The high-order accumulator is configured to calculate a high-order accumulation value by accumulatively adding the high-order multiplication values for input values. The low-order multiplier is configured to calculate a low-order multiplication value by multiplying an input value and a value of a digit smaller than the stop digit. The output unit is configured to output a value determined based on whether the high-order accumulation value exceeds a boundary value.Type: GrantFiled: August 24, 2017Date of Patent: December 1, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Masafumi Mori, Takao Marukame, Tetsufumi Tanamoto, Satoshi Takaya
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Patent number: 10489610Abstract: Systems and methods are discussed herein for reusing hardware for encryption and authentication, where the hardware has a fixed input bandwidth, and where the hardware has the same bandwidth for a different input bandwidth. In order to accomplish this mechanism, systems and methods are provided herein for processing invalid data that appears within streams of valid data. Systems and methods are also provided herein for authentication mechanisms that require more than one data cycle to complete.Type: GrantFiled: August 27, 2018Date of Patent: November 26, 2019Assignee: Altera CorporationInventor: Robert Groza
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Patent number: 10409556Abstract: A binary logic circuit for determining the ratio x/d in accordance with a rounding scheme, where x is a variable integer input of bit length w and d is a fixed positive integer of the form 2n±1, the binary logic circuit being configured to form the ratio as a plurality of bit slices, the bit slices collectively representing the ratio, wherein the binary logic circuit is configured to generate each bit slice according to a first modulo operation for calculating mod(2n±1) of a respective bit selection of the input x and in dependence on a check for a carry bit, wherein the binary logic circuit is configured to, responsive to the check, selectively combine a carry bit with the result of the first modulo operation.Type: GrantFiled: October 30, 2017Date of Patent: September 10, 2019Assignee: Imagination Technologies LimitedInventor: Thomas Rose
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Patent number: 10365538Abstract: According to an embodiment, a quantum computer includes first physical systems provided in a cavity, a second physical system provided in the cavity, and a light source unit. The first physical systems include a transition coupled to a common cavity mode of the cavity. The second physical system includes a first transition coupled to the common cavity mode and a second transition. The light source unit generates a first and a second light beam to manipulate two of the first physical systems and generates a third light beam that resonates with the second transition. The third light beam is radiated to the second physical system during a period when the first and the second light beam are simultaneously radiated to the two first physical systems.Type: GrantFiled: June 9, 2016Date of Patent: July 30, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Nakamura, Kouichi Ichimura, Hayato Goto, Mamiko Kujiraoka
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Patent number: 10133552Abstract: A data storage method includes storing a plurality of pieces of 2-bit wide ternary data in one word, each of the plurality of pieces of 2-bit wide ternary data indicating +1 when a first bit indicates a first value, indicating ?1 when a second bit indicates the first value, and indicating 0 when both the first bit and the second bit indicate a second value.Type: GrantFiled: July 11, 2015Date of Patent: November 20, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Shunsuke Okumura
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Patent number: 9703531Abstract: A method is provided for multiplying a first operand comprising at least two X-bit portions and a second operand comprising at least one Y-bit portion. At least two partial products are generated, each partial product comprising a product of a selected X-bit portion of the first operand and a selected Y-bit portion of the second operand. Each partial product is converted to a redundant representation in dependence on significance indicating information indicative of a significance of the partial product. In the redundant representation, the partial product is represented using a number of N-bit portions, and in a group of at least two adjacent N-bit portions, a number of overlap bits of a lower N-bit portion of the group have a same significance as some least significant bits of at least one upper N-bit portion of the group. The partial products are added while represented in the redundant representation.Type: GrantFiled: November 12, 2015Date of Patent: July 11, 2017Assignee: ARM LimitedInventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds
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Patent number: 9632752Abstract: The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction.Type: GrantFiled: December 20, 2012Date of Patent: April 25, 2017Assignees: IMEC, Katholieke Universiteit Leuven, KU LEUVEN R&D, Samsung Electronics Co., Ltd.Inventors: Robert Fasthuber, Praveen Raghavan, Francky Catthoor
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Patent number: 9551726Abstract: A device for the interferometric measuring of an object, including a source to generate a source beam, a beam splitting device to split the source beam into a measuring beam and a reference beam, an optic interference device and a first detector, which cooperate such that the measuring beam reflected by the object at least partially is at least partially interfered as the receiver beam and the reference beam on a detector area of the first detector. The beam splitting device splits the source beam into a measuring beam, a first partial reference beam, and at least one second partial reference beam. There is at least one second detector embodied such that the first receiver beam is interfered with the first partial reference beam on a detection area of the first detector and the second partial receiver beam with a second partial reference beam on a detection area of the second detector, each with the formation of an optic interference.Type: GrantFiled: July 1, 2013Date of Patent: January 24, 2017Assignee: Polytec GmbHInventors: Matthias Schussler, Christian Rembe, Alexander Drabenstedt, Sebastian Boedecker, Thian-Hua Xu
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Patent number: 9397725Abstract: According to an embodiment, a reception circuit receives a reception signal according to a signal transmitted from a transmission electrode through a reception electrode capacitively coupled to the transmission electrode. The reception circuit includes an adder, a hysteresis circuit, a shift register and a feedback signal generator. The adder is configured to add one or more feedback signals to the reception signal. The hysteresis circuit has hysteresis in input and output characteristics, and is configured to output output data according to an output signal of the adder. The shift register is configured to sequentially shift the output data of the hysteresis circuit. The feedback signal generator is configured to generate the feedback signal according to each output data of the shift register.Type: GrantFiled: September 10, 2014Date of Patent: July 19, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Shinsuke Fujii
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Patent number: 9164732Abstract: A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.Type: GrantFiled: December 23, 2013Date of Patent: October 20, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ki Lee, Sun-Soo Shin, Jonghoon Shin, Kyoung Moon Ahn, Ji-Su Kang, Kee Moon Chun
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Patent number: 8732225Abstract: Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use (e.g., in multiple instances of the DSP block circuitry on the IC) for implementing finite-impulse-response (“FIR”) digital filters in systolic form. Each DSP block may include (1) first and second multiplier circuitry and (2) adder circuitry for adding (a) outputs of the multipliers and (b) signals chained in from a first other instance of the DSP block circuitry. Systolic delay circuitry is provided for either the outputs of the first multiplier (upstream from the adder) or at least one of the sets of inputs to the first multiplier. Additional systolic delay circuitry is provided for outputs of the adder, which are chained out to a second other instance of the DSP block circuitry.Type: GrantFiled: October 11, 2013Date of Patent: May 20, 2014Assignee: Altera CorporationInventors: Suleyman Demirsoy, Hyun Yi
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Patent number: 8713081Abstract: A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.Type: GrantFiled: April 18, 2013Date of Patent: April 29, 2014Assignee: Altera CorporationInventor: Martin Langhammer
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Patent number: 8589466Abstract: Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.Type: GrantFiled: February 15, 2011Date of Patent: November 19, 2013Assignee: Ternarylogic LLCInventor: Peter Lablans
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Patent number: 8543630Abstract: In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.Type: GrantFiled: April 1, 2013Date of Patent: September 24, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Yonemura, Hirofumi Muratani, Atsushi Shimbo, Kenji Ohkuma, Taichi Isogai, Yuichi Komano, Kenichiro Furuta, Yoshikazu Hanatani
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Patent number: 8513975Abstract: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.Type: GrantFiled: July 5, 2012Date of Patent: August 20, 2013Inventor: Benjamin J. Cooper
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Patent number: 8447798Abstract: A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.Type: GrantFiled: March 25, 2010Date of Patent: May 21, 2013Assignee: Altera CorporationInventor: Martin Langhammer
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Patent number: 8438205Abstract: In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.Type: GrantFiled: February 26, 2009Date of Patent: May 7, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Yonemura, Hirofumi Muratani, Atsushi Shimbo, Kenji Ohkuma, Taichi Isogai, Yuichi Komano, Kenichiro Furuta, Yoshikazu Hanatani
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Patent number: 8417761Abstract: The digital propagate, digit generate, sum+0, and sum+1 terms used in typical carry-propagate adders are generated directly off the multiplicand. During the direct generation, the logic takes into account that each digit will be tripled and if each digit's next less significant digit is greater than 4. Using this technique, the generation of the multiplicand is significantly faster and uses less circuitry.Type: GrantFiled: December 8, 2008Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Mark Alan Erle, Brian John Hickmann
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Patent number: 8341203Abstract: The present invention provides a digital engineering method of hybrid numeral carry system and carry line, in which K common Q-ary numerals that participate in the computation of addition and subtraction are transformed into K or 2K numerals of hybrid numeral carry system, then said K or 2K numerals are added for the sum in the hybrid numeral carry system, whereby the operating speed of all kinds of digital engineering can be improved significantly and the error rate of written calculation engineering can be reduced greatly. The present invention also provides a computer technical solution of hybrid numeral carry system and carry line.Type: GrantFiled: November 3, 2005Date of Patent: December 25, 2012Inventors: Zhizhong Li, Juyuan Xu
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Patent number: 8266199Abstract: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.Type: GrantFiled: June 5, 2006Date of Patent: September 11, 2012Assignee: Altera CorporationInventors: Martin Langhammer, Kwan Yee Martin Lee, Orang Azgomi, Keone Streicher, Yi-Wen Lin
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Patent number: 8209370Abstract: Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.Type: GrantFiled: May 27, 2009Date of Patent: June 26, 2012Assignee: Ternarylogic LLCInventor: Peter Lablans
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Patent number: 8050648Abstract: Digital mixers which permit mixing of asynchronous signals may be constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), an RSFQ D flip-flop, an RSFQ XOR circuit, and an RSFQ T flip-flop. A binary tree arrangement of T flip-flops can be used to provide in-phase and quadrature phase-divided replicas of a reference signal. The mixing elements can be either an XOR circuit, a dual port NDRO circuit functioning as a multiplexer or an RS type NDRO functioning as an AND gate. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.Type: GrantFiled: March 16, 2010Date of Patent: November 1, 2011Assignee: Hypres, Inc.Inventors: Alexander F. Kirichenko, Deepnarayan Gupta, Saad Sarwana
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Patent number: 7711761Abstract: A system, such as, e.g., a multiplier, for processing digital signals by using digital signals in the Canonic Signed Digit representation, the system including an input element to make the digital signals available in the Binary Canonic Signed Digit representation, a converter to convert the digital signals into Canonic Signed Digit representation for use in processing. The input element may be a memory where the signals are stored in the Binary Canonic Signed Digit representation. Alternatively, the input element is adapted to be fed with digital signals in the two's complement representation, and includes at least one converter to convert the digital signals from the two's complement representation into the Binary Canonic Signed Digit representation. This preferably occurs via the T2I transformation, which leads to generating signals in the Canonic Signed Digit representation, which are then converted to the Binary Canonic Signed Digit representation.Type: GrantFiled: July 11, 2005Date of Patent: May 4, 2010Assignee: STMicroelectronics S.r.l.Inventors: Daniele Lo Iacono, Marco Ronchi
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Patent number: 7562106Abstract: Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.Type: GrantFiled: December 20, 2004Date of Patent: July 14, 2009Assignee: Ternarylogic LLCInventor: Peter Lablans
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Patent number: 7543008Abstract: An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recoded output values directly to partial product generators of a multiplier unit is also disclosed.Type: GrantFiled: April 27, 2005Date of Patent: June 2, 2009Assignee: Advanced Micro Devices, Inc.Inventors: David W. Matula, Willard S. Briggs
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Publication number: 20090030962Abstract: An (N+1) number of physical systems each having five energy levels |0>, |1>, |2>, |3>, and |4>, a qubit being expressed by |0> and |1>, are provided in an optical cavity having a cavity mode resonant with |2>-|3>, such that an N number of control systems and a target system are prepared. The target system is irradiated with light pulses resonant with |0>-|4>, |1>-|4>, and |2>-|4> to change a superposed state |c> to |2>. All of the physical systems are irradiated with light pulses resonant with |0>-|3> and |1>-|3>, and a phase of the light pulse resonant with the target system is shifted by a specific value dependent on a unitary transformation U. The target system is irradiated with light pulses resonant with |0>-|4>, |1>-|4>, and |2>-|4>, with a phase difference between them being set to a specific value dependent on the unitary transformation U, to return |2> to |c>.Type: ApplicationFiled: September 23, 2008Publication date: January 29, 2009Inventors: Hayato Goto, Kouichi Ichimura
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Patent number: 7461107Abstract: A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.Type: GrantFiled: March 22, 2007Date of Patent: December 2, 2008Assignee: LSI CorporationInventor: Mikhail I. Grinchuk
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Patent number: 7433905Abstract: A table establishes correspondence between first sets of at least one number, expressed in accordance with a signed code where each number may have the value of 0, 1 or ?1, and second sets of at least one number, expressed according to a simple form where each number may have the value 0 or 1. An input sequence of numbers is decomposed into sets of numbers present in the correspondence table. For each set of numbers derived from the decomposition, a corresponding set of numbers is given by the correspondence table. A sequence of numbers is compiled from the sets retrieved from the table. The invention is in particular useful in various algorithms, such as in cryptography, for example to store values in signed binary mode, in compact non-adjacent form with only the numbers 0, 1 and/or for rapidly producing random numbers in the non-adjacent form.Type: GrantFiled: February 5, 2002Date of Patent: October 7, 2008Assignee: GemplusInventor: Marc Joye
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Publication number: 20080147769Abstract: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.Type: ApplicationFiled: September 10, 2007Publication date: June 19, 2008Inventor: Benjamin J. Cooper
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Patent number: 7296048Abstract: There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1–3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.Type: GrantFiled: August 15, 2003Date of Patent: November 13, 2007Assignees: Kabushiki Kaisha Ultraclean Technology Research Institute, I & F, Inc.Inventors: Tadahiro Ohmi, Makoto Imai, Toshiyuki Nozawa, Masanori Fujibayashi, Koji Kotani, Tadashi Shibata, Takahisa Nitta
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Patent number: 7257609Abstract: The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is enabled to use only one adder in connection with the multiplication which contributes to a reduced hardware amount and reduced required area for the hardware. A shifter means based on binary weighted shifting is used for shifting in connection with the multiplication, thereby reducing the required hardware amount (number of multiplexers and hardwired shifting elements) and thus reducing the area for hardware implementation still further. The present invention can be used in applications using digital multiplication, such as in digital signal processing DSP, digital filters and/or finite impulse response filters FIR filters as well as programmable and/or adaptive digital filters.Type: GrantFiled: October 16, 2000Date of Patent: August 14, 2007Assignee: Nokia CorporationInventors: Marko Kosunen, Kari Halonen
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Publication number: 20070185952Abstract: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.Type: ApplicationFiled: June 5, 2006Publication date: August 9, 2007Applicant: Altera CorporationInventors: Martin Langhammer, Kwan Yee Martin Lee, Orang Azgomi, Keone Streicher, Yi-Wen Lin
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Publication number: 20070185951Abstract: A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.Type: ApplicationFiled: June 5, 2006Publication date: August 9, 2007Applicant: Altera CorporationInventors: Kwan Yee Martin Lee, Martin Langhammer, Yi-Wen Lin, Triet M. Nguyen
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Patent number: 7213043Abstract: A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.Type: GrantFiled: January 21, 2003Date of Patent: May 1, 2007Assignee: LSI Logic CorporationInventor: Mikhail I. Grinchuk
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Patent number: 7155474Abstract: A full adder in a semiconductor device, includes a reference current generation unit for generating a reference current, a carry generation unit for generating a threshold current for generating a carry in response to the reference current and for generating the carry by comparing the input current and the threshold current in response to an input current and a sum signal generation unit for outputting a differential sum signal for the input current and the threshold current according to a comparison result of the carry generation unit.Type: GrantFiled: December 31, 2002Date of Patent: December 26, 2006Assignee: Hynix Semiconductor Inc.Inventor: Yong-Sup Lee
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Patent number: 7099851Abstract: One embodiment of the present invention provides a system that solves a global optimization problem specified by a function ƒ and a set of equality constraints q1(x)=0 (i=1, . . . , r), wherein ƒ is a scalar function of a vector x=(x1, x2, x3, . . . xn). During operation, the system receives a representation of the function ƒ and the set of equality constraints and stores the representation in a memory within a computer system. Next, the system and performs an interval global optimization process to compute guaranteed bounds on a globally minimum value of the function ƒ(x) subject to the set of equality constraints. Performing this interval global optimization process involves, applying term consistency to the set of equality constraints over a subbox X, and excluding portions of the subbox X that violate the set of equality constraints.Type: GrantFiled: December 13, 2001Date of Patent: August 29, 2006Assignee: Sun Microsystems, Inc.Inventors: G. William Walster, Eldon R. Hansen
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Patent number: 6970994Abstract: A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.Type: GrantFiled: May 8, 2001Date of Patent: November 29, 2005Assignee: Intel CorporationInventors: Mohammad Abdallah, James Coke, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
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Patent number: 6816877Abstract: A digital multiplication apparatus and method adopting redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k number system, a data converter data-converts the m-bit number Y into m/k digit data D (=Dm/k−1Dm/k−2 . . . Di . . . DiDo). A partial product calculator converts each of the digits Di of the number Y converted by the data converter into a combination of the coefficients of a fundamental multiple, multiplies the combination by the number X, and outputs the product as a redundant binary partial product. A redundant binary adder sums the partial products for all of the digits of the converted number Y. A redundant binary (RB)-normal binary (NB) converter converts the redundant binary sum into a normal binary number and outputs the converted normal binary sum as the product of the two numbers. Therefore, even when the radix extends, the burden upon hardware can be minimized.Type: GrantFiled: April 12, 2001Date of Patent: November 9, 2004Assignee: Chang University of Science and Technology FoundationInventors: Hong-june Park, Sang-hoon Lee
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Patent number: 6728745Abstract: There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.Type: GrantFiled: September 6, 2000Date of Patent: April 27, 2004Assignees: Kabushiki Kaisha Ultraclean Technology Research Institute, I & F, Inc.Inventors: Tadahiro Ohmi, Makoto Imai, Toshiyuki Nozawa, Masanori Fujibayashi, Koji Kotani, Tadashi Shibata, Takahisa Nitta
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Patent number: 6671710Abstract: Non-binary methods of computing utilizing a digital multistate phase change material. Addition, subtraction, multiplication, and division are accomplished with the controlled application of energy to a phase change material. In one embodiment, energy in an amount insufficient to set the reset state of a phase change material is provided to store one or more numbers and further energy characteristic of the performance of a mathematical operation is provided to effect a computation. The set energy of the reset state of a phase change material provides an interval of energy that may be used to define programming states along the high resistance portion of the electrical resistance response curve of a phase change material. By sub-dividing this interval of energy, a plurality of programming states can be defined which are distinguishable in energy relative to the reset state.Type: GrantFiled: May 10, 2002Date of Patent: December 30, 2003Assignee: Energy Conversion Devices, Inc.Inventors: Stanford R. Ovshinsky, Alastair K. Livesey
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Patent number: 6567835Abstract: The present invention is a 5:2 carry-save-adder (CSA) that receives the five input signals I0, I1, I2, I3 and I4 and computes the two output signals SUM and CARRY. The 5:2 CSA comprises a first level of logic circuitry and a second level of logic circuitry. The first level of logic circuitry comprises a plurality of adders and receives the input signals and generates three intermediate terms T0, T1, and T2. The second level of logic circuitry comprises a carry logic circuit and a sum adder, and uses the intermediate terms to compute the two output signals SUM and CARRY. The 5:2 CSA of the present invention operates using either binary signals or N-NARY signals.Type: GrantFiled: September 17, 1999Date of Patent: May 20, 2003Assignee: Intrinsity, Inc.Inventors: James S. Blomgren, Jeffrey S. Brooks
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Patent number: 6557021Abstract: A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One embodiment of the present invention includes four logic levels, implemented in N-NARY logic. In the first three logic levels, propagation information is gathered for preselected bit groups from the coarse and medium shift output of the normalizer as those results become available. In the fourth level, an incremented, normalized intermediate single-precision or double-precision mantissa result is produced by combining fine shift output bit values with propagation information for the appropriate top bit group, middle bit group, and bottom bit group. The appropriate bit groups are determined by examining the value of the fine shift select signal.Type: GrantFiled: March 17, 2000Date of Patent: April 29, 2003Assignee: Intrinsity, Inc.Inventors: Jeffrey S. Brooks, James S. Blomgren
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Patent number: 6546410Abstract: Adder circuitry is provided based on a reduced mathematical method to provide high-speed hexadecimal addition. A first adder adds the least significant binary digits of two hexadecimal numbers to provide a Digit1 and a Dot1, and a second adder adds the second least significant binary digits to provide a Digit2 plus a Dot1 as a Sum2 and a CarryA. A secondary adder adds the Dot1 and the Sum2 to provide the sum of Digit2 plus Dot2 and Dot1 as a SumA. A generator generates a Dot2 of hexadecimal “1” for certain values of the Sum2 and the CarryA, and a detector triggers an output device, which outputs a hexadecimal “0”, to output the Dot2 in response to a certain pattern of hexadcecimal numbers in the Dot1 and the Sum2. Thus, the least signifigant digit of the added hexadecimal numbers is Digit1, the second least significant digit is SumA, and the third least significant digit is the output of the output device.Type: GrantFiled: January 10, 2000Date of Patent: April 8, 2003Assignee: Advanced Micro Devices, Inc.Inventor: Weng Fook Lee
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Publication number: 20020174157Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. Results of the subtraction operation are compared to zero in redundant form and without requiring carry propagation.Type: ApplicationFiled: December 22, 2000Publication date: November 21, 2002Inventors: Bharat Bhushan, Edward Grochowski, Vinod Sharma, John Crawford
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Publication number: 20020103840Abstract: A digital multiplication apparatus and method adopting a redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k number system, a data converter data-converts the m-bit number Y into m/k-digit data D(=Dm,k−1Dm/k−2 . . . Di . . . DiD0). A partial product calculator converts each of the digits Di of the number Y converted by the data converter into a combination of the coefficients of a fundamental multiple, multiplies the combination by the number X, and outputs the product as a redundant binary partial product. A redundant binary adder sums the partial products for all of the digits of the converted number Y. A redundant binary (RB)-normal binary (NB) converter converts the redundant binary sum into a normal binary number and outputs the converted normal binary sum as the product of the two numbers. Therefore, even when the radix extends, the burden upon hardware can be minimized.Type: ApplicationFiled: April 12, 2001Publication date: August 1, 2002Inventors: Hong-June Park, Sang-Hoon Lee
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Patent number: 6360241Abstract: The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.Type: GrantFiled: April 20, 1999Date of Patent: March 19, 2002Assignee: Compaq Information Technologies Goup, L.P.Inventors: Mark D. Matson, Robert J. Dupcak, Jonathan D. Krause, Sridhar Samudrala
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Patent number: 6347327Abstract: The present invention is an incrementor that receives as inputs a 32-dit 1-of-4 operand and a 1-of-2 increment control signal. For each dit of the operand, the present invention determines whether the increment control signal, which is treated as a carry into the least significant dit, propagates into said dit. If so, the value of the dit is incremented. Otherwise, the dit value is output without modification. The present invention also generates a carry out signal if the increment control signal has propagated across all dits.Type: GrantFiled: December 7, 1998Date of Patent: February 12, 2002Assignee: Intrinsity, Inc.Inventors: Anthony M. Petro, James S. Blomgren