Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: In one embodiment, a circuit for matrix decomposition is provided. The circuit includes an input circuit for receiving a first matrix. A permutation circuit is coupled to the input circuit and configured to interchange columns of the first matrix according to a selected permutation to produce a second matrix. A systolic array is coupled to the permutation circuit and configured to perform QR decomposition of the second matrix to produce a third matrix and a fourth matrix. A reverse permutation circuit is coupled to the systolic array and configured to interchange rows of the third matrix according to an inverse of the selected permutation to produce a first factor matrix and interchange rows of the fourth matrix according to the inverse of the selected permutation to produce a second factor matrix.

Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: The technology described provides a technique for synchronization between pipelines in a data processing apparatus. The data processing apparatus comprises a main processor operable to execute a sequence of instructions, the main processor comprising a first pipeline having a first plurality of pipeline stages, and a coprocessor operable to execute coprocessor instructions in said sequence of instructions. The coprocessor comprises a second pipeline having a second plurality of pipeline stages, and each coprocessor instruction is arranged to be routed through both the first pipeline and the second pipeline.

Abstract: A switching device for forwarding network traffic to a desired destination on a network, such as a telephone or computer network. The switching device includes multiple ports and uses a lookup table to determine which port to forward network traffic over. The lookup table includes network addresses that are maintained in ascending or descending order. The switching device includes multiple binary search engines coupled in series including one or more precursor binary search engines and a final stage binary search engine. Together, the binary search engines perform an N iteration binary search. Additionally, a single search engine can perform multiple concurrent searches so that source and destination addresses can be obtained simultaneously and without wasted memory cycles.

Abstract: A method of operation of an arithmetic and logic unit, a storage medium, and an arithmetic and logic unit introducing a technique and concept of converting a serial structure of decisions having an order dependency to an indeterminate code binary tree which can be processed in parallel so as to simplify the configuration and enable higher speed operation processing.Where a serial structure of decisions having an order dependency is converted to a binary tree structure using decision nodes not having dependency input/outputs as leaves and higher priority determination nodes as the nodes other than the leaves, the decision nodes having dependency input/outputs are replaced by decision nodes not having dependency input/outputs provided with connotation decision nodes and indeterminate code generation nodes.