Abstract: A decoder for decoding low-density parity-check codes includes a first calculator that calculates ??rRml, for each parity check equation, at iteration i?1. A second calculator calculates ??rQ?m, for each parity check equation, at iteration i. ??rQ?m represents information from bit node I to equation node m, one for each connection. ??rRml represents information from equation node m to bit node I, one for each connection. The first calculator is responsive to the second calculator.

Abstract: A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2?64) is provided. To enable testing of the mathematical program, instructions in the mathematical program are trapped. Errors are injected through the use of any status/control flag where an error can be created and be rectified later by a reversible operation so that the result of the mathematical operation is not modified by the injected error.

Abstract: In one embodiment, a checksum generator comprises an N-bit accumulator and a plurality of N-bit 3:2 carry save adders. A first plurality of the plurality of N-bit 3:2 carry save adders are coupled to receive N-bit inputs extracted from an input to the checksum generator, and one of the first plurality has an N-bit input coupled to the output of the accumulator. A second plurality of the plurality of N-bit 3:2 carry save adders have inputs coupled to outputs of the first plurality, and a most significant bit of each carry output of the first plurality is inserted as a least significant bit of the carry output at the input to the second plurality.

Abstract: A computer system including: at least one host computer, a storage system for storing data used in the host computer, and a managing computer for managing storing the data in the storage system which are connected to each other with a network. The managing computer monitors the journal volume which is a storing destinations of the journal, in a case that the journal is stored in the journal volume in parallel, when it is detected that the storing destination of the journal changes from one of the groups into which the journal is just stored to another group, transmits an instruction to the storage system to change the storing destination of the journal to another group.

Abstract: A method for generating a series of output signals represented by a series of measurement signals which is particularly useful in the compensation for jatter, missing spurious pulses or plates when applied to the processing of signals from a speed probe monitoring the speed of a rotating bladed shaft. The method includes the steps of predicting a value for a first measurement signal from a historical measurement signal value, generating a first output signal from the predicted value of the first measurement signal; comparing the measurement signal to its predicted value, and: if the measurement signal is within a predetermined range of acceptable values, using the first measurement signal to predict a value for a second measurement signal; if the measurement signal is outside the pre-determined range of acceptable values, using the first predicted value to predict a second measurement signal, and generating a second output signal from the predicted value of the second measurement signal.

Abstract: Methods and apparatus, including computer program products, for modelling a non-linear transfer function with a power law function. A transfer function is received. Iteratively, until a termination flag is set, a first power law function is received, an auxiliary function is generated from the transfer function and local differences between the transfer function and the first power law function, a second power law function is fitted to the auxiliary function, a modelling error is calculated from the second power law function and the transfer function, and the termination flag is set when the modelling error is less than a predetermined value.

Abstract: A method and apparatus for enhancing performance of parity check in computer readable media is provided. For example, in a RAID (N+1) configuration, a virtual data strip is added for a calculation of parity. Data of the virtual data strip is set so that a predetermined portion of a data area in the virtual data strip has a predetermined value. Consequently, performance of parity check performed in a data processing system having a RAID configuration can be enhanced.

Abstract: Certain exemplary embodiments provide a method comprising a plurality of activities, comprising: automatically: receiving a signal; and via a plurality of iterations, determining, for the received signal, a provable near-optimal B-term representation formed from a linear combination of a plurality of elements selected from a predetermined redundant ?-coherent dictionary, said determined near-optimal B-term representation corresponding to an error that is a minimum of a set of errors corresponding to all possible B-term representations associated with the predetermined redundant ?-coherent dictionary.

Abstract: An error-correcting method used in decoding data transmission is disclosed. The error-correcting method is used for analyzing an error receiving data received from a receiving terminal and comprises: providing a first calculating formula for manipulation of the receiving data to generate the first sum; providing a second calculating formula for manipulation of the receiving data to generate the second sum; identifying the error position of the receiving data according to the result of dividing the second sum by the first sum.

Abstract: Provided are an operation circuit for a modified Euclidean algorithm in a high-speed Reed-Solomon (RS) decoder and a method of implementing the modified Euclidean algorithm. Since a finite state machine (FSM) for generating a stop signal and an FSM for generating a control signal that controls a swap operation, a shift operation, and a polynomial operation for each basic cell of the modified Euclidean algorithm are used, an area-efficient RS decoder can be realized without using a conventional degree computation unit for comparing and calculating degrees.

Abstract: A saturation-capable arithmetic logic unit (ALU) includes a general-purpose comparator coupled to receive a data value and a saturation threshold value during a saturation operation. Using the general-purpose comparator of the ALU for saturation minimizes circuit area without adversely affecting microprocessor performance. In an unsigned saturation operation, the data value is replaced with the threshold value when the data value is greater than the threshold value. In a signed saturation operation, positive data values are compared with an upper threshold value and negative data values are compared with a lower threshold value. In this manner, the data value need only be compared to either the upper or lower threshold value, rather than both. If the data value falls outside the bounds set by the upper and lower threshold values, the data value is replaced with the nearest threshold value.

Abstract: A decoder for decoding low-density parity-check codes comprises a first calculator to calculate LLrRml, for each parity check equation, at iteration i?1. A detector detects LLrRml, at iteration i, in response to the first calculator. A second calculator calculates LLrQLm, for each parity check equation, at iteration i in response to the detector. LLrQLm represents information from bit node l to equation node m, one for each connection. LLrRml represents information from equation node m to bit node l, one for each connection. The first calculator is responsive to the second calculator.

Abstract: The invention relates to a method and system for calculating CRC. Firstly, a Partial CRC is calculated directly according to a segment of a message. Then, a First Code comprising the Partial CRC appended with a plurality of zero-bytes is generated. Finally, the Adjusted CRC is calculated according to the First Code. Therefore, the method and system of the invention can derive an Adjusted CRC directly from each segment of a message. After all segments of a message are received, all the derived Adjusted CRCs are merged to obtain a Final CRC of the message. The method and system of the invention can be quickly prototyped and implemented to various systems due to its simplicity.

Abstract: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

Abstract: This disclosure concerns a waveform corrector comprising a first portion calculating an offset value of an intermediate value between a maximum value and a minimum value of a signal with respect to a reference value; a second portion calculating an actual amplitude of the signal by subtracting the offset value from the maximum value or the minimum value; a third portion generating a first correction signal by subtracting the offset value from the digital signal; a fourth portion subtracting a value obtained by shifting a figure of the actual amplitude from the actual amplitude so that the actual amplitude converges into a reference amplitude; and a fifth portion subtracting a value obtained by shifting the first correction signal by an amount identical to a shift amount of the actual amplitude from the first correction signal so that the first correction signal converges into a second correction signal.

Abstract: Embodiments of the invention are directed to circuits and techniques for computer processor register integrity checking employing digital roots, and hexadecimal digital roots (HDRs) in particular, to validate the results of arithmetic operations and register moves. These circuits thus provide extra confidence that register operations were correctly executed. A hexadecimal digital root is computed for the result of each register computation and compared to the results of the same computation performed on the HDRs of the operands. The hexadecimal digital root approach may be simply implemented with standard combinatoric logic. Validation is accomplished in a single clock cycle so that there is no added system delay or latency. The circuits and methods described herein have comparatively little impact on processor real estate.

Abstract: An apparatus determines a communication protocol for transmitting data, adds a calculation result of checksum calculation to the data and transmits the result with the data, and stores the calculation result in a memory according to a communication protocol determination.

Abstract: A turbo decoding apparatus comprises: a backward-probability calculation unit that executes backward-probability calculation from time N to time 0 with respect to coded data having an information length N which is encoded with turbo-encoding; a storage unit to store backward-probability calculation results extracted from a plurality of continuous backward-probability calculation results regarding a predetermined section of at intervals of n-time; a forward-probability calculation unit that executes forward-probability calculation from time 0 to time N with respect to the coded data; and a decoded result calculation unit that calculates a decoded result of the coded data through joint-probability calculation using forward-probability calculation results by the forward-probability calculation unit and the backward-probability calculation results stored in the storage unit and backward-probability calculation results obtained through recalculation by the backward-probability calculation unit.

Abstract: A storage system for storing data on a storage medium includes an encoder, a linear block encoder, a write circuit, a read circuit, a channel decoder, and a soft linear block code decoder. In a first iteration, the channel decoder decodes data read by the read circuit. In succeeding iterations, the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block decoder from an immediately preceding iteration. The storage system includes a threshold check circuit to select (i) an output of the soft linear block code decoder if the number of parity-check violations has a first relationship with respect to a threshold, or (ii) an output of the channel decoder if the number of violations has a second relationship with respect to the threshold. The storage system includes a decoder to decode an output of the threshold check circuit.

Abstract: In a graphing calculator, a decimal calculation unit obtains a calculation result of an arithmetic expression input by an input device to an n-th digit and an (n+m)-th digit. When the values from the most significant digit to an (n+1)-th digit in the (n+m)-digit calculation result are zero, with respect to an addition or subtraction, the CPU corrects an n-digit calculation result of the addition or subtraction to zero.

Abstract: A wireless receiver which is used for a digital signal transmission system to wirelessly transmit a digital signal by packetizing and modifying it, selectively sets the shortest arithmetical bit length satisfying a required communication quality when performs demodulation arithmetical processing to demodulate a digital signal to be packet-transmitted, inputs a demodulation arithmetical result by the arithmetical bit length to calculate an error vector magnitude value that is a measure indicating a difference between the arithmetical result and a known ideal result, predicts a bit error rate by using the EVM value as an evaluation criterion, selects an arithmetical bit length by which the bit error rate becomes optimum, and executes the demodulating arithmetical processing by the selected arithmetical bit length.

Abstract: A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.

Abstract: A method and system for generating numerical test cases for testing binary floating-point arithmetic units for addition and subtraction operations, in order to verify the proper operation of the units according to a specified standard. The space for eligible test-cases is compatible with masks which stipulate the allowable forms of the operands and the result, including constant as well as variable digits in both the exponent and significand fields. The test-cases, which are generated randomly, cover the entire solution space without excluding any eligible solutions. All standard rounding modes are supported, and if a valid solution does not exist for a given set of masks, this fact is reported. The method is general and can be applied to any standard, such as the IEEE floating-point standard, in any precision.

Abstract: A vehicle electronic controller for checking a control microcomputer with a common monitoring IC, which is used in different vehicles. The vehicle electronic controller includes a control microcomputer, which calculates control data to control an actuator installed in a vehicle in accordance with a driving condition of the vehicle, and a monitoring IC, which is connected to the control microcomputer and checks whether or not the control data is normal based on a determination value. The control microcomputer provides the determination value to the monitoring IC. The monitoring IC includes a memory device, which stores the determination value in a rewritable manner. The monitoring IC receives the determination value and stores the determination value in the memory device.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) coded message. The coded message is modulated according to a high order modulation scheme that has a signal constellation representing more than two symbols per signaling point—e.g., 8-PSK (Phase Shift Keying) and 16-QAM (Quadrature Amplitude Modulation). The system includes a transmitter configured to propagate the modulated signal over the satellite. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates.

Abstract: Discrete Fourier transformation is applied to an analog system so that a signal be transfering, the analog data can be corrected before being quantized and after being transferred and received. In the DFT cyclic decoder and the method of the same, a cyclic property of DFT code is used to induce a decoding way in the receiving end of a communication system. This way is used to design a basic decoding circuit and a fast decoding circuit structure. Since the decoding process is quick and the structure is simple so that the analog error correcting code is used widely.

Abstract: An object is to provide a time-series prediction method and apparatus utilizing wavelet coefficient series which can accurately predict a prediction value of an original time series. When a time-series prediction utilizing wavelet coefficient series is performed, a time series is wavelet-transformed by use of a wavelet transformation unit in order to decompose the time series into a plurality of time series which are band-restricted in the frequency domain, predicted values of frequency components obtained as a result of decomposition are predicted by use of corresponding prediction units, and the prediction values of the respective frequency components are reconstructed by use of an inverse wavelet transformation unit to thereby obtain a prediction value of the original time series.

Abstract: A control arithmetic device includes a subtracting section, disturbance application detecting section, error correction amount calculating section, error correction amount convergence calculating section, and control arithmetic section. The subtracting section calculates the error of a controlled variable on the basis of a controlled variable and set point for a controlled system. The disturbance application detecting section detects, in control cycles, on the basis of the error output whether a disturbance is applied. The error correction amount calculating section calculates an error correction amount on the basis of the magnitude of the error when application of a disturbance is detected. The error correction amount convergence calculating section performs a convergence operation. A control arithmetic method is also presented.

Abstract: The present invention relates generally to error-correction coding and, more particularly, to a decoder for concatenated codes, e.g., turbo codes. The present invention provides a decoder for decoding encoded data, the decoder comprising: a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculates probability estimates for said symbols in a next iterative state; normalising means which normalises said next states estimates; a switch that receives both said normalised and said unnormalised next state estimates, the output of the switch being coupled to the input of the processor; wherein the switch is arranged to switch between the normalised and unnormalised next state estimates depending on the iterative state.

Abstract: A method of decrypting a cipher polynomial (e) using a private key (f) comprises:

Abstract: A method and apparatus for characterizing frequency response of a device under test (DUT) is disclosed. A repeated base bit pattern is received, the base bit pattern including a first transition from a 0-bit to a 1-bit. Then, using bit error rate distribution, multivalue voltage along the first transition is determined. Finally, the multivalued voltages are converted into frequency domain using fast Fourier transform. The apparatus includes a processor and storage with instructions for the processor to perform these operations. Using the present inventive technique, the frequency response of the DUT can be determined using an error performance analyzer such as a BERT.

Abstract: Methods and apparatuses for performing arithmetic encoding and/or decoding are disclosed. In one embodiment, the method for creating a state machine for probability estimation comprises assigning probabilities to states of a look up table (LUT), including setting a probability for each state i of the states equal to the highest probability of the LPS multiplied by the adaptation rate to the power i, where i is a number for a given state and the adaptation rate is smaller than 1. The method also comprises generating state transitions for states in the LUT to be transitioned to upon observing an MPS and an LPS, wherein the next state to which the state machine transitions from a current state when an MPS is observed is a next state higher than the current state if the current state is not the highest state and is the current state if the current state is the highest state.

Abstract: A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.

Abstract: A decoding method is provided which is capable of achieving decoding of error correcting codes in a simple configuration and in a short time. In the method of decoding error correcting codes to perform iterative decoding which consists of forward processing, backward processing, and extrinsic information value calculating processing, a second path metric value in a window boundary obtained at time of performing iterative decoding last time is used as an initial value of the second path metric value in a window boundary to be obtained at time of performing iterative decoding this time in the backward processing.

Abstract: An error correction algebraic decoder and an associated method correct a combination of a B-byte burst of errors and t-byte random errors in a failed sector, by iteratively adding and removing an erasure (N−B) times until the entire failed sector has been scanned, provided the following inequality is satisfied: (B+2t)≦(R−1), where N denotes the number of bytes, B denotes the length of the burst of errors, t denotes the total number of random errors, and R denotes the number of check bytes in the failed sector. This results in a corrected sector at a decoding latency that is a generally linear function of the number of the check bytes R, as follows: Decoding Latency=5R(N−B).

Abstract: An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver can include a Doppler correction circuit, which permits correlation data with frequency shift in the code to be non-coherently integrated among relatively fewer addresses or tap positions in memory. One receiver includes a Doppler offset generator that can advantageously offset a time index used to address a tap position in a non-coherent memory to compensate for code drift in a code with a frequency offset. The amount of offset is computed by accumulating clock cycles of a clock signal that is related to the frequency offset computed by the DFT or FFT frequency bin. The offset aligns a correlation peak in the received code such that the correlation peak can be accumulated in relatively fewer tap positions or addresses.

Abstract: A method and apparatus for use with a computer system are disclosed. A packet is received that includes a header. The header indicates at least one characteristic that is associated with a layer of a protocol stack. The packet is parsed in hardware to extract the characteristic(s), and the packet is processed based on the parsing. Hardware may construct subsequent headers and update fields of the transport, network and data link layers.

Abstract: An operation method has processing for applying a same type of operation in parallel to N M-bit operands to obtain N M-bit operation results executed on a computer. Here, N is an integer equal to or greater than 2 and M is an integer equal to or greater than 1. The operation method includes: an operation step of applying the type of operation to an N*M-bit provisional operand that is formed by concatenating the N M-bit operands, to obtain one N*M-bit provisional operation result, and generating correction information based on an effect had, by applying the operation, on each M bits of the provisional operation result from a bit that neighbors the M bits; and a correction step of correcting the provisional operation result in M-bit units with use of the correction information, to obtain the N M-bit operation results.

Abstract: A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first saturation select control is asserted in response to an unsigned saturated instruction, and a second saturation select control is asserted in response to a signed saturated instruction. If either select control is asserted, each logic block outputs a corresponding bit of a respective saturation value. In response to a modulo mode instruction, both select control signals are negated, and each logic block outputs a corresponding bit of the arithmetic operation (sum or difference) implemented by the instruction.

Abstract: An apparatus for saturation detection and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an output from an adder receiving a pair of input operands, and a plurality of saturation value signals. Each input operand may include a plurality of subvector operands of a preselected data type, each data type has having a corresponding length. The selection circuitry selects the data value signal in response to a plurality of second signals. The second signals are generated from carry-out signals from the subvector operands, and first signals that are generated using instruction information for the executing instruction. The second signals may be generated by logically combining the first signals with carry propagate, carry generate and carry-out signals from carry lookahead logic receiving the subvector operands as input.

Abstract: In a computer system, a method and system for verifying whether a floating-point logic unit correctly directly rounds floating-point numbers when conducting multiplication, square root, and division operations. A bit sequence that represents a directed boundary condition for a mathematical operation is identified. This sequence is then recast in terms of a series of integer equations. A recurrence is used to solve these equations to produce difficult test data. When solving the equations, any intermediate terms that exceed the computer's precision are discarded. The logic then conducts the mathematical operation under inspection using the test cases. The logic's computed value is then compared to an expected value. If the computed value equals the expected value, the logic has accurately performed the operation. If not, the logic is faulty.

Abstract: The present invention comprises methods and apparatus for determining the rate at which data was encoded when such data is received at a receiver. According to the present invention, the rate is determined by computing, for a plurality of possible rates, a final test statistic based on a plurality of measures. The final test statistics are compared and based upon certain selection criteria (for example, without limiting the foregoing, which final test statistic corresponds the highest value), the rate is selected. In the preferred embodiment, the measures comprise statistics based on the cyclical redundancy check, Viterbi metrics, re-encoded symbol error rate, and distance to next largest Viterbi metric.

Abstract: A microcomputer is provided with an upper clip circuit for comparing digital values output from an AD converting circuit 1 with a high level reference value A, and replacing a digital value larger than the reference value A with the reference value A; and a lower clip circuit for comparing digital values output from the upper clip circuit with a reference value B, and replacing a digital value smaller than the reference value B with the reference value B. Irregular signal waveforms can be removed by replacing with the reference values A, B, thereby enhancing the reliability of operation results.

Abstract: An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface, a buffer memory, a core processor for performing digital signal processing which includes a reduced instruction set computer (RISC) processor and four signal processing units. The four signal processing units execute the digital signal processing algorithms in parallel including the execution of the saturated multiplication and accumulation operation. The ASSP is utilized in telecommunication interface devices such as a gateway. The ASSP is well suited to handling voice and data compression/decompression in telecommunication systems where a packetized network is used to transceive packetized data and voice.

Abstract: Objects of the present invention are to realize that a plurality of mathematical expressions are inputted and displayed within the same screen in textbook book format, and that a plurality of mathematical expressions are inputted and displayed in textbook book format and one line format. A plurality of mathematical expressions which are inputted in textbook book format or one line format by use of a keyboard are stored into an expression storing buffer on a data storing RAM memory. The plurality of stored mathematical expressions are developed on a main buffer and a sub buffer of a display forming buffer on the data storing RAM memory, and an image which is produced by synthesizing the display data of the two display forming buffers is formed in VRAM on the data storing RAM memory by using CG data on a program ROM, and displayed on a liquid crystal display via a liquid crystal driver.

Abstract: A method to detect a normalized data field of all zeros or all ones includes receiving a control field and a data field, dividing the data field into segments, and performing detections on each segment. Each segment undergoes all zeros detection, all ones detection, modified zeros detection, and modified ones detection. The modified zeros detection and modified ones detection are both done based on the control field. Each detection for each segment generates a response. Then, a pair of the four responses, or a clear responses signal, is selected for each of the segments based on the control field. From the selected responses, the method determines if the normalized data field is all zeros or all ones.

Abstract: A method and an apparatus for controlling calculation error produced by the accumulation error due to digit truncation in a non-integer computation. The error is eliminated by controlling the values of LSB, C.sub.in and the addition/subtraction selecting signal as, so that C.sub.in is not necessarily equal to C.sub.in. Considering a even number of cascaded pipelines, C.sub.in in the odd pipelines is set as 0, wherein C.sub.in in the even pipelines is set as 1. The resultant error is thus eliminated mutually by odd and even pipelines.

Abstract: A method and apparatus for processing network packets is disclosed. A Single Instruction Multiple Data (SIMD) architecture processor is disclosed. The SIMD processor includes several instructions designed specifically for the task of network packet processing. For example, SIMD add instructions for performing one's complement additions are included to quickly calculate Internet checksums. Furthermore, the SIMD processor includes several instructions for performing lane arithmetic.