Abstract: The present invention discloses a multimedia data processing method that uses a multiplication operation unit, an exclusive-or operation unit, a bit right shift operation unit, a bit left shift operation unit and a comparison operation unit to compute a square root for an integer in a binary form, such that more computations can be processed in a shorter time, and lower the cost for a programmable digital calculator and digital circuits which comes with a central processing unit of a computer system, and thus allowing the algorithm of the present invention to be used extensively.

Abstract: A fast batch verification method and apparatus are provided. In the method of batch-verifying a plurality of exponentiations, (a) a predetermined bit value t is set to an integer equal to or greater than 1; (b) a maximum Hamming weight k is set to an integer equal to or greater than 0 and less than or equal than the predetermined bit value t; (c) n verification exponents si are randomly selected from a set of verification exponents S (n is an integer greater than 1, i is an integer such that 1?i?n), where the set of verification exponents S include elements whose bit values are less than or equal to the predetermined bit value t and to which a Hamming weight less than or equal to the maximum Hamming weight k is allocated; (d) a value of verification result is computed by a predetermined verification formula; and (e) the verification of the signatures is determined to be passed when the value of verification result satisfies a pre-determined pass condition.

Abstract: Provided is a square root calculation apparatus. The apparatus includes a section judgment unit, a coefficient storing unit, and an adder. The section judgment unit stores information regarding a plurality of sections obtained by dividing an entire range of an input value into predetermined intervals, and judges one of the sections to which the input value belongs when the input value is input. The coefficient storing unit stores, in advance, first-order term coefficients and constant terms of first-order approximate equations obtained by approximating square root curves for respective sections, multiplies a first-order term coefficient of the first-order approximate equation in the section to which the input value belongs, by the input value to output a first-order term, and outputs a constant term in the section to which the input value belongs. The adder adds the first-order term and the constant term output from the coefficient storing unit to calculate an approximated square root value.

Abstract: The invention provides circuitry for carrying out a square root operation. The circuitry utilizes iteration circuitry for carrying out a plurality of iterations. The iteration circuitry includes a circuit for calculating a root multiple, the root multiple being a multiple of a current quotient value. The root multiple is used by the iteration circuitry to modify a current remainder.

Abstract: A method of demodulating a square root for processing digital signals is disclosed. The demodulation includes the following steps. First, define |l arg e| to be the larger one between the absolute value of two input values I and Q and define |small| to be the smaller one between the absolute value of the two input values I and Q. Next, define a first determining form by the inequalities 16|small?16|l arg e|?18|small| and 16|l arg e|=16|small|. In addition, define a second determining form by the inequalities 16|small|?16|l arg e|?18|small| and 16|l arg e|?|small|. When the relation between |l arg e| and |small| conforms to the first determining form, the approximate root-mean-square value of the two input values I and Q is |l arg e|+2?5|l arg e|. When the relation between |l arg e| and |small| conforms to the second determining form, the approximate root-mean-square value of the two input values I and Q is |l arg e|+2?6|l arg e|.

Abstract: Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using iterative steps. In addition, the methods taught herein utilize compressed tables for the coefficient terms A, B, and C from the quadratic expression Ax2+Bx+C, thus minimizing hardware requirements.

Abstract: A method and arrangements for increased precision in the computation of a reciprocal square root is disclosed. In accordance with the present invention, it is possible to achieve fifty three (53) bits of precision in less processing time than previously possible.

Abstract: A reciprocal square root for a radix of x is calculated when S[j] represents the partial result obtained after j iterations of calculation, W[j], a residual, and P[j], the product of an operand X and the S[j]. Firstly, appropriate values are set to the initial values S[0], W[0], and P[0]. Secondly, n iterations of calculations from j=0 to n?1 are performed. One calculation includes selecting a reciprocal square root digit qj+1 from the digit set {?a, . . . , ?1, 0, 1, . . . , a}, and calculating a recurrence equation of the S[j], i.e., S[j+1]:=S[j]+qj+1r?j?1, a recurrence equation of the W[j], i.e., W[j+1]:=rW[j]?(2P[j]+Xqj+1r?j?1)qj+1, and a recurrence equation of the P[j], i.e., P[j+1]:=P[j]+Xqj+1r?j?1.

Abstract: Generally, a method and apparatus are provided for computing a matrix inverse square root of a given positive-definite Hermitian matrix, K. The disclosed technique for computing an inverse square root of a matrix may be implemented, for example, by the noise whitener of a MIMO receiver. Conventional noise whitening algorithms whiten a non-white vector, X, by applying a matrix, Q, to X, such that the resulting vector, Y, equal to Q·X, is a white vector. Thus, the noise whitening algorithms attempt to identify a matrix, Q, that when multiplied by the non-white vector, will convert the vector to a white vector. The disclosed iterative algorithm determines the matrix, Q, given the covariance matrix, K. The disclosed matrix inverse square root determination process initially establishes an initial matrix, Q0, by multiplying an identity matrix by a scalar value and then continues to iterate and compute another value of the matrix, Qn+1, until a convergence threshold is satisfied.

Abstract: A dividing circuit and square root extracting circuit using the Newton-Raphson method. The number of places of an initial value of the Newton-Raphson method is decreased, and a part of a multiplier is omitted. Therefore the circuit scale is reduced. A circuit dedicated for the iterated computation circuit for the Newton-Raphson method is mounted, enabling the whole circuits to operate as a pipeline circuit. By cut-off in expanding an iterative operation to a series operation, use of a table, adoption of approximation mode for deriving an initial value, and adoption of redundant expression for computation, higher speed operation and reduction of circuit scale are possible.

Abstract: Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {?1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial remainder from (i?2)'th iterative operation and by the quotient/root prediction table. The present procedures generate the (i?1)'th correction term, which is to be applied in calculating the i'th partial remainder, simultaneously with the (i?2)'th correction term, and need not to perform an iterative operation to obtain the i'th partial remainder.

Abstract: Circuitry for carrying out an arithmetic operation requiring a plurality of iterations, such as division or square root operations, utilizes N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry includes at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.

Abstract: The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry utilizes common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division operation is to be performed. The iteration circuitry is controlled in accordance with whether a square root or division operation is to be performed.

Abstract: A SQRT calculator capable of calculation with a minimal error is provided. The integer calculation unit selects a largest integer from a set of integers with a square of each of the integers smaller than an input datum. The transformation unit transforms the selected integer from the integer calculation unit by multiplying it by 2 and shifts a decimal point of the resulting number to the right by 1 place, thereby adding a certain number less than 10 to the decimal point shifted number to calculate a transformation value. The calculation unit shifts a decimal point of the number less than 10 to the left by 2 places and multiplies the transformation value by the resulting value, thereby subtracting the multiplied value from the input datum and choosing a largest number less than 10 with the subtracted value being in a desired range as a second decimal number of the square root. Thus, the SQRT calculator is capable of calculation with minimal error and, furthermore, has a minimum size of hardware.

Abstract: One embodiment of the present invention provides a system that performs a carry-save square root operation that calculates an approximation of a square root, Q, of a radicand, R. The system calculates Q by iteratively selecting an operation to perform based on higher-order bits of a remainder, r, and then performs the operation. This operation can include subtracting two times a square root calculated thus far, q, and a coefficient, c, from r, and adding c to q. During this operation, the system maintains r in carry-save form, which eliminates the need for carry propagation while updating r, thereby speeding up the square root operation. Furthermore, the selection logic, which decides what operation to perform next, is simpler than previous square-root implementations, thereby providing a further speedup.

Abstract: A pipelined circuit configured to generate a Taylor's series approximation at least one function, preferably at least one of the reciprocal and the reciprocal square root, of an input value. The circuit is preloaded with or configured to generate a predetermined set of Taylor's series coefficients for each segment of the input value range. Other aspects of the invention are methods for determining preferred parameters for elements of such a circuit, a circuit designed in accordance with such a method, and a system (e.g., a pipelined graphics processor) for and method of pipelined graphics data processing using any embodiment of the circuit. The preferred parameters are determined by minimizing the circuit's size subject to constraints on input and output value format and output accuracy, assuming a specific function to be approximated and a specific degree for the approximation but allowing variation of parameters such as coefficient width and number of input value range segments.

Abstract: A Givens rotation computation technique is provided that makes use of polynomial approximations of an expression that contains a square root function. The polynomial approximation uses polynomial coefficients that are specifically adapted to respective ones of a number of subintervals within the range of possible values of the input variable of the expression. The technique may be used in data communications devices such as those in wireless local area networks. An example is the application of the Givens rotations technique in a decision feedback equalizer.

Abstract: The invention provides circuitry for carrying out at least one of a square root operation and a division operation. The circuitry utilizes a carry slave adder and a carry propagate adder part. The carry save adder and the carry propagate adder part are arranged in parallel.

Abstract: A method and system is disclosed for calculating the square root of a number using a fixed-point microprocessor. The method includes employing a binary search to obtain the integer portion of the square root, and calculating a fraction of the square root utilizing the integer portion. The method further includes summing the fractional portion together with the integer portion to yield the square root. Also disclosed is a calculator apparatus for employing the method.

Abstract: The present invention provides an apparatus and method for performing an operation on an operand or operands in order to generate a result, in which the operation is implemented by iterative execution of a recurrence equation. In each iteration, execution of the recurrence equation causes a predetermined number of bits of the result and a residual to be generated, the residual generated in a previous iteration being used as an input for the current iteration, and in the first iteration the residual comprising the operand.

Abstract: A calculating circuit and a method for generating an output signal representing an output number approximating an N-th root and/or a reciprocal of an input number represented by an input signal are described. The calculating circuit includes a subtractor circuit, an integrator circuit, and a multiplier circuit. The subtractor circuit responsive to a first signal and a feedback signal and configured for generating an error signal representing a difference between the first signal and the feedback signal. The integrator circuit responsive to the error signal and configured for computing the output signal. The multiplier circuit responsive to the output signal and configured for generating a feedback signal.

Abstract: In a method for determining the square root of a long-bit number using a short-bit processor, the long-bit number is assumed to be c×22K+d, where c, d<22k, and its solution is assumed to be (a×2K+b)2. The ‘a’ is determined by using a bisection method to obtain the floor value of the square root of ‘c’. In order to obtained the value of ‘b’, there is derived a successive substitution equation: b[n]=(c?a2)×22k+(d?b[n?1]2)/22(k+1). An initial value is given to ‘b’ to execute the successive substitution equation recursively several times until the equation is convergent.

Abstract: A floating point unit includes a multiplier, an approximation circuit, and a control circuit coupled to the multiplier and the approximation circuit. The approximation circuit is configured to generate an approximation of a difference of the first result from the multiplier and a constant. The control circuit is configured to approximate a function specified by a floating point instruction provided to the floating point unit for execution using an approximation algorithm. The approximation algorithm comprises at least two iterations through the multiplier and optionally the approximation circuit. The control circuit is configured to correct the approximation from the approximation circuit from a first iteration of the approximation algorithm during a second iteration of the approximation algorithm by supplying a correction vector to the multiplier during the second iteration. The multiplier is configured to incorporate the correction vector into the first result during the second iteration.

Abstract: A square root extractor includes only multipliers, summers, delay elements, and a scaler so that the square root of a signal may be produced without complex computations.

Abstract: Method and arrangement for sensing and digitally transmitting analog output measurement variables of a plurality of transformers The invention relates to a method and an arrangement for sensing and digitally transmitting analog output measurement variables of a plurality of transformers to a protective unit or panel unit in which digital measurement variables corresponding to the output measurement variables are transmitted to a data concentrator in which a telegram is formed with the digital measurement variables and a predetermined minimum sampling rate. So that analog output measurement variables of transformers can be acquired, collected and transmitted to protective units or panel units at high speed and in synchronism with one another, the analog output measurement variables are converted into the digital measurement variables (Md) and transmitted with a sampling rate which is higher than the minimum sampling rate by a factor (m).

Abstract: A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i−1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.

Abstract: A calculating circuit and a method for generating an output signal representing an output number approximating an N-th root and/or a reciprocal of an input number represented by an input signal are described. The calculating circuit includes a subtractor circuit, an integrator circuit, and a multiplier circuit. The subtractor circuit responsive to a first signal and a feedback signal and configured for generating an error signal representing a difference between the first signal and the feedback signal. The integrator circuit responsive to the error signal and configured for computing the output signal. The multiplier circuit responsive to the output signal and configured for generating a feedback signal.

Abstract: An apparatus and method for demodulating a square root of the sum of squares of two inputs I and Q in a digital signal processing are provided. The square root {square root over (I2+Q2)} is approximated by an equation aX +bY, wherein coefficients a and b are special binary numbers. Due to the numbers, the square root {square root over (I2+Q2)} can be quickly computed by the operation of shifting and addition. A plurality of possible approximation values for the coefficients a and b are provided, as well as the use of a comparator to select the maximal one among the possible approximation values.

Abstract: The invention relates to a method and digital signal processing equipment for performing a digital signal processing calculation, the method employing a look-up table in which predetermined numerical values, which are inverse values of square roots of numbers, have been stored. In the method, the look-up table is searched for the inverse value of the square root of a desired number. If the value is found in the look-up table, it is retrieved. If the value is not found in the look-up table, the number is scaled such that the inverse value of the square root of the scaled number is found in the look-up table. The found value is then retrieved from the look-up table and descaled to produce the inverse value of the square root of the number. The inverse value of the square root of the number is used to carry out a calculation.

Abstract: The invention provides circuitry for carrying out a square root operation. The circuitry utilizes iteration circuitry for carrying out a plurality of iterations. The iteration circuitry includes a circuit for calculating a root multiple, the root multiple being a multiple of a current quotient value. The root multiple is used by the iteration circuitry to modify a current remainder.

Abstract: The invention provides circuitry for carrying out an arithmetic operation requiring a plurality of iterations. The circuitry utilizes N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry includes at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.

Abstract: This invention is a method and apparatus which provide a solution to the problem of constructing efficient and secure digital signature schemes. It presents a signature scheme that can be proven to be existentially unforgeable under a chosen message attack, assuming a variant of the RSA conjecture. This scheme is not based on “signature trees”, but instead it uses a “hash-and-sign” paradigm, while maintaining provable security. The security proof is based on well-defined and reasonable assumptions made on the cryptographic hash function in use. In particular, it does not model this function as a random oracle. The signature scheme which is described in this invention is efficient. Further, it is “stateless”, in the sense that the signer does not need to keep any state, other than the secret key, for the purpose of generating signatures.

Abstract: Computer method and apparatus for performing a square root or division operation generating a root or quotient is presented. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

Abstract: The present invention discloses an envelope detection circuit by using a peel cone approximation concept. The envelope detection circuit comprises an absolute value comparision mechanism, a read only memory and a multiplier/adder mechanism. Particularly, the present invention uses a divider to generate an address of the read only memory to obtain less error and less hardware cost.

Abstract: The invention relates to a method and digital signal processing equipment for performing a digital signal processing calculation, the method employing a look-up table in which predetermined numerical values, which are inverse values of square roots of numbers, have been stored. In the method, the look-up table is searched for the inverse value of the square root of a desired number. If the value is found in the look-up table, it is retrieved. If the value is not found in the look-up table, the number is scaled such that the inverse value of the square root of the scaled number is found in the look-up table. The found value is then retrieved from the look-up table and descaled to produce the inverse value of the square root of the number. The inverse value of the square root of the number is used to carry out a calculation.

Abstract: An approximate value calculating unit is provided for a storage apparatus in which a seek control is performed by speed controlling a head. When a square root arithmetic operation is needed in the calculation of a seek speed target value which is used in the seek control, the approximate value calculating unit divides a range of an input value x serving as a target of the square root arithmetic operation into a plurality of intervals, sets a polynomial of degree N to approximately output a square root {square root over ( )}x of the input value x as an approximate function every interval, and calculates the square root approximate value of the input value x by selectively using the approximate function corresponding to the interval to which the input value x belongs.

Abstract: An arithmetic device having a cache for performing arithmetic operations is provided. The cache stores previously performed resultant data and operand for an arithmetic operation and upon receiving a same operand to be operated upon, the corresponding stored resultant data is output, bypassing the arithmetic processing and operation by the processor. The device having the cache is also configured for outputting a partial resultant output for a partially matched operand.

Abstract: A square root extractor includes only multipliers, summers, delay elements, and a scaler so that the square root of a signal may be produced without complex computations.

Abstract: A reciprocal square root for a radix of x is calculated when S[j] represents the partial result obtained after j iterations of calculation, W[j], a residual, and P[j], the product of an operand X and the S[j]. Firstly, appropriate values are set to the initial values S[0], W[0], and P[0]. Secondly, n iterations of calculations from j=0 to n−1 are performed. One calculation includes selecting a reciprocal square root digit qj+1 from the digit set {−a, . . . , −1, 0, 1, . . . , a}, and calculating a recurrence equation of the S[j], i.e., S[j+1]:=S[j]+qj+1r−j−1, a recurrence equation of the W[j], i.e., W[j+1]:=rW[j]−(2P[j]+Xqj+1r−j−1) qj+1, and a recurrence equation of the P[j], i.e.

Abstract: In a method for determining the square root of a long-bit number using a short-bit processor, the long-bit number is assumed to be c×22K+d, where c, d<22k, and its solution is assumed to be (a×2K+b)2. The ‘a’ is determined by using a bisection method to obtain the floor value of the square root of ‘c’. In order to obtained the value of ‘b’, there is derived a successive substitution equation: b[n]=(c−a2)×22k+(d−b[n−1]2)/22(k+1). An initial value is given to ‘b’ to execute the successive substitution equation recursively several times until the equation is convergent.

Abstract: The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

Abstract: The number X is a number whose square root is to be computed efficiently. A first register of a processor is set to the number X. A second register of the processor is set to a number L, wherein the number L indicates a number of significant bits of X. The number L is shifted right in the second register by one bit to produce a number N. The number X is shifted right in the first register by N bits to produce a number X1. A third register of the processor is set to 1 and shifted left by N bits to produce the result N1 in the third register. The results N1 and X1 are added and shifted right by one bit to produce an approximation to the square root of X.

Abstract: A method and system is disclosed for calculating the square root of a number using a fixed-point microprocessor. The method includes employing a binary search to obtain the integer portion of the square root, and calculating a fraction of the square root utilizing the integer portion. The method further includes summing the fractional portion together with the integer portion to yield the square root. Also disclosed is a calculator apparatus for employing the method.

Abstract: A method optimizes function evaluations performed by of a VLIW processor through enhanced parallelism by evaluating the function by table approximation using decomposition into a Taylor series.

Abstract: A parallel fixed-point square root and reciprocal square root computation uses the same coefficient tables as the floating point square root and reciprocal square root computation by converting the fixed-point numbers into a floating-point structure with a leading implicit 1. The value of a number X is stored as two fixed-point numbers. In one embodiment, the fixed-point numbers are converted to the special floating-point structure using a leading zero detector and a shifter. Following the square root computation or the reciprocal square root computation, the floating point result is shifted back into the two-entry fixed-point format. The shift count is determined by the number of leaded zeros detected during the conversion from fixed-point to floating-point format.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

Abstract: A multi-function look-up table for determining output values for predetermined ranges of a first mathematical function and a second mathematical function. In one embodiment, the multi-function look-up table is a bipartite look-up table including a first plurality of storage locations and a second plurality of storage locations. The first plurality of storage locations store base values for the first and second mathematical functions. Each base value is an output value (for either the first or second function) corresponding to an input region which includes the look-up table input value. The second plurality of storage locations, on the other hand, store difference values for both the first and second mathematical functions. These difference values are used for linear interpolation in conjunction with a corresponding base value in order to generate a look-up table output value.

Abstract: A method for generating entries for a bipartite look-up table having base and difference table portions. In one embodiment, these entries are usable to form output values for a mathematical function, f(x), in response to receiving corresponding input values within a predetermined input range. The method first comprises partitioning the input range into I intervals, J subintervals/interval, and K sub-subintervals/subinterval. For a given interval M, the method includes generating K difference table entries and J base table entries. Each of the K difference table entries corresponds to a particular group of sub-subintervals within interval M, each of which has the same relative position within their respective subintervals. Each difference table entry is computed by averaging difference values for the sub-subintervals included in a corresponding group N.

Abstract: An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a square root calculation precision. The apparatus includes translation logic and execution logic. The translation logic decodes the square root macro instruction into a plurality of prescribed-precision machine instructions according to the square root calculation precision specified by the plurality of square root instructions. The execution logic, coupled to the translation logic, receives the plurality of prescribed-precision machine instructions and calculates the square root of the operand according to the specified square root calculation precision. At least one of the plurality of square root instructions specifies the square root calculation precision such that less significant bits are calculated in the square root than are provided in the operand.

Abstract: An improved method of estimating the square root, reciprocal square root, and reciprocal of an input value in a computer system. The input value, after being normalized, is used to select a pair of constants from a table. The constants are based on a linear approximation of the function for each interval of the input value, offset to reduce a maximum error value for a given interval. The estimated function is calculated by adding or subtracting the product of a part of the normalized input value and the first constant from the second constant. In one implementation, the input value is normalized within the range 1.ltoreq.x<2, and one lookup table is used, having an interval size of 1/32. In a further preferred embodiment, only a lower order part of the mantissa is used in the multiply-add operation, to reduce the number of bits required (the high order part of the mantissa is used to select the constants from the table). In another implementation, the input value is normalized within the range 0.5.ltoreq.