Abstract: A processing element (PE) of a systolic array can perform neural networks computations on two or more data elements of an input data set using the same weight. Thus, two or more output data elements corresponding to an output data set may be generated. Based on the size of the input data set and an input data type, the systolic array can process a single data element or multiple data elements in parallel.

Abstract: According to the embodiments, a semiconductor device includes: an adder configured to generate positive multiple data of the multiplicand which is used for a plurality of the multiplication in plurality and does not include a value of 2n (n is a positive integer) of the multiplicand; a Wallace tree circuit provided in each of the multiplier circuits and configured to operate a sum of a plurality of partial products by using a plurality of adders; and a selection circuit provided in each of the multiplier circuits and configured to select, according to a plurality of bits selected from the multiplier, data falling in a multiple of one of the multiplicand, data of 2n of the multiplicand, and the positive multiple data from the adder in order to output as one partial product of the plurality of partial products to the Wallace tree circuit.

Abstract: Disclosed herein includes a system, a method, and a device including shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network. The first value has a predetermined format including a first bit, and two or more second bits to represent a value of zero or 2n where n is an integer greater than or equal to 0. The device shifts, when the two or more second bits represent the value of 2n, the second value by (n+1) bits via the shift circuitry to provide a first result, selectively outputs zero or the second value, based on a value of the first bit of the first value, to provide a second result, and adds the first result and the second results via the add circuitry to provide a result of the multiplication of the first and second values.

Abstract: An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.

Abstract: A method is provided that includes providing a hard-wired integer multiplier circuit configured to multiply a first physical operand and a second physical operand, mapping a first logical operand to a first portion of the first physical operand, mapping a second logical operand to a second portion of the first physical operand, and mapping a third logical operand to the second physical operand. The method further includes multiplying the first physical operand and the second physical operand using the hard-wired integer multiplier circuit to provide a multiplication result that includes a first portion including a product of the first logical operand and the third logical operand, and a second portion including a product of the second logical operand and the third logical operand.

Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.

Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.

Abstract: A processor includes a front end including a decoder, an execution unit including a shift-sum multiplier (SSM), and a retirement unit. The decoder includes logic identify a multiplication instruction to multiply a first number and a second number. The execution unit includes logic to, based on the instruction, access a look-up table based on the second number to determine a plurality of shift parameters and one or more flag parameters. The SSM includes logic to use the shift parameters to shift the first number to determine a plurality of partial products, and the flag parameters to determine signs of the partial products. The SSM also includes logic to sum the partial products to yield a result of the multiplication instruction.

Abstract: Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value.

Abstract: A shared parallel adder tree for executing multiple different population count operations on a single datum includes a number of carry-save adders (CSAs) and/or half adders (HAs), arranged in rows, where certain CSAs and HAs are dedicated to a single population count operation, while other CSAs and HAs are shared among two or more population count operations. The datum is applied to the first row in the tree. Partial sums of the number of ones at various locations within the tree are routed to certain CSAs and/or HAs “down” the tree to propagate the particular population count operations. Carry-propagate adders generate at least a portion of the final sum of the number of ones in certain population count operations. An “AND” operation on a particular number of the bits in the datum provides the high order bit of the resulting sum of the particular population count operation.

Abstract: Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and an addend and a relation between a minuend and a subtrahend, respectively, thereby preventing borrowing and carrying from being propagated in modules having basic digits.

Abstract: A multiplier and a method multiply, using an array of adders, two binary numbers X and Y defining a matrix [Eni=xn?i·yi], wherein the initial matrix [Eni=xn?i·yi] is transformed into a matrix [Eni=(xn?i?yi)·(yi?1?yi)=(xn?i?yi)·Yi] with Yi=yi?1?yi or [Eni=eni·Yi] with eni=xn?i?yi. A first approximation Un0 and Rn?1i?1 is formed of the sum and carry of the first two rows y0 and y1 of this matrix, and this is used as an input for the following estimation step which is repeated for all the following rows, successively carrying out the addition of the following yi+1 rows up to the last non-zero row, according to a first given series of propagation equations, and then the propagation of the carries Rni?1 is carried out over the zero yi+1 rows according to a second given series of propagation equations, in order to obtain the final result of the product P.

Abstract: A macrocell including an adder block with a plurality of bit-slice adders, a bypass path and a control unit adapted to receive a carry of a first neighboring macrocell, and to output a carry by generation within the adder block or by passage of the carry of the first neighboring macrocell through the bypass path to a second neighboring macrocell. The control unit is adapted to signal a validity of the carry output of the macrocell depending on a logical combination of states of the two carry output lines. The control unit is further adapted, depending on a validity signal of the first neighboring macrocell indicating a validity of the carry, to prevent forwarding the carry.

Abstract: Digital mixers which permit mixing of asynchronous signals are constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), an RSFQ D flip-flop, an RSFQ XOR circuit, and an RSFQ T flip-flop. A binary tree arrangement of T flip-flops can be used to provide in-phase and quadrature phase-divided replicas of a reference signal. The mixing elements can be either an XOR circuit, a dual port NDRO circuit functioning as a multiplexer or an RS type NDRO functioning as an AND gate. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.

Abstract: A multiplier and a method multiply, using an array of adders, two binary numbers X and Y defining a matrix [Eni=xn?i·yi], wherein the initial matrix [Eni=xn?i·yi] is transformed into a matrix [Eni=(xn?i?yi)·(yi?1?yi)=(xn?i?y1)·Yi] with Yi=yi?1?yi or [Eni=eni·Yi] with eni=xn?i?yi. A first approximation Un0 and Rn?1i?1 is formed of the sum and carry of the first two rows y0 and y1 of this matrix, and this is used as an input for the following estimation step which is repeated for all the following rows, successively carrying out the addition of the following Yi+1 rows up to the last non-zero row, according to a first given series of propagation equations, and then the propagation of the carries Rni?1 is carried out over the zero Yi+1 rows according to a second given series of propagation equations, in order to obtain the final result of the product P.

Abstract: An adder circuit for multiplying two long integers deploys a network of adders for summing a succession of words of the long integers to generate intermediate results. The number of addends varies as a function of bit position and the network of adders is designed to reduce the number of levels of adders in the network according to a maximum number of expected addends. A number of strategically placed extra adders may be positioned in the network to further reduce the number of levels. An output stage may be provided that adds sum and carry outputs of the network and retains a most significant bit for use with a subsequent calculation output of the network. The network may be configured so that a subsequent calculation by the network can commence before the previous calculation has been completed, the output of the previous calculation being fed back to the network at an intermediate level and its lowest (output) level.

Abstract: A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bit 0 position.

Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

Abstract: An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does not require extra circuits or routing overhead. Power dissipation is reduced by ordering the sequence of partial-product additions such that an increasing sequence of “transition probabilities” is encountered.

Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

Abstract: The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

Abstract: A stream cipher cryptosystem includes a pseudo-random bit generator receiving a key and providing a vulnerable keystream vulnerable to crytanalysis, and a non-linear filter cryptographic isolator to convert the vulnerable keystream into a protected keystream. The non-linear filter cryptographic isolator includes a multiplier for performing a multiplication function on the vulnerable keystream to provide a lower partial product array and an upper partial product array, and a simple unbiased operation (SUO) for combining the lower partial product array and the upper partial product array to provide the protected keystream. In example encryption operations, a plaintext binary data sequence is combined with the protected keystream to provide a ciphertext binary data sequence. In example decryption operations, a ciphertext binary data sequence is combined with the protected keystream to provide a plaintext binary data sequence.

Abstract: An apparatus and method for compressing a reduction array into an accumulated carry-save sum. The reduction array includes a partial product matrix, a carry-save sum, and a constant value row. A compressor array generates a previous accumulated carry-save sum. A three-input/two-output carry-save adder pre-reduces the constant value row and the previously accumulated carry-save sum into a two-row intermediate carry-save sum that is added to the partial product matrix to form a current accumulated carry-save sum.

Abstract: A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.

Abstract: A method is described for providing an improved multiplier/accumulator which utilizes less processing resources than such devices which are known in the prior art. The methodology operates to utilize the processing resources of a multiplier-accumulator combination on a cooperative basis, with the result that at least one adder stage in such a combination can be eliminated. The method includes the processing by the accumulator of certain terms that would otherwise be processed by the multiplier.

Abstract: In a case of performing a multiplication operation with low accuracy, a value of the most significant bit included in the least significant half the bits of a multiplier is replaced with “0”. A Booth decoder divides the multiplier into a plurality of partial bit rows. A plurality of partial product generating circuits, each of which is arranged corresponding to corresponding one of the partial bit rows divided by the Booth decoder, each generates a partial product of a multiplicand and each corresponding one of the partial bit rows. In the case of performing the multiplication operation with low accuracy, the partial product generating circuits generating the partial products corresponding to the partial bit row of the least significant half the bits, generate partial products of each corresponding bit row and the least significant half the bits of the multiplicand, and generate partial products of each corresponding bit row and the most significant half the bits of the multiplicand.

Abstract: An integrated multiplier circuit includes an array of one-bit adders, organized into a plurality of stages with a plurality of bit positions in each stage. Each one-bit adder has a carry input terminal and a pair of addend input terminals, and receives a carry signal and two addend signals. The carry signal is normally generated in the preceding bit position in the preceding stage of the array, and is received at the carry input terminal, but if the carry signal arrives with less delay than one of the two addend input signals, it is input at the corresponding addend input terminal, and the more delayed addend input signal is input at the carry input terminal. This input arrangement reduces the total time needed to complete a multiplication operation.

Abstract: An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does not require extra circuits or routing overhead. Power dissipation is reduced by ordering the sequence of partial-product additions such that an increasing sequence of “transition probabilities” is encountered.

Abstract: Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby.

Abstract: A specialized Sum-of-Absolute-Difference (SAD) calculator for motion estimation uses inversion rather than 2's complementing. The absolute-value operation of each pixel-pair difference is performed by a bit-wise inversion rather than a complement. This reduces delay since the adder/incrementer propagation is eliminated. The increment needed to adjust for inversion rather than 2's complementing is accomplished by using the carry inputs to the summing and final adders that generate the sum of the absolute differences. When 2-input final adders are used for summing, a total of k−1 adders are used to sum k absolute differences. One additional increment is needed since only k−1 adders are available. A reduced half-adder rather than a full adder is inserted between the summing and final adder for this remaining increment. Propagation of carries between bit positions in a full adder can be avoided using the half adder.

Abstract: A method and system is provided which overlaps the process of partial product reduction and the final adder in both higher- and lower-order bits when performing multiplication. The method and system reduces the number of left-over bits such that the final addition on these bits requires fewer logic stages to complete its process thereby reducing the propagation delay.

Abstract: A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplier. This input circuitry includes a plurality of Booth recoding logic cells that provide the control signals to multiplexers in the adder cells in the array. The Booth recoding logic cells receive different subsets of bits of the second number and generate the Booth recoded control signals as a function of the received subset of bits. Each Booth recoding logic cell includes balanced logic circuitry for generating all of the Booth recoded control signals from that Booth recoding logic cell at the same time. The balanced logic circuitry minimizes temporary short-circuit paths in the multiplexers in the adder cells. The input circuitry also includes a split bus that provides the first number to the array.

Abstract: A multiplying device operates for implementing multiplication between multiplicand data and multiplier data in a two's complement representation form. Each of the multiplicand data and the multiplier data has n bits, where n denotes a predetermined even number. A 1-bit sign extension of the multiplicand data is executed to generate data having n+1 bits. In the multiplying device, n/2 partial product data pieces are generated on the basis of the data having n+1 bits and the multiplier data according to second-order Booth's algorithm. Each of the n/2 partial product data pieces has n+1 bits. There is a plurality of adders connected and arranged in a tree configuration. The adders operate for adding the n/2 partial product data pieces. The adders include a final-stage adder which outputs multiplication result data representing a product of the multiplicand data and the multiplier data. The multiplication result data has 2n−1 bits.

Abstract: A multiplication array is divided into divided Wallace tree arrays each performing multiplication by addition in a tree-like form. An addition result is transmitted from the divided Wallace tree arrays to a final addition circuit. Thus, an interconnection line length of a critical path of a multiplication apparatus can be reduced.

Abstract: An adder tree includes several partial product generators, each generating a bit of equal weight. An adder receives the bits and provides a carry bit to a logic unit. The logic unit propagates the carry bit to the next more significant column in response to a carry enable instruction. The logic unit outputs a bit that is independent of the carry bit in response to a lack of a carry enable instruction.

Abstract: A multiplier circuit has an encoder and a partial product bit generating circuit. The encoder receives a multiplier bit signal and is used to output a plurality of encode signals. The partial product bit generating circuit receives the encode signals along with a multiplicand bit signal from each digit place and is used to generate a partial product bit for each digit place. The partial product bit generating circuit has a first selection circuit which is used to select a logically true signal from among the encode signals in accordance with a value of the multiplicand bit signal. Therefore, the circuit can be reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.

Abstract: A multiplier contains an array of partial product generators, at least one new modified-Booth encoder. Corresponding to each new modified-Booth encoder, the partial product generator array includes a new adder cell. The partial product generator array receives inputs Y0 . . . YN with the Y0 receiving partial product generator being a new partial product generator for generating a partial product PP*(0,j). The new modified-Booth encoder receives multiplier bits and a multiplicand input Y0, and generates control signals and a carry in signal. The new adder cell is connected to the new modified-Booth encoder, the Y0 receiving new partial product generator and the (j−2) row Y2 receiving partial product generator and generates a partial product and an intermediate carry out signal so as to reduce the number of gate delay stages in the critical path of the multiplier.

Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

Abstract: A multiplier architecture in accordance with the present invention provides increased operating speed, and yet maintains regularity in its structure in order to achieve a small floor plan when reduced to silicon. A Hekstra-type multiplier is modified by replacing full adders circuits with compressor circuits in a manner that preserves the balance of the signal propagation delays. The result is an architecture having a regular layout that greatly facilitates its implementation in silicon.

Abstract: A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplier. This input circuitry includes a plurality of Booth recoding logic cells that provide the control signals to multiplexers in the adder cells in the array. The Booth recoding logic cells receive different subsets of bits of the second number and generate the Booth recoded control signals as a function of the received subset of bits. Each Booth recoding logic cell includes balanced logic circuitry for generating all of the Booth recoded control signals from that Booth recoding logic cell at the same time. The balanced logic circuitry minimizes temporary short-circuit paths in the multiplexers in the adder cells. The input circuitry also includes a split bus that provides the first number to the array.

Abstract: A number of adder structures (also referred to herein as "tiles" and "Quickadders.TM.") are provided which may be constructed with positively and/or negatively weighted and signed inputs and outputs and which may be placed so as to span one or more bitslices of a multiplier array. In a second aspect of the present invention, groups of replicable circuitry columns are provided for forming multiplier arrays for multiplying binary numbers X and Y to obtain a binary product Z. These groups of columns of circuitry include left column groups to handle X-inputs to the array, internal column groups, and right column groups to handle outputs to a CLA adder/subtractor (or equivalent) for processing the MSBs of the product. The LSBs of the product are produced directly by the array. The groups may be thought of as replacing 2, 3 or 4 conventional columns of full-adder circuitry of a basic array such as that shown in FIGS. 1 and 2.

Abstract: A multiplier in a data processing system has a modified compressor structure which is configured to alleviate both a tendency of the multiplier to be wire bound and to optimize a circuit area required to implement the multiplier. In the modified compressor structure, all inputs to the compressor are not of the same weight, all outputs of the compressor are not of the same weight, and carry values generated during the compression process are no longer all shifted in a same direction. Instead, in the compressor, a mixture of sum values and carry values generated during a compression process are reduced within the compressor. By modifying the compressor so that it is no longer limited to receiving only inputs having a same weight, there is a reduced input/output signal requirement and, therefore, the compressor has less global interconnect requirements.