Coded Decimal Patents (Class 708/652)
  • Patent number: 10430185
    Abstract: An instruction generates a value for use in processing within a computing environment. The instruction obtains a sign control associated with the instruction, and shifts an input value of the instruction in a specified direction by a selected amount to provide a result. The result is placed in a first designated location in a register, and the sign, which is based on the sign control, is placed in a second designated location of the register. The result and the sign provide a signed value to be used in processing within the computing environment.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: October 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Reid T. Copeland, Silvia Melitta Mueller
  • Patent number: 10235170
    Abstract: An instruction generates a value for use in processing within a computing environment. The instruction obtains a sign control associated with the instruction, and shifts an input value of the instruction in a specified direction by a selected amount to provide a result. The result is placed in a first designated location in a register, and the sign, which is based on the sign control, is placed in a second designated location of the register. The result and the sign provide a signed value to be used in processing within the computing environment.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Reid T. Copeland, Silvia Melitta Mueller
  • Patent number: 8572141
    Abstract: A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Adam B. Collura, Mark A. Erle, Wen H. Li, Eric M. Schwarz
  • Patent number: 7738657
    Abstract: The present disclosure provides a system and method for performing multi-precision division. A method according to one embodiment may include generating a first product by multiplying a modulus having a most significant bit and/or a least significant bit equal to one and a quotient approximation of the modulus. The method may also include generating the 1's complement of the first product, generating a second product by multiplying the 1's complement and the quotient approximation, normalizing and truncating the second product to obtain a quotient, and storing the quotient in memory. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Matt Bace, Gunnar Gaubatz, Gilbert M. Wolrich
  • Patent number: 7567999
    Abstract: A device for calculating a result or an integer multiple of the result of a division of a numerator by a denominator includes a unit for providing a factor which is selected such that a product of the factor and the denominator is greater than the result. The device further includes a unit for modularly reducing a first product of the numerator and the factor using a modulus equaling a sum of a second product of the denominator and the factor and of an integer to obtain an auxiliary quantity having the result. A unit is used to extract the result or the integer multiple of the result from the auxiliary quantity. A division is thus reduced to a modular reduction and an extraction which is uncomplicated as far as calculation is concerned so that, in particular in long-number division tasks, the speed on the one hand and the safety on the other hand are increased.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: July 28, 2009
    Assignee: Infineon Technologies AG
    Inventor: Wieland Fischer
  • Patent number: 6067617
    Abstract: A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode operating in a milli-mode state when macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers and the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode. Millicode flags allow specialized update and branch instructions and flags are either cleared or specifically set for a millicode instruction. A millicode instruction for editing functions processes one byte of an input pattern string, generates one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: May 23, 2000
    Assignee: International Business Machines Corporation
    Inventors: Charles Franklin Webb, Wen He Li