Abstract: There is provided an information processing device to reduce a processing load associated with inner product operations while also guaranteeing the quantization granularity of weight coefficients, the information processing device including: a multiply-accumulate operation circuit configured to execute a multiply-accumulate operation on the basis of multiple input values and multiple weight coefficients that are quantized by an exponential representation and that correspond to each of the input values. Exponents of the quantized weight coefficients are expressed by fractions taking a predetermined divisor as a denominator, and the multiply-accumulate operation circuit performs the multiply-accumulate operation using different addition multipliers on the basis of a remainder determined from the divisor.

Abstract: A method implements fixed-point polynomials in hardware logic. In an embodiment the method comprises distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial and optimizing each operator to satisfy the part of the error bound allocated to that operator. The distribution of errors between operators is updated in an iterative process until a stop condition (such as a maximum number of iterations) is reached.

Abstract: A segment divider, a segment division operation method, and an electronic device are disclosed, relating to the technical field of digital signal processing. The divider includes: a first shift register circuit; a second shift register circuit; a calculation circuit configured to compare data in first registers and data in second registers according to the cascade order, to perform a preset operation and generate an operation result; a third shift register circuit configured to receive and register the operation result bit by bit; then a shift control circuit configured to control the first shift register circuit and the third shift register circuit to perform a shift operation; a counting circuit configured to accumulate the number of shift operations after each shift operation, and send an output signal to finish the operation or send a calculation signal to continue the operation; and an output circuit configured to output a target result.

Abstract: Implementations of this specification provide a method and apparatus for computer data processing for large number operations. An example method performed by a computing device includes splitting a multiplier and a multiplicand into respective four 64-bit numbers from most significant bits to least significant bits; reading the split multipliers and the split multiplicands into a register; and obtaining a multiplication processing result for the multiplier and the multiplicand by performing operations including: classifying the split multipliers and the split multiplicands into groups of data pairs, calculating multiplication results of the groups of data pairs one by one, performing accumulation on multiplication results of data pairs in each group, and storing an accumulation result corresponding to the data pairs in memory as the multiplication processing result for the multiplier and the multiplicand.

Abstract: Provided are a method and apparatus for processing a division operation. The method includes acquiring input data, detecting reference data related to a division operation corresponding to the acquired input data, from a cache memory in which data related to at least one division operation is pre-stored, selecting any one operator from among a plurality of operators identified according to at least one of a processable number of data bits and a calculation type, based on a difference between the detected reference data and the input data, and acquiring a result of performing division operation on the input data from the selected operator.

Abstract: Techniques are disclosed relating to circuitry configured to perform reciprocal-based floating-point division. In some embodiments, floating-point circuitry includes reciprocal circuitry configured to generate a reciprocal of a divisor, multiplication circuitry configured to multiply the reciprocal results with a dividend, and circuitry configured to clear a least significant bit of an integer representation of the multiplication output to generate a modified multiplication output. The floating-point circuitry may be configured to convert the modified multiplication output to a representation using the first precision to generate a division output. In some embodiments, the refinement using the integer representation may provide correctly-rounded subnormal division results. The disclosed techniques may improve accuracy, reduce processing time, and/or reduce instructions needed for floating-point division, with little to no increase in chip area.

Abstract: Control circuitry coupled to a multiply unit which includes a plurality of stage, each of which may be configured to perform a corresponding arithmetic function, may be configured to retrieve a given entry from a lookup table dependent upon a first portion of a binary representation of an input operand. An error value of an error function evaluated dependent upon a lookup value in a given entry of the plurality of entries is included in a predetermined error range. The control circuitry may be further configured to determine an initial approximation of a result of an iterative arithmetic operation using the first entry and initiate the iterative arithmetic operation using the initial approximation and the input operand.

Abstract: The invention introduces a method for executing a computer instruction, which contains at least the following steps: decoding the computer instruction to generate a micro-instruction at least containing an opcode (operation code) and a packed operand, where the packed operand contains all n input parameters corresponding to the computer instruction; generating n addresses of the n input parameters according to the opcode and the packed operand; and reading n approximations corresponding to the n addresses from a lookup table.

Abstract: Provided is a fast divider including an initial parameter setting unit and an arithmetic unit. The arithmetic unit is coupled to the initial parameter setting unit that receives a divisor and a dividend, and sets a plurality of initial parameters of a sequence according to the divisor and the dividend. The plurality of initial parameters includes an initial term, a first term and a common ratio having an absolute value smaller than 1. The arithmetic unit stores a recurrence relation of the sequence and iteratively computes a quotient using the recurrence relation according to the plurality of initial parameters. The recurrence relation indicates that a (k+1)th term is equal to a product of a kth term multiplied by a sum of the common ratio and 1 subtracted by a product of a (k?1)th term multiplied by the common ratio. k is an integer larger than or equal to 1.

Abstract: Systems, apparatuses, and methods for performing a division operation are disclosed. In one embodiment, a processor includes at least one arithmetic logic unit and a register file. In response to detecting a request to perform a division operation between a dividend and a divisor, the processor generates an initial approximation of the reciprocal of the divisor. Then, the processor converts the initial approximation of the reciprocal of the divisor into a fractional fixed point representation. The processor also introduces a small error into the initial approximation of the reciprocal of the divisor. Then, the processor implements one or more Newton-Raphson iterations for refining the approximation of the reciprocal and then multiplies the final reciprocal value by the dividend to generate the quotient.

Abstract: In an embodiment, multi-precision numbers A and B are accessed from a storage device (e.g., a memory array), where A is a dividend and B is a divisor. A multi-precision division operation is iteratively performed on the numbers A and B including: performing a multi-precision subtraction operation on A and B during a first iteration of the multi-precision division operation; performing a multi-precision addition operation on A and B during a second iteration of the multi-precision division operation as a result of a determination that a final borrow occurred during the subtraction operation; and performing a multi-precision addition operation on A and B after a final iteration of the multi-precision division operation.

Abstract: A method of performing digital division includes right-shifting a divider to provide a temporary divider, subtracting the temporary divider from a temporary dividend to provide a difference, determining the temporary dividend based on at least one of a dividend and the difference, and left-shifting a quotient based on the difference. A corresponding computer-readable medium and device are provided. A system to perform digital division includes a counter and a division circuit. The counter provides a count, and the division circuit is operatively coupled to the counter. The division circuit divides a dividend by a divider to provide a quotient in response to the counter. At least one of the counter and division circuit is configured to accept at least one of the count, dividend, divider, and quotient with a configurable bit-width.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: Systems, apparatus and methods are described related to optimizing fixed point divide.

Abstract: A method includes receiving a dividend and a divisor for performing a division operation. Numbers p and n are found, for which the divisor equals 2n(1+2p). An interim result, which is equal to a reciprocal of 1+2p multiplied by the dividend, is calculated. The interim result is divided by 2n to produce a result of the division operation.

Abstract: A method for determining a quotient value from a dividend value and a divisor value in a digital processing circuit is provided. The method includes computing a reciprocal value of the divisor value and multiplying the reciprocal value by the dividend value to obtain a reciprocal product, the reciprocal product having an integer part. The method also includes computing an intermediate remainder value by computing a product of the integer part and the divisor value, and subtracting the resulting product from the dividend value and determining the quotient value based upon the intermediate remainder value.

Abstract: Radix-based division is described. A dividend operand and a divisor operand are obtained. An estimate that is a reciprocal of the divisor operand is obtained. For a prescaling mode, a prescaling iteration is performed which includes: multiplying the divisor operand with the estimate to provide a prescaled divisor; apportioning the dividend operand into portions from most significant to least significant; providing the estimate to iteration blocks ordered from highest to lowest; providing the most significant to the least significant of the portions of the dividend operand respectively to the highest to the lowest of the iteration blocks; respectively multiplying the portions of the dividend operand with the estimate to provide first partial products; and parsing most significant residue portions and least significant residue portions as associated with order of the iteration blocks from the first partial products.

Abstract: A method and apparatus for reducing memory required to store reciprocal approximations as specified in Institute of Electrical and Electronic Engineers (IEEE) standards such as IEEE 754 is presented. Monotonic properties of the reciprocal function are used to bound groups of values. Efficient bit-vectors are used to represent information in groups resulting in a very compact table representation about four times smaller than storing all of the reciprocal approximations in a table.

Abstract: A device for determining an inverse of an initial value related to a modulus, comprising a unit configured to process an iterative algorithm in a plurality of iterations, wherein an iteration includes two modular reductions and has, as an iteration loop result, values obtained by an iteration loop of an extended Euclidean algorithm.

Abstract: An improved method and apparatus for performing floating-point division is disclosed. In a particular embodiment, fractional operands are pre-scaled and an estimate of a reciprocal of the pre-scaled fractional divisor is obtained from a lookup table using a portion of the bits of the pre-scaled fractional divisor. This value is used to scale the fractional operands and a multiply-add operation is used based on principles of series expansion to compute a final result with an acceptable degree of accuracy.

Abstract: Methods and apparatus to determine a remainder value are disclosed. A disclosed example method involves, during a compilation phase, causing a processor to multiply a dividend value by a first value to generate a second value associated with a product. The first value is associated with a scaled approximate reciprocal of a divisor value, and the scaled approximate reciprocal of the divisor value is determined using a compound exponent value. During a runtime phase, the processor is caused to multiply a third value from the second value. The third value is generated using at least a subset bitfield of the second value. During the runtime phase, the processor is caused to determine a remainder value based on the third value. The processor is caused to store the remainder value in a memory.

Abstract: A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.

Abstract: A method for determining a quotient value from a dividend value and a divisor value in a digital processing circuit is provided. The method includes computing a reciprocal value of the divisor value and multiplying the reciprocal value by the dividend value to obtain a reciprocal product, the reciprocal product having an integer part. The method also includes computing an intermediate remainder value by computing a product of the integer part and the divisor value, and subtracting the resulting product from the dividend value and determining the quotient value based upon the intermediate remainder value.

Abstract: One embodiment of the present invention provides a system that performs both error-check and exact-check operations for a Newton-Raphson divide or square-root computation. During operation, the system performs Newton-Raphson iterations followed by a multiply for a divide or a square-root operation to produce a result, which includes one or more additional bits of accuracy beyond a desired accuracy for the result. Next, the system rounds the result to the desired accuracy to produce a rounded result t. The system then analyzes the additional bits of accuracy to determine whether t is correct and whether t is exact.

Abstract: Methods and apparatus to provide rounding of a binary integer are described. In one embodiment, a value that indicates whether a divisor divides a binary integer is extracted from a product of the binary integer and a scaled approximate reciprocal of the divisor.

Abstract: The present disclosure provides a system and method for performing multi-precision division. A method according to one embodiment may include generating a first product by multiplying a modulus having a most significant bit and/or a least significant bit equal to one and a quotient approximation of the modulus. The method may also include generating the 1's complement of the first product, generating a second product by multiplying the 1's complement and the quotient approximation, normalizing and truncating the second product to obtain a quotient, and storing the quotient in memory. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: A computational method for implementation in an electronic digital processing system performs integer division upon very large (multi-word) operands. An approximated reciprocal of the divisor is obtained by extracting the two most significant words of the divisor, adding one to the extracted value and dividing from a power of two out to two significant words. Multiplying this reciprocal value by a remainder (initialized as the dividend) obtains a quotient value, which is then decremented by a random value. The randomized quotient is multiplied by the actual divisor, and decremented from the remainder. The quotient value is accumulated to obtain updated quotient values. This process is repeated over a fixed number of rounds related to the relative sizes in words of the dividend and divisor. Each round corrects approximation and randomization errors from a preceding round.

Abstract: One embodiment of the present invention provides a system that uses the Newton-Raphson technique to perform a division operation. During operation, the system receives a numerator a and a denominator b. The system then divides a by b by first using the Newton-Raphson technique to calculate 1/b, and then multiplying 1/b by a to produce the result a/b. While using Newton-Raphson technique to find 1/b, the system first obtains an initial estimate x0 for 1/b and then iteratively solves the equation xi+1=xi(2?bxi). Each iteration involves: (1) using a multiplier circuit to multiply b by xi to compute bxi; (2) performing a bit-wise complement operation on bxi to compute 2?bxi, whereby an additional pass through an adder circuit or a multiply/add circuit is not required to perform the subtraction operation. (3) The system then uses the multiplier circuit to multiply xi by 2?bxi to compute xi(2?bxi).

Abstract: Methods and apparatus for determining a remainder value are disclosed. The methods and apparatus extract a residuary subset bitfield value from a binary value that is calculated using a scaled approximate reciprocal value that is associated with a compound exponent scaling value. The residuary subset bitfield value is part of a range of contiguous bits that is associated with upper and lower boundary bit-position values that are part of the compound exponent scaling value. The methods and apparatus determine the remainder value based on the residuary subset bitfield value.

Abstract: A dividing circuit and square root extracting circuit using the Newton-Raphson method. The number of places of an initial value of the Newton-Raphson method is decreased, and a part of a multiplier is omitted. Therefore the circuit scale is reduced. A circuit dedicated for the iterated computation circuit for the Newton-Raphson method is mounted, enabling the whole circuits to operate as a pipeline circuit. By cut-off in expanding an iterative operation to a series operation, use of a table, adoption of approximation mode for deriving an initial value, and adoption of redundant expression for computation, higher speed operation and reduction of circuit scale are possible.

Abstract: Methods, machines, and systems are provided for very high radix division using narrow data paths. A numerator and denominator are received for a very high radix division calculation. An approximate reciprocal of the denominator is obtained from a data structure. The numerator and denominator are pre-scaled by the reciprocal. The denominator is decomposed to an equivalent expression that results in a number of leading insignificant values. Next, modifying a current remainder by forming a first product and subtracting the equivalent expression iteratively assembles a quotient.

Abstract: Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.

Abstract: A pipelined circuit configured to generate a Taylor's series approximation at least one function, preferably at least one of the reciprocal and the reciprocal square root, of an input value. The circuit is preloaded with or configured to generate a predetermined set of Taylor's series coefficients for each segment of the input value range. Other aspects of the invention are methods for determining preferred parameters for elements of such a circuit, a circuit designed in accordance with such a method, and a system (e.g., a pipelined graphics processor) for and method of pipelined graphics data processing using any embodiment of the circuit. The preferred parameters are determined by minimizing the circuit's size subject to constraints on input and output value format and output accuracy, assuming a specific function to be approximated and a specific degree for the approximation but allowing variation of parameters such as coefficient width and number of input value range segments.

Abstract: Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.

Abstract: Improved methods of operating a digital data processor to perform binary division include estimating reciprocals of at least selected divisors based on value accessed from a look-up table. For divisors in a first numerical range, the estimation can be based on a value stored in a first look-up table at an index defined by the divisor. For divisors in a second numerical range, the estimation can be based on an index that is a bitwise-shifted function of the divisor. The methods can be applied to scalar and vector binary division.

Abstract: The present invention provides apparatus, methods, and computer program products for non-iterative division and non-iterative reciprocal generation. In one embodiment, the present invention uses a logic network that determines the bits of the quotient of a divisor and dividend by using a non-iterative, (i.e., non trial and error), method. Further, in another embodiment, the present invention may determine the reciprocal of a number M by separating the number M into at least two numbers X, Y . . . Z so that M=X+Y+ . . . +Z. The reciprocal of M is computed according to an equation 1/M=F(X,Y . . . Z) or an approximation 1/M?G(X,Y . . . Z), where the approximation gives the correct value of the inverse of M to a predetermined accuracy. In some embodiments, the apparatus uses an equation that exactly describes the reciprocal or instead, it may include one or more memories for storing look-up tables containing pre-calculated parts of the equation.

Abstract: A method of executing division and an electronic apparatus implementing the method are provided. In the method, an auxiliary divisor is retrieved from a look-up table stored in the electronic apparatus, the auxiliary divisor being a predetermined number generated by the product of the powers of the integer two and the reciprocal of the divisor. In the method, the division is executed in the electronic apparatus by multiplying the dividend of the division by the auxiliary divisor. The result of the division is scaled in the electronic apparatus in order to represent it in the desired form by shifting the result obtained by multiplying.

Abstract: The division and square root systems include a multiplier. The systems also include a multipartite table system, a folding inverter, and a complement inverter, each coupled to the multiplier. The division and square root functions can be performed using three scaling iterations. The system first determines both a first and a second scaling value. The first scaling value is a semi-complement term computed using the folding inverter to invert selected bits of the input. The second scaling value is a table lookup value obtained from the multipartite table system. In the first iteration, the system scales the input by the semi-complement term. In the second iteration, the resulting approximation is scaled by a function of the table lookup value. In the third iteration, the approximation is scaled by a value obtained from a function of the semi-complement term and the table lookup value. After the third iteration, the approximation is available for rounding.

Abstract: A method and apparatus for the calculation of the reciprocal of a normalized mantissa M for a floating-point input number D. A formula for determining the minimum size for the look-up table in accordance with the required precision is provided, as well as formulas for calculating look-up table entries. The look-up table stores the initiation approximations and the correction coefficients, which are addressed by the corresponding number of the mantissa's most significant bits and used to obtain the initial approximation of the reciprocal by means of linear interpolation requiring one subtraction operation and one multiplication operation. The result of the linear interpolation may be fed to a Newton-Raphson iteration device requiring, for each iteration, two multiplication operations and one two's complement operation, thereby doubling the precision of the reciprocal.

Abstract: In a digital processor performing division, quotient accumulation apparatus is formed of a set of muxes and a single carry save adder. Partial quotients are accumulated in carry-save form with proper sign extension. Delay of partial quotient bit fragments from one iteration to a following iteration enables the apparatus to limit use to one carry save adder. By enlarging minimal logic, the quotient accumulation apparatus operates at a rate fast enough to support the rate of fast dividers.

Abstract: A non-inverting domino register including a domino stage, a storage stage, a keeper circuit and an output stage. The domino stage includes evaluation logic, coupled between evaluation devices at a pre-charged node, which evaluates a logic function. The storage stage drives a first preliminary output node and includes a pull-up device and a pull-down device both responsive to the pre-charged node, and a second pull-down device responsive to the clock signal. The keeper circuit is a cross-coupled pair of inverters coupled between the first preliminary output node and a second preliminary output node. The output stage includes a pair of pull-up and pull-down devices for driving an output node. The first pull-up device and the first pull-down device are both responsive to the pre-charged node, and the second pull-up device and the second pull-down device are both responsive to the second preliminary output node.

Abstract: A method and apparatus for performing a floating point division of a dividend (a) by a divisor (b) to produce a correctly rounded-to-nearest quotient (q′) having a mantissa of P bits in a data processing system is disclosed. In one embodiment, the data processing system computes a current quotient estimate (qm′, where m represents an integer and m>=0) that is within 1 ulp of a true quotient (a/b). Then the data processing system computes a current remainder estimate (rm′) based on the dividend (a), the divisor (b) and the current quotient estimate (qm′). The data processing system also computes a current reciprocal estimate (yn′, where n represents an integer and n>=0) based on a reciprocal intermediate value (E) with a relative error with respect to a true reciprocal of the divisor (1/b) of less than or equal to z/(22P) (where z is an integer derived from error analyses of computations of the current reciprocal estimate (yn′)).

Abstract: The invention relates to a method and digital signal processing equipment for performing a digital signal processing calculation, the method employing a look-up table in which predetermined numerical values, which are inverse values of square roots of numbers, have been stored. In the method, the look-up table is searched for the inverse value of the square root of a desired number. If the value is found in the look-up table, it is retrieved. If the value is not found in the look-up table, the number is scaled such that the inverse value of the square root of the scaled number is found in the look-up table. The found value is then retrieved from the look-up table and descaled to produce the inverse value of the square root of the number. The inverse value of the square root of the number is used to carry out a calculation.

Abstract: A multiplier configured to execute division and square root operations by executing iterative multiplication operations is disclosed. The multiplier is configured to complete divide-by-two and zero dividend instructions in fewer clock cycles by detecting them before or during the first iteration and then performing an exponent adjustment and rounding the result to the desired precision. A system and method for rapidly executing divide-by-two and zero dividend instructions within the context of a multiplier that executes division and square root instructions using iterative multiplication are also disclosed.

Abstract: A method and apparatus for the calculation of the reciprocal of a normalized mantissa M for a floating-point input number D. A formula for determining the minimum size for the look-up table in accordance with the required precision is provided, as well as formulas for calculating look-up table entries. The look-up table stores the initiation approximations and the correction coefficients, which are addressed by the corresponding number of the mantissa's most significant bits and used to obtain the initial approximation of the reciprocal by means of linear interpolation requiring one subtraction operation and one multiplication operation. The result of the linear interpolation may be fed to a Newton-Raphson iteration device requiring, for each iteration, two multiplication operations and one two's complement operation, thereby doubling the precision of the reciprocal.

Abstract: A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated reciprocal term from the first memory and a selected reciprocal error term from the second memory to provide the reciprocal. The selected estimated reciprocal term and the selected reciprocal error term correspond to at least a portion of a divisor. The apparatus includes a multiplier for multiplying a dividend by the reciprocal to generate a quotient. The method includes the step of looking up an estimated reciprocal term in a first lookup table stored in a first computer memory wherein the estimated reciprocal term corresponds to at least a portion of a given divisor. A reciprocal error term is looked up in a second lookup table stored in a second computer memory, the error term corresponds to at least a portion of the divisor.

Abstract: A computation unit computes a division operation Y/X by determining the value of a divisor reciprocal 1/X and multiplying the reciprocal by a numerator Y. The reciprocal 1/X value is determined using a quadratic approximation having a form: Ax2+Bx+C, where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficients determines the error in a final result. Storage size is reduced through use of “least mean square error”techniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x2, Ax2, and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.

Abstract: An arithmetic division for implementation using hardware or software is performed by firstly storing the reciprocal of each nth value in a range 0 to X where n is greater than 1 and storing the differences between the reciprocals of the intervening n-1 values. A mantissa and an operand for an arithmetic division are received. one of the stored reciprocals is retrieved in response to the most significant part of the received mantissa and a set of differences is retrieved in response to a least significant part of the received mantissa. The differences and the reciprocal are summed and the result is multiplied by the received operand, other thereby giving the result of the arithmetic division.

Abstract: A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated reciprocal term from the first memory and a selected reciprocal error term from the second memory to provide the reciprocal. The selected estimated reciprocal term and the selected reciprocal error term correspond to at least a portion of a divisor. The apparatus includes a multiplier for multiplying a dividend by the reciprocal to generate a quotient. The method includes the step of looking up an estimated reciprocal term in a first lookup table stored in a first computer memory wherein the estimated reciprocal term corresponds to at least a portion of a given divisor. A reciprocal error term is looked up in a second lookup table stored in a second computer memory, the error term corresponds to at least a portion of the divisor.

Abstract: Division system and method support a hardware division address centrifuge to provide a flexible addressing scheme, and thus facilitates the reorganization and redistribution of data between remote and local memory blocks in a distributed memory massively parallel processing system. A flexible addressing scheme supports data organizations which can vary widely, depending on the processing task. Different data organizations in memory are supported by a PE internal address having certain bits designated as the target PE number and the remaining bits designating the offset within that PE's local memory. The PE and offset bits are distributed throughout the PE internal address to achieve various data distributions throughout memory. When a transfer occurs, the PE number bits and offset bits are separated via the centrifuge under control of a software-supplied mask.