Abstract: An execution unit comprising a processing pipeline configured to perform calculations to evaluate a plurality of mathematical functions. The processing pipeline comprises a plurality of stages through which each calculation for evaluating a mathematical function progresses to an end result. Each of a plurality of processing circuits in the pipeline is configured to perform an operation on input values during at least one stage of the plurality of stages. The plurality of processing circuits include multiplier circuits. A first multiplier circuit and a second multiplier circuit are configured to operate in parallel, such that at the same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform their processing. A third multiplier circuit is arranged in series with the first multiplier circuit and the second multiplier circuit and processes outputs from the first multiplier circuit and the second multiplier circuit.

Abstract: According to one general aspect, an apparatus may include a key selector configured to select a personality key from at least a portion of an input value. The apparatus may include a sparse look-up table configured to determine a portion of a result based upon the personality key and a prior remainder. The apparatus may include an adder configured to compute a current remainder based upon, at least, the input value, and the portion of the result. The apparatus may be configured to iteratively compute current remainders and portions of the result until either the current remainder is zero, or a predefined level of precision is reached.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: One embodiment of the present invention sets forth a technique for performing fast integer division using commonly available arithmetic operations. The technique may be implemented in a four-stage process using a single-precision floating point reciprocal in conjunction with integer addition and multiplication. Furthermore, the technique may be fully pipelined on many conventional processors for overall performance that is comparable to the best available high-performance alternatives.

Abstract: The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0·q?1 q?2 . . . q?n), then the algorithm provides for computing S = AB D to yield a w-bit quotient Q and w-bit remainder R by: (1) determining the next quotient digit q?j using a quotient digit selection function; (2) generating the product q?jD; and (3) performing the triple addition of rRj-1, (?q?jD) and b - ( j - 1 ) ? ( A r ) where R0=b?1Ar?1. The recurrence relation may be implemented with carry-save adders for computation using bitwise logical operators (AND, OR, XOR).

Abstract: The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.

Abstract: A floating-point circuit may include a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor, as well as a divide engine coupled to the normalization circuit. In response to determining that one or more of the input floating-point operands is a denormal number, the operand normalization circuit may be further configured to normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine, and dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ). The divide engine may be configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit.

Abstract: Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {?1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial remainder from (i?2)'th iterative operation and by the quotient/root prediction table. The present procedures generate the (i?1)'th correction term, which is to be applied in calculating the i'th partial remainder, simultaneously with the (i?2)'th correction term, and need not to perform an iterative operation to obtain the i'th partial remainder.

Abstract: A device for calculating a result or an integer multiple of the result of a division of a numerator by a denominator includes a unit for providing a factor which is selected such that a product of the factor and the denominator is greater than the result. The device further includes a unit for modularly reducing a first product of the numerator and the factor using a modulus equaling a sum of a second product of the denominator and the factor and of an integer to obtain an auxiliary quantity having the result. A unit is used to extract the result or the integer multiple of the result from the auxiliary quantity. A division is thus reduced to a modular reduction and an extraction which is uncomplicated as far as calculation is concerned so that, in particular in long-number division tasks, the speed on the one hand and the safety on the other hand are increased.

Abstract: A system for encoding and decoding data words including an anti-analysis encoder unit for receiving an original plaintext and producing a recoded data, a data compression unit for receiving the recoded data and producing a compressed recoded data, and an encryption unit for receiving the compressed recoded data and producing an encrypted data. The recoded data has an increased non-correlatable data redundancy compared with the original plaintext in order to mask the statistical distribution of characters in the plaintext data. The system of the present invention further includes a decryption unit for receiving the encrypted data and producing a decrypted data, a data decompression unit for receiving the decrypted data and producing an uncompressed recoded data, and an anti-analysis decoder unit for receiving the uncompressed recoded data and producing a recovered plaintext that corresponds with the original plaintext.

Abstract: A divider circuit for dividing a dividend by a divisor, includes: a multiplicative divisor generating circuit configured to generate 2m-2 multiplicative divisors that are 2 to 2m-1 times the divisor, the m indicating an integer of 2 or more; and a quotient generating circuit configured to sequentially generate a quotient of the dividend, by m bits in decreasing order of significance, by subtracting from the dividend the divisor and the 2m-2 multiplicative divisors, respectively.

Abstract: A division operation is simulated by performing multiple subtractions, in parallel, each of which represents the subtraction of a different multiple of the divisor from the dividend. Each subtraction produces a possible remainder value, but only one subtraction will result in a valid remainder—the one representing the divisor multiplied by the actual quotient that would result from the division operation—and that remainder is then identified as the modulo output of the division operation.

Abstract: Methods, machines, and systems are provided for very high radix division using narrow data paths. A numerator and denominator are received for a very high radix division calculation. An approximate reciprocal of the denominator is obtained from a data structure. The numerator and denominator are pre-scaled by the reciprocal. The denominator is decomposed to an equivalent expression that results in a number of leading insignificant values. Next, modifying a current remainder by forming a first product and subtracting the equivalent expression iteratively assembles a quotient.

Abstract: The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry utilizes common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division operation is to be performed. The iteration circuitry is controlled in accordance with whether a square root or division operation is to be performed.

Abstract: A method of decimal division in a superscalar processor comprising: obtaining a first operand and a second operand; establishing a dividend and a divisor from the first operand and the second operand; determining a quotient digit and a resulting partial remainder; based on multiple parallel/simultaneous subtractions of at least one of the divisor and a multiple of the divisor from the dividend, utilizing dataflow elements of multiple execution pipes of the superscalar processor.

Abstract: The invention provides circuitry for carrying out at least one of a square root operation and a division operation. The circuitry utilizes a carry slave adder and a carry propagate adder part. The carry save adder and the carry propagate adder part are arranged in parallel.

Abstract: A higher-radix type divider is provided which is capable of obtaining a quotient at a high speed by performing a scaling on a divisor and by representing a partial remainder in a redundant binary notation. The divider for obtaining the quotient by referring to the divisor and dividend normalized respectively so as to satisfy a range of ½K or more and less an ½K+1 (k being a positive integer) and to a length of bits, out of all bits of the partial remainder, defined by a radix for operations and a maximum number of digits, is provided with a scaling factor generating section, a multiplying section, a divisor tripled-number generating section and a repetitive operating section.

Abstract: An SRT division unit for performing a novel SRT division algorithm is presented. The novel SRT division algorithm comprises a method for performing SRT division using a radix r. As one skilled in the art will appreciate, the radix r dictates the number of quotient-bits k generated during a single iteration. The relationship between radix r and the number of quotient-bits k generated in a single iteration is r=2k. The number of iterations needed to determine all quotient-digits is N, such that N=54/k for a 64 bit floating point value. In accordance with one embodiment of the present invention, the SRT division unit generates a scaling factor M, which comprises scaling sub-factors M1 and M2 according to the relationship M=r*M1+M2. Next, the division unit generates a scaled divisor Y by multiplying a divisor DR by scaling factor M, such that said scaled divisor Y=DR*M=r(DR*M1)+DR*M2.

Abstract: A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterative operation type. The pipelined divider has a delay time of 3 cycles in a single precision, and can reduce a chip size by about ⅓ in comparison to the existing pipelined divider.

Abstract: A high radix divider capable of reducing the size of the circuit of a quotient/remainder judgement unit in a radix 2k restoring division divider for finding a quotient k number of bits at a time, comparing multiples B, 2B, and 3B of a divisor B with a remainder R in parallel in two-input comparators and a three-input comparator and performing radix 4 division by finding a quotient 2 bits at a time. At this time, using a three-input comparator 313 in the comparison of 3B=(B+2B)≦R to realize comparison without the addition (B+2B), also, finding a new remainder Re in a three-input adder/subtractor for the simultaneous complex addition/subtraction R−(x+y) by a single ripple carry.

Abstract: A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated reciprocal term from the first memory and a selected reciprocal error term from the second memory to provide the reciprocal. The selected estimated reciprocal term and the selected reciprocal error term correspond to at least a portion of a divisor. The apparatus includes a multiplier for multiplying a dividend by the reciprocal to generate a quotient. The method includes the step of looking up an estimated reciprocal term in a first lookup table stored in a first computer memory wherein the estimated reciprocal term corresponds to at least a portion of a given divisor. A reciprocal error term is looked up in a second lookup table stored in a second computer memory, the error term corresponds to at least a portion of the divisor.

Abstract: The invention provides computer apparatus for performing a division operation having a dividend mathematically divided by a divisor. The dividend and the divisor are split between a state machine and an array of carry save adders. The most significant bits of the dividend and the divisor are input to the state machine and the least significant bits of the dividend and the divisor are input to the carry save adder array. The state machine is fully encoded with partial remainder values and quotient digit values for all possible combinations of the most significant bits of the divisor and the dividend. The carry save adders add the respective least significant bits of the dividend and the divisor and output spillover signals to the state machine. The state machine provides partial remainders and quotient digits selected from the encoded partial remainder values and quotient digit values dependent on (i.e. as a function of) the most significant bits of the dividend, divisor and the spillover signals.

Abstract: In a multiple determination apparatus for determining whether or not a dividend is a multiple of a divisor which is represented by D=.alpha..multidot.2.sup.r where .alpha. is an odd number and r is 0, 1, 2, . . . , a non-zero determination circuit determines whether or not a remainder of a division of the dividend by 2.sup.r is zero. A selector circuit replaces a first number with a quotient of the division. An operational circuit determines whether or not a greatest common measure between .alpha. and the first number coincides with .alpha., when the remainder is zero. Thus, it is determined that the dividend is a multiple of the divisor when the greatest common measure coincides with .alpha..

Abstract: An iterative division and/or iterative square root circuit 20 uses quotient digits q.sub.j+1 within the calculation that are dependent upon the input divisor D or radicand A and current partial remainder or partial radicand P.sub.j for the cycle reached. As the input divisor D or radicand A is fixed throughout the calculation, the critical path through the iterative circuit may be speeded up by preselecting and storing a subset QC of quotient digit values using a primary quotient digit selecting circuit 18, 22 operating in dependence upon the divisor D or radicand A and independently of the partial remainder or partial radicand P.sub.j. Within the iterative circuit 20, the quotient digits q.sub.j+1 to be used for each cycle can then be selected from this subset QC by a secondary quotient digit selecting circuit 24 in dependence upon the partial remainder or partial radicand P.sub.j and independent of the divisor D or radicand A.

Abstract: A multiplier uses squaring units to find the product of two binary numbers A and B by exploiting the algebraic expansion of (A-B).sup.2 or (A+B).sup.2. The squaring units may be look-up memories. However, to multiply extremely large numbers, each squaring unit may itself have look-up memories and additional components. A divider may be formed by using the multiplier to multiply trial quotients by a divisor and by comparing the product with a dividend. The trial quotient is formed by shifting a one through a sequence of bit positions and latching the one at bit positions such that the trial quotient times the divisor does not exceed the dividend.

Abstract: A divider which multiplies both divisor and dividend by a first multiplier generated from the divisor to compute an intermediate divisor and an intermediate quotient, and iterates such computations by the number of times needed, so that the intermediate divisor approaches a predetermined value, and the intermediate quotient approaches the quotient obtained by dividing the dividend by the divisor. This makes it possible to implement a fast divider with a configuration simpler than that of a conventional divider which feeds back the outputs of multipliers many times depending on the accuracy required, which involves delay times in the multiplication and makes the configuration complicated.