Abstract: A bidirectional bus system that includes a bus master having a first transmitter coupled to a bidirectional bus. The first transmitter transmits a signal in a first voltage range onto the bus. The bus master has a first receiver coupled to the bus. A bus slave having a second transmitter coupled to the bus is included. The second transmitter transmits a signal in a second voltage range onto the bus, where the bus slave having a second receiver is coupled to the bus. The first receiver is configured to interpret the signal in the first voltage range to indicate an idle state while the second receiver interprets the signal in the first voltage range as indicating data. The second receiver interprets the signal in the second voltage range as indicative of an idle state while the first receiver interprets the signal in the second voltage range as indicating data.

Abstract: An object is disclosed, the object (100) comprising a body comprising an antenna; and an integrated circuit embedded in the body and electrically connected to the antenna for receiving and transmitting wireless signals. The integrated circuit receives wireless signals at first and second different frequencies, waits until a command is received at the first frequency from a first reader device before transmitting a first signal and, upon detection of a signal at a second frequency different to the first frequency from a second reader device (201), transmits a second signal without waiting until a command is received.

Abstract: Embodiments enable built-in sinusoidal jitter injection, for example, in a serializer/deserializer (SERDES) circuit. For example, embodiments can receive a tracking profile that corresponds to a predetermined sinusoidal jitter (SJ) profile and a predetermined phase interpolator (PI) profile. A shift determination can be made for each of a plurality of insertion times according to the tracking profile, the shift determination indicating whether to adjust phase interpolation of the SERDES circuit. At each of the plurality of insertion times, a phase adjustment signal can be generated as a function of the shift determination. For example, the phase adjustment signal can indicate a control code for a phase interpolator coupled to a clock generator of the SERDES, and the signal can be output to the phase interpolator. Some implementations adjust the phase interpolator in response to the phase adjustment signal, such that the phase interpolator injects SJ that substantially tracks the SJ profile.

Abstract: The present disclosure pertains to a programmable data width converter device, system and method thereof. Programmable data width converter (pDWC) of the present disclosure can include a control Finite State Machine (FSM) that is configured to receive input values of m and n, and control any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) based on the received values of m and n; and a loadable programmable shift register with programmable load location (pSRL) operatively coupled with the control FSM, wherein the pSRL is configured to perform loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM. The pDWC can be configured to programmably convert width of m k-bit word input to n k-bit word output, and wherein 1?m?M and 1?n?N.

Abstract: The disclosure extends to methods, systems, and computer program products for digitally imaging with area limited image sensors, such as within a lumen of an endoscope. The system includes an image sensor comprising a pixel array for sensing electromagnetic radiation. The pixel array comprises a plurality of pixel groups comprising only active pixels, a plurality of pixel groups comprising only optical black pixels, and a plurality of line readouts, wherein each line readout is configured to read out a single group of the plurality of pixel groups in the pixel array. The imaging system samples one or more of the plurality of pixel groups comprising only optical black pixels a plurality of times to reduce a size of the image sensor by reducing a number of optical black columns.

Abstract: A device is connected to a connector of a computing system. In response, the computing system determines whether the device is a management device. In response to determining that the device is the management device, the computing system couples the connector to a management port of a service processor of the computing system. In response to determining that the device is not the management device, the computing system couples the connector to a system port of a primary processor of the computing system.

Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

Abstract: An enumeration technique is provided that includes a master/slave embodiment and a half-duplex embodiment.

Abstract: System, methods and apparatus are described that facilitate a device to encode/decode data in a data communications interface coupled to a plurality of wires. The device determines a value of a sequence of data bits allocated to a frame, converts the value into a sequence of symbols associated with the frame, and transmits the sequence of symbols to a receiver. The device performs the converting by calculating base-N coefficients of a base-N number polynomial for the frame based on the value, where N is greater than 2, calculating base-2 coefficients of a base-2 number polynomial for each symbol according to a respective base-N coefficient corresponding to each symbol, determining changes of states of the plurality of wires for each symbol according to the base-2 coefficients respectively calculated for each symbol, and generating the sequence of symbols based on the changes of states of the plurality of wires for each symbol.

Abstract: A product, according to one embodiment, includes a support portion, the support portion being elongated in a first direction; and an insertion portion extending from the support portion in a second direction orthogonal to the first direction, the insertion portion having dimensions allowing insertion of the insertion portion in a card connector of a circuit board. At least an exterior of the insertion portion is electrically insulating. The support portion is wider than the insertion portion in a third direction orthogonal to each of the first and second directions.

Abstract: A method may include creating a priority order among two or more transport media based on an availability of each transport medium when a request to establish an outbound communication session is received. The method may further include receiving the request to establish an outbound communication session with a contact and selecting a transport medium of the two or more transport media based on the priority order and one or more user identifications associated with the contact. The method may also include selecting a software controller in response to the selection of the transport medium based on the software controller being associated with the selected transport medium and sending the request to establish the outbound communication session to an electronic device by the selected software controller through the selected transport medium. The method may also include establishing the outbound communication session with the electronic device through the selected transport medium.

Abstract: The memory control unit includes a descriptor fetch block suitable for fetching a descriptor from a volatile memory; an instruction fetch block suitable for fetching an instruction set from an instruction memory through an address information, wherein the instruction fetch block obtains the address information from the instruction memory through an index information included in the fetched descriptor; and a memory instruction generation block suitable for generating a memory instruction by combining a descriptor parameter value included in the fetched descriptor to the fetched instruction set.

Abstract: A media item is presented via a media player, the media player configured to receive the media item, the media item being associated with a format and including an audio component. Responsive to a change in a display mode associated with the media player, a second media player is identified that is configured to receive a corresponding media item, the corresponding media item being associated with a second format and including a second audio component that matches the audio component. A particular location is determined in the media item to cease presentation of the media item via the media player and a corresponding location in the corresponding media item to begin presentation of the corresponding media item using the second media player. Responsive to reaching the particular location, concurrently, presentation of the media item is ceased and presentation of the corresponding media item at the corresponding location is begun.

Abstract: Exemplary embodiments include a socket interposer having a plurality of connectors configured to attach to a server board, the server board including: a first processor socket having a processor form factor, and a first memory associated with the first processor socket, a processor inserted into the at least first processor socket, the processor having access to the first memory, and a second processor socket having the processor form factor, and a second memory associated with the second processor socket, wherein the plurality of connectors are configured to fit the processor form factor; and a multi-modal I/O interface having a first mode and a second mode, wherein in the first mode provides processor-to-processor communication, and the second mode provides the first processor with accessibility to the second memory associated with the second processor socket.

Abstract: Systems, methods, circuits and computer-readable mediums for managing single-wire communications. In one aspect, a method includes starting a transmission cycle by transmitting a clock pulse to a single-wire bus, sampling a data bit transmitted from a single-wire device through the single-wire bus within the transmission cycle after the transmission of the clock pulse, and determining whether a sampling period of the sampling is smaller than a sampling threshold for the data bit. In response to determining that the sampling period is not smaller than the sampling threshold, the method further includes determining that the transmitted data bit is an invalid data bit, and in response: transmitting a high logic voltage level pulse to the single-wire bus for timeout and restarting the transmission cycle for retransmission of the data bit.

Abstract: A dual-data-rate interface is provided that includes a transmitter driving a transmit pin coupled to a receive pin of a receiver. The receiver drives its receive pin with cycles of a fetch clock. The transmitter responds to each edge of the fetch clock by transmitting a bit over the transmit pin to the receiver.

Abstract: A system-on-Chip (SoC) and a load imbalance detecting method of the same are provided. The SoC includes at least one master, a plurality of slaves, an interconnect, a measurement block, a central controller. The interconnect is configured to connect the at least one master and each of the plurality of slaves. The measurement block is configured to connect each of the plurality of slaves and the interconnect using a channel and to measure a load of each of the plurality of slaves. The central controller is configured to measure a load imbalance among the plurality of channels using the measured load information.

Abstract: Methods and systems for implementing a pre-processing and processing pipeline for a queue client are disclosed. A queue client receives, from a queue service, data indicative of an estimated time to process a first message in a queue. The queue client initiates processing of the first message. The queue client receives, from the queue service, data indicative of an estimated time to pre-process a second message in the queue. The queue client initiates pre-processing of the second message during the processing of the first message. The pre-processing of the second message is scheduled based on the estimated time to process the first message and the estimated time to pre-process the second message.

Abstract: An electronic device has a management data input/output (MDIO) bus, a control unit, and an MDIO master. The control circuit receives a host command from a host device, and outputs a plurality of MDIO commands in response to the host command. The MDIO master receives the MDIO commands from the control circuit, and transmits the MDIO commands to the MDIO bus.

Abstract: A system and method is disclosed for creating and exposing virtual disk images to a host server, during a KVM session, using an HTML5 KVM virtual media client running in the Web browser of a user's device (e.g., PC workstation). The host server is able to select all or specific portions of the virtual disk image for use, whereupon the bytes representing the selected data content are packaged by the HTML5 KVM virtual media client and transmitted to the host server. Using the HTML5 KVM virtual media client to create and expose virtual disk images eliminates the problem of the Web browser not being able to directly access physical media (e.g., disks) on the user's device.

Abstract: A method is disclosed for exposing virtual disk images on a user device, which is running an HTML5 KVM virtual media client in a Web browser, and which has established a KVM session with a KVM device associated with a remote device. A selected disk image file is initially obtained by the user device and a message sent to the remote device that the disk image file is available for use. The HTML5 KVM virtual media client exposes the disk image file for use to the remote device, which sends a message to the HTML5 KVM virtual media client requesting a specific portion of the disk image file. The HTML5 KVM virtual media client receives the message and a script engine running in the Web browser creates a new file available to the Web browser of just the portion requested by the remote device, which is then transmitted to the remote device.

Abstract: The disclosure relates to a system and method where a first user may submit untested or unverified code to a first server, which code may be accessed by a user via a browser. The first server provides results of the executed code to a second server via a redirect request. The redirected output is then sent from the second server back to the user's browser. For example, the results of the executed code can be returned to the user immediately without storage, such that malicious code embedded in a result of the executed code cannot access domain resources from the same domain as a URL associated with the executed code, and only the user requesting execution of the code can see the result.

Abstract: Various embodiments are generally directed to instrumenting an interrupt service routine. A non-executable address may be provisioned and added to an execution stack to cause a page fault on a known address after execution of an interrupt service routine. The page fault on the known address can be used to trigger instrumentation operations and also to return to the interrupted process.

Abstract: A system and method for emulating a universal serial bus device is disclosed. An example embodiment may include an emulated USB (EUP) device that can emulate physical USB peripherals. This device may have a microcontroller that is programmable with software to emulate a plurality of physical USB peripheral devices by supporting multiple USB profiles. In order to emulate a specific physical USB peripheral device, the EUP device may receive specific descriptors including device identifiers related to the particular physical USB peripheral device being emulated. The EUP device may communicate with a test executor computing device that simulates the USB interactions of the physical USB peripheral device using a serial protocol. Communication between the EUP device and a computing device under test may occur via USB protocol.

Abstract: Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

Abstract: Multi-channel universal serial bus (USB) to subrate channel systems and methods are disclosed. According to an aspect, a system includes a USB interface configured to communicatively connect to a computing device. The system may also include a multi-channel interface configured to communicatively connect to multiple subrate channels. Further, the system may include a controller configured to communicatively connect the subrate channels with the computing device via the USB interface. The controller may also be configured to communicate, to the computing device, connection specifications for the subrate channels.

Abstract: An access controlling method of a dual port memory system is provided. The method includes: requesting, by a first processor, an access from a dual port memory; and transmitting, by the dual port memory, a result signal according to the access request to the first processor, wherein the result signal includes a first result signal for notifying access success, a second result signal for notifying access failure, and a third result signal for notifying access hold.

Abstract: Provided is a communication system including a master device that transmits a signal transmitted from an upstream side to a downstream side, and plural slave devices connected in series to the downstream side of the master device, wherein the slave devices include a communications port that communicates with the upstream side and at least one communications port that communicates with the downstream side, and the master device sequentially sets identification information that identifies the slave device from another slave device from the upstream side to the downstream side by sequentially transmitting a setting information towards all of the plural slave devices.

Abstract: A system includes an input/output adapter operable to receive a plurality of packets. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet including completion data on a first multi-stage pipeline and a second packet including completion data on a second multi-stage pipeline in parallel. The controller shares completion update information between the first multi-stage pipeline and the second multi-stage pipeline based on determining that the completion data of the first packet and the completion data of the second packet are associated with a same request. An aspect of the completion update information is adjusted to maintain a sequential completion order in a buffer to hold the completion data of the first packet and the completion data of the second packet based on the sharing of the completion update information between the first multi-stage pipeline and the second multi-stage pipeline.

Abstract: Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.

Abstract: A method and an information handling system (IHS) perform server boot failure recovery by disabling failed devices and/or failed functions within functional devices. According to one aspect, a processor-executed fault isolation module (FIM) initiates calls to detected devices during a binding phase. The FIM identifies devices corresponding to successfully completed calls as operational devices, and identifies devices corresponding to failed calls as failed devices. Following completion of the binding phase, the FIM initiates calls, via a pre-boot application, to individual protocol functions of each operational device identified during the binding phase. If a first protocol call to a first operational device is successfully completed, the FIM identifies a protocol function(s) corresponding to the first protocol call as an operational function(s).

Abstract: System, methods and apparatus are described that offer improved performance of a camera control interface (CCIe) bus. A method of data communications includes transmitting a first synchronization code on a serial bus, establishing synchronization with a first device coupled to the serial bus in response to the first synchronization code, communicating with the first device over the serial bus in accordance with a first protocol, after establishing synchronization with the first device, transmitting a first unsynchronization code on the serial bus, where the unsynchronization code is configured to cause a loss of synchronization with the first device, transmitting a second synchronization code on the serial bus, establishing synchronization with a second device coupled to the serial bus in response to the second synchronization code, and communicating with the second device over the serial bus in accordance with a second protocol, after establishing synchronization with the second device.

Abstract: A method for extending a Peripheral Component Interconnect Express (PCIe) domain. A configuration space address can be allocated to a PCIe device in an extended domain from a memory address of a root complex endpoint device, a correspondence between the configuration space address and a bus number/device number/function number (BDF) can be established, and a bus number can be allocated from a second bus set of the extended domain to a PCIe device discovered in the extended domain, where the bus number is used for determining the BDF of the PCIe device discovered in the extended domain, so as to access, according to the correspondence between the configuration space address and the BDF and by using the BDF of the PCIe device discovered in the extended domain, a configuration space register of the PCIe device discovered in the extended domain.

Abstract: One aspect of a multiple data type interface device can include a plurality of upstream ports, wherein at least two of the upstream ports are of a different type, a plurality of downstream ports, wherein at least one of the plurality of downstream ports is configured to connect to an external device, and one or more processors configured to detect a connection at one of the plurality of upstream ports, and route an upstream port signal associated with one of the plurality of upstream ports to the at least one of the plurality of downstream ports configured to connect to the external device when the connection is detected at the one of the plurality of upstream.

Abstract: Provided is a method of driving a system-on-chip (SOC). The method includes adding a first transaction to a list, allocating the first transaction to a first slot, determining whether a second transaction is redundant, and adding the second transaction to the list and allocating the second transaction to the first slot when it is determined that the second transaction is redundant. Accordingly, the SOC can increase outstanding capability and enhance performance of a system interconnection.

Abstract: A method and system are provided for implementing a hierarchical high radix switch with a time-sliced crossbar. The hierarchical high radix switch includes a plurality of inputs and a plurality of outputs. Each input belongs to one input group; each input group sends consolidated requests to each output, by ORing the requests from the local input ports in that input group. Each output port belongs to one output group; each output port grants one of the requesting input groups using a rotating priority defined by a next-to-serve pointer. Each output group consolidates the output port grants and allows one grant to pass back to an input group. Each input port in an input group evaluates all incoming grants in an oldest packet first manner to form an accept. Each input group consolidates the input port accepts and selects one accept to send to the output port.

Abstract: Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair of embedded high speed serial interface data lines, the SE1 indicating a register access protocol (RAP) message follows the SE1 signal. The method also includes accessing a register of an embedded high speed serial interface component based on the RAP message.

Abstract: Using relatively inexpensive, external resistor networks, an electronic device, such as an FPGA, can be configured to use non-MIPI interfaces to communicate with one or more MIPI-compliant devices, such as video sources (e.g., cameras) and sinks (e.g., displays). High-speed (HS) and low-power (LP) MIPI signaling for each MIPI clock/data lane is supported by a set of one or more non-MIPI interfaces, such as LVDS and/or LVCMOS receivers, transmitters, and/or transceivers, and an appropriate, corresponding, external resistor network. For configurations in which the resistor-configured electronic device can handle high-speed MIPI data from a MIPI-compliant device, the electronic device can detect transitions in the MIPI mode of the MIPI-compliant device. In some configurations, the resistor-configured electronic device can provide high-speed MIPI data to a MIPI-compliant device. In either case, the electronic device configures the non-MIPI interfaces to support the current MIPI HS/LP mode.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A processor receives a deadlock detection message transferred between a plurality of controlled devices so as to be transferred between a plurality of nodes along a first link and a second link, and determines whether a deadlock has occurred on the basis of a history of the deadlock detection message. The plurality of nodes are combined using the first link extending from a first node to a second node and the second link extending from a third node to a fourth node. The first node corresponds to a first controlled device whose control right a first terminal has. The second node corresponds to a second controlled device whose control right the first terminal has. The third node corresponds to a third controlled device whose control right a second terminal has. The fourth node corresponds to a fourth controlled device whose control right the second terminal waits to be given.

Abstract: A rack management method and system is disclosed. The method includes detecting the presence of a computing device releasably mounted in a frame, the detecting based on an electrical connection established between a configuration bar disposed in a rear portion of the frame and the computing device, and determining a physical location of the computing device within the frame based on the electrical connection. The method also includes retrieving management information about the computing device from a profile storage disposed within the computing device via the electrical connection and storing the management information in a management table, the management table associating the computing device with the physical location within the frame.

Abstract: A request to send a first message from a first component to a second component is received at an arbiter. The first component is located in a first time zone and the second component is located in a second time zone. The arbiter determines that the second component is located in the second time zone. It is determined that the second time zone can be communicated with via one or more communications channels in a first direction. It is determined whether bandwidth is available on the one or more communications channels in the first direction. If bandwidth is available on the one or more communications channels in the first direction, a data path between the first component and the one or more communications channels in the first direction is created and the request is granted. Otherwise, the grant of the request is delayed.

Abstract: Disclosed are alternate embodiments of various components of a barrier operator system. and methods of operation, including of the mechanical drive subsystem with segmented and self-locking rail unit, rail mounting supports, belt and chain drive tensioning, and drive assembly carriage and interface; the electronics and software routines for controlled operation of the various barrier operator functions; wall console communications with the barrier operator; encryption and decryption of access codes; establishment and monitoring of travel limits and barrier speed and force profiles; thermal protection of barrier operator drive motors; and establishment and control of communications from the barrier operator to accessories by way of a wireless adapter.

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract: A pull-up resistor of an electronic device pulls up a potential of a USB signal line that is for connection with a host, thereby allowing the host to detect a communication speed. In response to a status request from the host in a normal power mode, a transmission-reception section transmits a status response indicating a switchable status when the electronic device is switchable to a power saving mode. A control section performs switching to the power saving mode after the host suspends transmission of the status request upon receipt of the status response, and performs switching to the normal power mode in response to a specific event within the electronic device in the power saving mode. A switch disables the pull-up to inform the host about disconnection, and enables the pull-up to inform the host that the connection is re-established, thereby causing transmission of the status request to be resumed.

Abstract: A dock for interacting with a computing device. The computing device configures itself for operations based on its context, which may be determined form the dock by reading a value from a tag on the dock. The computing device may use low power transmissions such that receiving a value from the tag provides an indication of proximity to the dock. The value read provides an indication of a desired operation, and, in response to reading a value of the tag, the computing device may launch an application, pair with devices in the vicinity of the dock, or take other actions that configure the computing device. A universal dock, usable with computing devices of a plurality of form factors, may be implemented by providing an array of tags and, in some cases, a non-contact power supply.

Abstract: In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect and to transmit the packet. This packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.

Abstract: An aspect of present disclosure relates to a computer-implemented method for handling two SGPIO channels by using one SGPIO decoder. The method includes: (a) establishing communication between a backplane controller and a host computer through HBA, (b) receiving control commands and control data for monitoring and controlling a first and a second group of drive slots, (c) checking a clock signal having a first time period and a second time period, (d) forwarding the control commands and control data for the first group to the first group of drive slots during first time period, and forwarding the control commands and control data for the second group to the second group of drive slots during second time period, (e) receiving responses from first and second group of drive slots, respectively, and (f) sending the responses from first and second group of drive slots to the host computer.

Abstract: A method and a random bit generator for generating a random output bit sequence. In this method, a configuration of 2n state machines is used, the state machines each including n state bits, each state machine always assuming a different state than the other state machines of the configuration, an input signal being supplied to the input end of the state machines, and these each generating n signature bits, which together form a signature bit sequence, as a function of their state, the random output bit sequence being generated by selection of individual bits from the signature bit sequences of all state machines of the configuration.

Abstract: A method, system, and/or computer program product for dynamic array masking is provided. Dynamic array masking includes, during execution of computer instructions that access a cache memory, detecting an error condition in a portion of the cache memory. The portion of the cache memory contains an array macro. Dynamic array masking, during the execution of the computer instructions that access a cache memory, further includes dynamically setting mask bits to indicate the error condition in the portion of the cache memory and preventing subsequent writes to the portion of the cache memory in accordance with the dynamically set mask bits. Embodiments also include evicting cache entries from the portion of the cache memory. This evicting can include performing a cache purge operation for the cache entries corresponding to the dynamically set mask bits.