Abstract: A resource request arbitration device is connected with each of a plurality of masters, and arbitrates transfer requests issued by the masters. The resource request arbitration device includes a plurality of counters each indicating a slack time of a transfer request issued by a master corresponding to the counter, and compares counter values stored in the counters by a tournament method, and specifies a master that has issued a transfer request having the highest priority. The resource request arbitration device grants access permission to the specified master to permit the specified master to use a slave.

Abstract: An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is op

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Abstract: An access control apparatus which establishes a connection based on connection establishment requests from connected devices and controls accesses to a connection target device. The access control apparatus includes a connection information managing unit which manages connect wait conditions to the connection target device of the connected devices based on criterion information in a connection request transmitted from the connected devices and determination for selecting one connected device from the connected devices. The access control apparatus includes a selecting unit which selects one of the connected devices which has a delay tendency related to connection based on adjustment information which is set in accordance with the connect wait conditions of the connected devices and increases a delay tendency in connection of the connected device, and a determining unit which determines the connected device selected by the selecting unit as one to be connected to the connection target device.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: A device for generating a priority value of a processor in a multiprocessor apparatus, the device comprising a counter, an interface for receiving signals from an arbiter, wherein the signals indicate decision of the arbiter about granting or denying access to a common resource in said multiprocessor apparatus. The counter is adapted to change its value in response to said signal and the changes of the counter go in opposite directions depending on the type of signal received from the arbiter. The device is also adapted to send the modified value of the counter as a new priority value to the arbiter.

Abstract: A bus arbitration system, a method of connecting a master device and a peripheral over a bus system of an IC and an IC is provided. In one embodiment, the bus arbitration system includes: (1) a bus system configured to couple master devices to peripherals, port arbiters coupled to the bus system, wherein each of the port arbiters uniquely corresponds to one of the peripherals and is configured to manage access to the uniquely corresponding peripheral and a request splitter configured to receive connection requests from the master devices for the peripherals and direct the connection requests to a specific one of the port arbiters according to a port identifier associated with each of the connection requests.

Abstract: A communication system including a resource and an arbiter. The resource is shared among a plurality of requestors such that, at any given time, only one of the plurality of requestors has access to the resource. The arbiter is configured to receive a request from each of the plurality of requestors to access the resource, in which each request has a priority level associated with the request. The arbiter is further configured to age each request at a different rate relative to that associated with another request, and grant each requestor access to the resource based on i) the priority level and/or ii) the age of the request corresponding to the requestor.

Abstract: Interconnect circuitry 2 has a plurality of data source circuits 8 connected to respective input paths 4 and a plurality of data destination circuits 10 connected to respective output paths 6. Connection cells 12 provide selective connections between input paths 4 and output paths 6. Arbitration circuitry 26 provides adaptive priority arbitration between overlapping requests received at different input paths. Priority bits 16 within a matrix of priority bit 46 for each output path 10 are used to represent the priority relationships between different input paths which compete for access to that output path 10. Update operations are applied on a per row or per column basis within the matrix to implement update schemes such as least recently granted, most recently granted, round robin, reversal, swap, selective least recently granted, selective most recently granted etc.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: An on-chip Radio Frequency (RF) Interconnect (RF-I) for communication between internal circuit nodes of an integrated circuit is provided. In one embodiment, an integrated circuit is provided that includes an on-chip transmission line, a first circuit node associated with an RF transmitter connected to the transmission line, and a second circuit node associated with an RF receiver connected to the transmission line. In order to transmit data from the first circuit node to the second circuit node, the RF transmitter associated with the first circuit node modulates the data onto an RF carrier frequency to provide a modulated RF signal and transmits the modulated RF signal over the transmission line. The RF receiver associated with the second circuit node receives the modulated RF signal from the transmission line and demodulates the modulated RF signal to recover the data for the second circuit node.

Abstract: An apparatus for performing arbitration increases the fairness of arbitrations, decreases system latency, increases system throughput, and is suitable for use in more complex systems. According to an exemplary embodiment, the apparatus includes a generator for generating a plurality of arbitration numbers corresponding to a plurality of agents, and circuitry for selecting one of the agents to access a resource shared by the agents based on the arbitration numbers. At least one of the arbitration numbers includes a plurality of fields corresponding to a plurality of parameters.

Abstract: Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.

Abstract: A bus host controller and a method thereof are provided. If a terminal device coupled to the bus is a non-periodic device, the bus host controller places a higher priority on data packet transferring request than start-of-frame (SOF) packet transferring request.

Abstract: An arbiter, a system, and a method for generating a pseudo-grant signal in response to a request and receiving target information in response to the pseudo-grant signal. The pseudo-grant signal reduces or eliminates waiting time.

Abstract: When selecting one command within a processor from a plurality of command queues vested with order of priority, the order of priority assigned to the plurality of command queues is dynamically changed so as to select a command, on a priority basis, from a command queue vested with a higher priority from among the plurality of command queues in accordance with the post-change order of priority.

Abstract: A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.

Abstract: A method and apparatus for intelligently routing and managing audio signals within an electronic device is disclosed. The routing is responsive to a set of logical and physical policies which are stored in data tables which can be updated as needed.

Abstract: Method of processing data of at lease one data stream, data processing module for processing at a of at least one data stream, data processing system comprising such module, computer program product, data storage system and method of use thereof. For a time-based transfer of data to or from a device, data streams may be given a system ID and it is proposed to dynamically distribute available stream IDs. The proposed concept provides for indicating a type of data stream, providing and/or handling a set of stream IDs comprising a number of stream IDs and issuing a stream ID from the set of stream IDs to the data stream depending on the type of data stream. In a preferred embodiment, it is proposed to reserve one stream ID for an audio-video request, characterized by having no error handling time available. A further stream ID may be reserved for best effort requests.

Abstract: A priority determining method and apparatus can reduce a total waiting time of DMA request blocks by granting priority to each of Direct Memory Access (DMA) request blocks transmitting a DMA request signal, based on Data Transfer Amounts (DTAs) of the DMA request blocks and Arrival Times (ATs) of the DMA request signals, counting the number of priority changes of each of DMA request blocks whose priority is changed in the priority granting process, and if a DMA request signal is received from a new DMA request block, determining priorities of the DMA request blocks based on the counted the number of priority changes.

Abstract: There is described a method, a bus protocol, a peripheral module, a processing unit, a hub and also to a system consisting of said components, for event signaling between at least one peripheral module and a processing unit by means of a system bus. In this case the data to be transmitted data is encoded into a larger symbol space, from which a standard idle symbol is used in telegram pauses for synchronizing a connection between transmitter and receiver. A message present at the peripheral modules is enabled to be signaled to the processing unit independently of the telegram traffic initiated by the processing unit.

Abstract: An arbiter in a communication system including a plurality of request shapers in communication with a plurality of requestors. Each request shaper is configured to receive a request for access to a resource of the communication system, initially assign a priority level to the request upon receipt of the request, increase an age of the request, after increasing the age of the request, compare the age of the request to a delta period value associated with the respective requestor, and repeatedly increase the priority level of the request based on the comparison. Each of the plurality of requestors has a corresponding delta period value that is different from that of other ones of the plurality of requestors. An arbiter core is configured to grant one of the plurality of requestors access to the resource based on the priority level of each request and the age of each request.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: The invention relates to methods and devices for generating a distribution function. To that end preference vectors are defined for each instance something is distributed to from which elements are selected by means of an arbitration vector.

Abstract: A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A selector selects one of the arbiters to select the one of the multiple scheduled TLPs and DLLPs for transmission. A programmable storage element provides a value to control the selector. In one embodiment, the distinct priority rule employed by at least a first of the arbiters prioritizes TLPs higher than Ack/Nak DLLPs, and the distinct priority rule employed by at least a second of the arbiters prioritizes Ack/Nak DLLPs higher than TLPs. In one embodiment, at least a first arbiter prioritizes TLPs higher than Ack/Nak DLLPs and UpdateFC DLLPs, at least a second arbiter prioritizes Ack/Nak DLLPs higher than TLPs and UpdateFC DLLPs, and at least a third arbiter prioritizes UpdateFC DLLPs higher than TLPs and Ack/Nak DLLPs.

Abstract: A system for transmitting and receiving image and audio data that is information on any of image and audio has a transmission apparatus and a reception apparatus. The transmission apparatus transmits the image and audio data using a multi-channel communication system and includes a first protocol conversion device. The reception apparatus receives the image and audio data using the multi-channel communication system and includes a second protocol conversion device. The transmission apparatus performs data conversion processing on the image and audio data by the first protocol conversion device using a protocol to produce parallel image and audio data, and transmits it to the reception apparatus using the multi-channel communication system. The reception apparatus receives the parallel data to perform data conversion processing on the parallel data using the protocol by the second protocol conversion device to return to the image and audio data.

Abstract: A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.

Abstract: A bus system is provided for implantable medical devices. The bus system provides for flexible and reliable communication between subsystems in an implantable medical device. The bus system facilitates a wide variety of communications between various subsystems. These various subsystems can include one or more sensing devices, processors, data storage devices, patient alert devices, power management devices, signal processing and other devices implemented to perform a variety of different functions.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.

Abstract: A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.

Abstract: Resource requests are allocated by storing resource requests in a queue slots in a queue. A token is associated with one of the queue slots. During an arbitration cycle, the queue slot with the token is given the priority to the resource. If the queue slot with the token does not include a request, a different queue slot having the highest static priority and including a request is given access to the resource. The token is advanced to a different queue slot after one or more arbitration cycles. Requests are assigned to the highest priority queue slot, to random or arbitrarily selected queue slots, or based on the source and/or type of the request. One or more queue slots may be received for specific sources or types of requests. Resources include processor access, bus access, cache or system memory interface access, and internal or external interface access.

Abstract: An aspect of the present invention provides an arbiter which grants a request (to access a resource) in the same clock cycle as in which the requests from requesters is received. In one embodiment, such a feature may be provided in case of arbitration policies requiring state information from previous grants. In another embodiment, such a feature may be provided when the arbitration policy is programmable such that the same arbiter can be used for different arbitration policies.

Abstract: A data processing apparatus and method are provided for arbitrating between messages routed over a communication channel. The data processing apparatus has a plurality of processing elements, each processing element executing a process requiring messages to be issued to recipient elements, and a communication channel shared amongst those processing elements over which the messages are routed. Arbitration circuitry performs an arbitration process to arbitrate between multiple messages routed over the communication channel. Each processing element issues progress data for the process executing on that processing element, the progress data indicating latency implications for the process. Arbitration control circuitry is then responsive to the progress data from each processing element to perform a priority ordering process taking into account the latency implications of each process as indicated by the progress data in order to generate priority ordering data.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: The present invention relates to a method for disconnecting a transceiver from a bus in multipoint/multidrop architecture. A central processing unit (CPU) and a universal asynchronous receiver transmitter (UART) in a system are connected to a controller used for storing and transmitting data, and the controller is further connected with a bus through a transceiver that monitors/records data and a relay that connects or disconnects the transceiver from the bus. The controller comprises a signal comparator used to compare similarities and differences of data and a failure detection controller used to achieve connection or disconnection of the bus with the transceiver. In case of the transceiver's failure, the controller disconnects the transceiver from the bus to ensure that the bus does not fail to work due to breakdown of the transceiver.

Abstract: A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.

Abstract: In a bus arbitration device that utilizes a resource use management device, upon detecting that a processor is permitted to access a memory, a detection unit decreases a counter by 1 and starts a timer, in a delay circuit, that is not in operation to count time. When the timer counts to a predetermined cycle time period, the delay circuit increases the counter by 1. A control unit permits the processor to access the memory, if the counter is larger than 0.

Abstract: A priority control value, which is smaller as the priority of access by each of requesters is higher, decreases with the lapse of time when an access request is issued. When the access is completed, the priority control value increases by a priority decrease value (PERIOD). When there is no access request, the priority control value decreases to a reference priority value (TMIN) and is then maintained at the reference priority value. Access permission is given to the one of the requesters issuing requests which has the smallest priority control value. As a result, proper arbitration is performed at a high speed with a simple hardware configuration.

Abstract: A bus of a SoC (system on chip) includes a system arbiter for controlling not only a command arbiter but also a read information arbiter, a write data control circuit, a write complete notice arbiter and the like. A sequential table containing a series of system operations including activation processing and application processing and an operation clock information circuit or the like that becomes effective when a SoC bus region is divided by an operation clock frequency are utilized in assignment of priority of buses of the system arbiter. Thus, the information transfer efficiency of the whole system bus and the information transfer efficiency of every transfer originator can be improved.

Abstract: When four access request origins A, B, C, and D are present, a priority table (No. 1) having a priority order of A, B, C, and D, a priority table (No. 2) having a priority order of B, D, A, and C, a priority table (No. 3) having a priority order of C, A, D, and B, and a priority table (No. 4) having a priority order of D, C, B, and A are prepared. An order of employing these tables is determined in advance in this order. A priority table next in the order to the priority table employed in last arbitration or, when a priority table at the bottom in the order is employed in last arbitration, a priority table at the top in the order is employed. Based on the priority levels defined in the employed priority table, an access request to be accepted is selected.

Abstract: An arbitration circuit for granting access to a shared resource among requestors comprises N request shapers, where N is an integer greater than one. An input unit receives a request from a requestor. An age unit assigns an age to the request and increases the age of the request when the requestor is not granted access to the shared resource. A priority unit assigns a priority level to each of the requests and selectively increases the priority level of the request based on the age of the respective one of the requests and a delta period of the request. An arbiter core receives the requests from the N request shapers and selectively grants access to the shared resource to each of the requestors corresponding to the requests based on the priority level and age of the requests. The delta period of one of the N request shapers is different than the delta period of another of the N request shapers.

Abstract: The remaining time period until the deadline of transfer by a device connected to a bus is measured, the remaining data size to be transferred by the device is detected, and the priority level of the device is set based on the remaining time period and the remaining data size.

Abstract: There is provided a request arbitration apparatus for arbitrating a plurality of request holding sections which hold requests having priorities when the requests are output from the plurality of request holding sections to the output device. The request arbitration apparatus includes: a setting section that sets the request holding section, which holds the highest priority request among all the requests held by the plurality of request holding sections, as a highest priority request holding section; and a control section that controls the highest priority request holding section so that the request held first among all the requests held by the highest priority request holding section is output to the output device.

Abstract: A circuit for selecting one of N requestors in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the requestors is selected next. The first addend is an N-bit vector where each bit is false if the corresponding requester is requesting access to a shared resource. The second addend is a 1-hot vector indicating the last selected requester. A multithreading microprocessor dispatch scheduler employs the circuit for N concurrent threads each thread having one of P priorities. The dispatch scheduler generates P N-bit 1-hot round-robin bit vectors, and each thread's priority is used to select the appropriate round-robin bit from P vectors for combination with the thread's priority and an issuable bit to create a dispatch level used to select a thread for instruction dispatching.

Abstract: An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.

Abstract: An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.

Abstract: A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.

Abstract: The embodiments provide an arbiter in a microprocessor that can handle requests to access a shared resource from function units with different priorities without starving the access opportunities of requests from function units with low priority. In one embodiment, a microprocessor is provided. The microprocessor includes a shared resource and a plurality of requesting entities accessing the shared resource. Each of the plurality of requesting entities has a priority value and requests from the each of the plurality of requesting entities are assigned the priority value. The plurality of requesting entities are function units of the microprocessor. The microprocessor also includes a priority-encode arbiter with an adjustable ring counter disposed between the shared resource and the plurality of requesting entities to control the access requests of the plurality of requesting entities to the shared resource.

Abstract: According to an aspect of the invention, there is provided a data transfer control device that carries out data transfer in a data transfer system, in which plural bus masters are connected to a system bus and the data transfer between the bus masters is arbitrated by bus arbitration of each of the bus masters, between the bus masters, the data transfer control device including: an execution cycle monitoring section that monitors an access state for the system bus at the bus master when plural bus masters simultaneously request a use right with respect to the system bus; and a function execution order changing control section that changes an execution order of plural functions included in the bus master to be monitored, based on the access state monitored by the execution cycle monitoring section.