Abstract: An ATA compatible data transfer system includes a system processor having system memory, the system processor configured to issue a Programmable I/O (PIO) type command to effect data transfer between a peripheral device and the system memory through a host controller and an ATA controller. The host controller accesses data to/from the host memory directly. The host controller and the ATA controller complete data transfer between the peripheral device and the system memory by executing the PIO type command without requiring interrupt servicing by the system processor.

Abstract: A method and apparatus are described to provide shared switch and cache memory. The apparatus may comprise a message switch module, a cache controller module, and shared switch and cache memory to provide shared memory to the message switch module and to the cache controller module. The cache controller module may comprise pointer memory to store a plurality of pointers, each pointer pointing to a location in the shared switch and cache memory (e.g., point to a message header partition in the shared switch and cache memory). If there is a corresponding pointer, a memory read response may be sent to the requesting agent. If there is no corresponding pointer, a write data request may be sent to a corresponding destination agent and, in response to receiving the requested data, a pointer to the stored data in the pointer memory may be provided.

Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers to multiple DMA transfer requests that are grouped in time by virtualizing DMA transfer requests into an available DMA channel identifier using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once the input values associated with the DMA transfer requests are mapped to the selected DMA channel identifier, the DMA transfers are performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfers. When there is a request to wait for completion of the data transfers, the same input values are used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.

Abstract: A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.

Abstract: A data transfer device includes: a plurality of storage devices (10) including a plurality of transfer sources (TS) of which storage regions are different from each other and setting registers (40) of which number is equal to the number of the transfer sources (TS). The setting registers (40) stores for the transfer sources (TS) DMA transfer settings of the transfer sources (TS), and a DMA control section (20) performs data transfer control on the basis of the set values of the setting registers (40).

Abstract: A method, apparatus and program storage device for enabling multiple asynchronous direct memory access task executions. DMA I/O operations and performance are improved by reducing the overhead in DMA chaining events by creating a software DMA queue when a hardware DMA queue overflows and dynamically linking new DMA requests to the software queue until a hardware queue becomes available at which time the software queue is put on the hardware queue. Thus, microcode does not need to manage the hardware queues and keep the DMA engine running continuously because it no longer has to wait for microcode to reset the DMA chain completion indicator.

Abstract: A system and method of transferring data of unknown length in a computer system includes providing an embedded device having a processing apparatus and a DMA engine, the processing apparatus processing the data and the DMA engine transferring the data from the embedded device to a component in the computer system, determining whether information from the embedded device is an address value or a data value, programming the DMA engine with the address value if the information is the address value, and transferring the data value to the address value in the component if the information is the data value.

Abstract: An IO adapter for guaranteeing the data transfer bandwidth on each capsule interface when multiple capsule interfaces jointly share the DMA engine of the IO adapter. An IO driver containing a capsule interface information table including bandwidth information and for setting the forming status of a pair of capsule interfaces and, during data transfer subdivides the descriptors for the capsule interfaces into multiple groups for each data buffer size satisfying the preset bandwidth information and, copies one group at each fixed sample time set by the descriptor registration means, into the descriptor ring and performs DMA transfer. To control this copy information, the IO driver contains a ring scheduler information table for managing the number of descriptor entries for the capsule interface cycle time and, a ring scheduler cancel means for renewing the entries in the ring scheduler information table each time one transmission of the descriptor group ends.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A direct memory access (DMA) transfer apparatus configured to sequentially read, into a register, at least one transfer setting value for data transfer stored in a memory and to perform DMA transfer processing based on the read transfer setting value includes a unit configured to receive a No Operation (NOP) designation for designating no performance of DMA transfer as the transfer setting value, and a unit configured to generate, if the NOP designation has been performed with the transfer setting value read into the register, an NOP interrupt signal to end transfer processing without performing the DMA transfer.

Abstract: A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

Abstract: A method, medium and system for setting a transfer unit in a data processing system. The method comprises setting a transfer unit in a data processing system which repeatedly performs a process of transmitting data stored in a first memory to a second memory in a predetermined transfer unit, processing the transmitted data stored in the second memory, and transmitting the processed data to the first memory. The method includes computing overhead on the data processing system according to the size of each of a plurality of data units available as the transfer unit; and setting a data unit, which corresponds to a minimum overhead from among the computed overheads, as the transfer unit. Accordingly, it is possible to set an optimum transfer unit according to an environment of a data processing system in order to improve the performance of the data processing system.

Abstract: There is provided a transfer apparatus having a bridge that transfers a transaction between a first and a second bus, and a data transfer unit that performs a data transfer by DMA between the first and second bus. The transfer apparatus controls a transfer sequence of transaction transfers by the bridge and data transfers by the data transfer unit, in which transaction transfers by the bridge are based on bus sequencing rules and data transfers by the data transfer unit are based on a data transfer activation condition.

Abstract: A method for evaluating performance of DMA-based algorithmic tasks on a target multi-core processing system includes the steps of: inputting a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; evaluating performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and providing results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.

Abstract: Task management methods. A plurality of GBL (global bandwidth limiter) classes is provided. One of the GBL classes is selected based on the priority of a first task, in which the first task is from a MCU (micro-controller unit) bus. A system GBL class is selected based on the highest GBL class which has been selected among the GBL classes. A bandwidth limiter of a DMA (direct memory access) unit is assigned according to the system GBL class and the priority of a second task if the DMA unit is activated by the second task. The second task is from a DMA bus, and the cycle between the DMA and MCU buses is determined according to the bandwidth limiter.

Abstract: A network element (NE) includes an intelligent interface (II) with its own operating environment rendering it active during the NE boot process, and with separate intelligence allowing it to take actions on the NE prior to, during, and after the boot process. The combination of independent operation and increased intelligence provides enhanced management opportunities to enable the NE to be controlled throughout the boot process and after completion of the boot process. For example, files may be uploaded to the NE before or during the boot process to restart the NE from a new software image. The II allows this downloading process to occur in parallel on multiple NEs from a centralized storage resource. Diagnostic checks may be run on the NE, and files, and MIB information, and other data may be transmitted from the II to enable a network manager to more effectively manage the NE.

Abstract: A method for interacting with a memory device is provided. In this method, a cryptographic communication application is registered to be associated with a protocol type in a web browser. A message encapsulated in the protocol type from the web browser is received and thereafter transmitted to the memory device. Here, the message is associated with a cryptographic operation.

Abstract: A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state processing (DMA control). Further, the channel manager circuit updates the control information, writes back the control information to the control memory, and executes time-division control of the plurality of DMA channels. Hence the circuit scale can be reduced, contributing to decreased costs, and the number of development processes can be reduced.

Abstract: An I/O controller and method are provided. The I/O controller to which an I/O device can be connected, and instructs the I/O device to execute a process includes a descriptor transfer device that transfers a descriptor indicating contents of a process to be executed, and execution instruction unit that instructs the I/O device to execute the process, based on the descriptor transferred from the descriptor transfer device, wherein the descriptor transfer device includes a memory for storing the descriptor; descriptor reading unit that reads, according to an indication regarding a descriptor read source from a processor, an indicated descriptor from a main memory or said memory which stores the descriptor, and descriptor transfer unit that transfers the read descriptor to the execution instruction unit.

Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.

Abstract: A memory access control apparatus receives from a DMA requestor an access request command, which contains an IOID, for a DMA address space that is a memory area used for a DMA transfer, and determines whether the access is permitted or not and executes the access if it is permitted. The operating system on the PU sets in MMU the correspondence relationship between the logical address space of a user process and the DMA address space. When the user process instructs to access the DMA address space by specifying a logical address, the MMU translates the logical address into a physical address of the DMA address space.

Abstract: Provided is a multi channel data transfer device. The multi channel data transfer device includes: a plurality of channel control unit connected to a plurality of peripheral devices, respectively; a plurality of control registers storing setting data for controlling an operation of each of the plurality of channel controllers; and a common register controller delivering common setting data to all or part of the plurality of control registers, the common setting data being applied in common to all or part of the plurality of channel controllers.

Abstract: A user interface between a FlexRay communications module which is connected to a FlexRay communications link over which messages are transmitted and which includes a message memory for buffer storing messages from the FlexRay communications link or for the FlexRay communications link, and a microcontroller which is assigned to the FlexRay communications module and which includes a microprocessor and a direct memory access (DMA) controller for exchanging data with the message memory. In order for the DMA controller of the microcontroller to be connected more effectively to the FlexRay communications module, the user interface has a state machine, which, once configured by the microprocessor of the microcontroller, independently coordinates and controls a data transmission between the message memory of the FlexRay communications module and the DMA controller.

Abstract: A mechanism for programming a direct memory access engine operating as a single thread processor is provided. A program is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the program located in the local memory is to be executed. The direct memory access engine executes the program without intervention by a host processor. Responsive to the program completing execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

Abstract: Provided herein is multi-function platform comprising a plurality of devices and a large memory that is external to the devices and shared among the devices. In an embodiment, a Direct Memory Access (DMA) controller is provided for each device to efficiently transfer data between the device and the shared memory. More than one DMA may be provided for a device. For example, separate DMAs may be provided for different components of a device that perform different subfunctions enabling efficient transfer of data between the different components of the device and the shared memory. In another embodiment, each device comprises a local embedded memory and is provided with a DMA for transferring data between the local memory and the shared memory. Examples of devices that can be included in the platform include a GNSS receiver, a audio player, a video player, a wireless communication device, a routing device, or the like.

Abstract: This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media processors (DMP). The prescribed interface programs signals available in the DMP external memory interface (EMIF) functions to match the requirements of ATA-HDD PIO functions. Selected signal redefinition and minimal glue logic is employed to form a seamless link between the EMIF I/O of the digital media processor DMP and the ATA-HDD hard drive.

Abstract: A data transfer control device includes a PATA I/F connected to a PATA bus, an SATA I/F connected to an SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register (TFR). The sequence controller suspends transmission of a register FIS corresponding to an ATA packet command issued by a host to a device, and performs a dummy setting that causes the host to issue an ATAPI packet command using the TFR. The sequence controller transmits the register FIS corresponding to the ATA packet command to the device after the host has issued the ATAPI packet command.

Abstract: An electronic device includes routing logic operatively coupled to a communication port that is externally accessible so that there is no need to disassemble the electronic device to gain access. The port may be a USB port and provides access to an internal bus. The routing logic is also operatively coupled to a memory subsystem such that it may route data from an external device, connected at the port, to the memory subsystem to modify or replace a boot code, including a BIOS code. A memory interface device includes an interface module, a memory interface module for communicating with a memory subsystem including a boot PROM, and a routing logic coupled to the interface module and the memory interface module. The routing logic routes data from the external device to the boot PROM, so that a boot code, including a BIOS, may be modified or replaced.

Abstract: A computer-implemented method, apparatus, and computer program product are disclosed for migrating data from a source physical page to a destination physical page. A migration process is begun to migrate data from the source physical page to the destination physical page which causes a host bridge to enter a first state. The host bridge then suspends processing of direct memory access operations when the host bridge is in the first state. The data is migrated from the source physical page to the destination physical page while the host bridge is in the first state.

Abstract: A network element (NE) includes an intelligent interface (II) with its own operating environment rendering it active during the NE boot process, and with separate intelligence allowing it to take actions on the NE prior to, during, and after the boot process. The combination of independent operation and increased intelligence provides enhanced management opportunities to enable the NE to be controlled throughout the boot process and after completion of the boot process. For example, files may be uploaded to the NE before or during the boot process to restart the NE from a new software image. The II allows this downloading process to occur in parallel on multiple NEs from a centralized storage resource. Diagnostic checks may be run on the NE, and files, and MIB information, and other data may be transmitted from the II to enable a network manager to more effectively manage the NE.

Abstract: A direct memory access controller has a data register for transferring data from a source to a destination address. A pattern register is provided and a data comparator is coupled with the data register and the pattern register for comparing the content of the data register with the content of the pattern register. A control unit coupled with the comparator controls the data flow and stops a data transfer if the comparator detects a match of the data register and the pattern register.

Abstract: A DMA transfer control apparatus comprises an internal memory for temporarily storing data, a buffer for temporarily storing data, a selector for selecting one of input data to the buffer and output data from the buffer per byte, and a rotator for rotating data. The internal memory receives read data from a transfer source, the buffer receives data from the internal memory, the selector receives data from the internal memory and data from the buffer, and the rotator receives data selected by the selector. An output of the rotator is used as write data. Thereby, high-speed DMA transfer is performed even when data transfer source addresses and data transfer destination addresses have different byte alignments where the addresses are located.

Abstract: A computer that operates in a metered mode for normal use and a restricted mode uses an input/output memory management unit (I/O MMU) in conjunction with a security policy to determine which peripheral devices are allowed direct memory access during the restricted mode of operation. During restricted mode operation, non-authorized peripheral devices are removed from virtual address page tables or given vectors to non-functioning memory areas.

Abstract: Methods and apparatus are disclosed for identifying a system. In various embodiments, values of identification codes are read from each of a plurality of electronic devices of the system. The values of the identification codes are used to generate a system identifier value.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: A method for the transmission of digital messages by the output terminals of a monitoring circuit which is integrated into a microprocessor, the digital messages being representative of first specific events which are dependent on the execution of a series of instructions by the microprocessor.

Abstract: A system control device comprises a system LSI section having a plurality of functional blocks, a system control microcomputer section for controlling the control register of each of the functional blocks, an address decoding section for decoding an access address to a predetermined byte in a control register which the system control microcomputer section attempts to access, and issuing an access control signal to the whole of a single control register including the predetermined byte, an access control section for changing the access control signal to the whole of the single control register to an access control signal to the predetermined bytes of the plurality of control registers included in the system LSI section, with respect to access to an address to the predetermined byte, and an access mode control register for indicating whether or not the changing by the access control section is to be performed.

Abstract: A method and system in which one or more hardware accelerators are directly accessible via a direct memory access controller (DMAC) including an internal mechanism. In some embodiments, the internal mechanism may include a local interconnect in the DMAC. In other embodiments, a DMAC structure includes a mechanism that provides for streaming data through hardware accelerators and allows for simultaneous reads and writes among multiple endpoint pairs transferring data. For added flexibility and increased independence from a microprocessor, a DMAC may include a command decoder that discovers, decodes and interprets commands in a data stream.

Abstract: A media processing system and device with improved power usage characteristics, improved audio functionality and improved media security is provided. Embodiments of the media processing system include an audio processing subsystem that operates independently of the host processor for long periods of time, allowing the host processor to enter a low power state. Other aspects of the media processing system provide for enhanced audio effects such as mixing stored audio samples into real-time telephone audio. Still other aspects of the media processing system provide for improved media security due to the isolation of decrypted audio data from the host processor.

Abstract: The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling the software program management of the caches. The commands include commands for writing data to the cache, loading data from the cache, and for marking data in the cache as no longer needed. The cache can be a system cache or a DMA cache.

Abstract: Methods and systems for customizing information in a memory associated with a SAS host bus adapter (“HBA”). A SAS HBA typically includes a memory component that stores information common to all SAS HBA's manufactured by a particular vendor (e.g., common instructions and data). In addition, each HBA memory component typically includes some information unique to each HBA (e.g., board trace number, SAS address, configuration page, boot record, etc.). Features and aspects hereof permit pre-programmed memory components to be integrated with a SAS HBA to eliminate a step to program an assembled HBA through a specialized, one-time interaction to add required unique information. Thus a manufacturer may simply integrate a pre-programmed memory component to an otherwise completed HBA assembly to complete the product manufacturing without need for a special programming step. Or a design or test engineer may simply replace a memory component to change unique information on the HBA.

Abstract: The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the control method of the serial communication, in which a DMA controller is used for the data reception in the serial communication, and a number larger than the number of data received at a time is set in advance as the number of transfers of the receive DMA controller, and further, the function to generate the timeout interrupt when data is not received for a certain period is added to the serial interface, so that the serial communication can be controlled and performed without applying the load on the CPU.

Abstract: A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.

Abstract: A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a processor core, local memory and DMA module. The local memory of the idling SPE stores data stored in the global memory and used by the processor core of the running SPE, before the data is used by the processor core of the running SPE. The DMA module of the running SPE reads the data from the local memory of the idling SPE, and transfers the data to the processor core of the running SPE.

Abstract: A method is provided for simultaneously loading and executing program code in a circuit system. The circuit system includes a plurality of memory devices, a microprocessor, and a loading circuit. The method includes dividing the program code into a plurality of code divisions and utilizing the microprocessor to execute at least a code division when the loading circuit loads any other code division into a memory device of the plurality of memory devices.

Abstract: A system and method is disclosed for prioritizing requests received from multiple requesters for presentation to a shared resource. The system includes logic that implements multiple priority schemes. This logic may be programmably configured to associate each of the requesters with any of the priority schemes. The priority scheme that is associated with the requester controls how that requester submits requests to the shared resource. The requests that have been submitted by any of the requesters in this manner are then processed in a predetermined order. This order is established using an absolute priority assigned to each of the requesters. This order may further be determined by assigning one or more requesters a priority that is relative to another requester. The absolute and relative priority assignments are programmable.

Abstract: A direct memory access (DMA) device includes a barrier and interrupt mechanism that allows interrupt and mailbox operations to occur in such a way that ensures correct operation, but still allows for high performance out-of-order data moves to occur whenever possible. Certain descriptors are defined to be “barrier descriptors.” When the DMA device encounters a barrier descriptor, it ensures that all of the previous descriptors complete before the barrier descriptor completes. The DMA device further ensures that any interrupt generated by a barrier descriptor will not assert until the data move associated with the barrier descriptor completes. The DMA controller only permits interrupts to be generated by barrier descriptors. The barrier descriptor concept also allows software to embed mailbox completion messages into the scatter/gather linked list of descriptors.

Abstract: DMAC includes current transfer setting registers and next transfer setting registers. Each of the current transfer setting registers stores transfer source address, transfer destination address and transfer count. The next transfer setting registers stores a transfer setting of a DMA transfer carried out after completing a DMA transfer according to a current transfer setting stored in the current transfer setting registers as a next transfer setting. Further, flags are provided for controlling to write to each of the next transfer setting registers.

Abstract: A video multiviewer system includes a Graphics Processing Unit (GPU) that includes a GPU memory. A video input module is operative with the GPU for receiving video data and transferring the video data to the GPU memory via a Direct Memory Access (DMA). A programmable circuit such as a Field Programmable Gate Array (FPGA) includes a multi-ported and in one aspect a dual ported block Random Access Memory (RAM) configured for a plurality of DMA channels for receiving video data and allowing uninterrupted operation of consecutive DMA transfers of video data to the GPU memory. A display displays the multiple video windows based upon video data received within the GPU memory.

Abstract: A method and system for transferring units of data between a computer memory and an external system in which a DMA controller stores and uses information from an I/O device interfacing with the external system to transfer data more efficiently.