Abstract: Systems, apparatuses and methods may provide for a frontend driver that notifies a hypervisor of a map request from a guest driver of a device, wherein the device is passed through to and directly controlled by a virtual machine, and wherein the map request is associated with an attempt of the device to access a guest memory page in a virtualized execution environment. The frontend driver may also determine whether the guest memory page is pinned and send a map hypercall to the hypervisor if the guest memory page is not pinned. Additionally, the hypervisor may determine that the guest memory page is pinned, determine, based on a direct memory access (DMA) bitmap, that an unmap request from the guest driver has been issued, and unpin the guest memory page.

Abstract: A plurality of signals within a memory sub-system are analyzed by a signal analyzer component. Relevant signals among the plurality of signals are determined by the signal analyzer component such that the relevant signals comprise a subset of signals among the plurality of signals. Information corresponding to the relevant signals is sampled by the signal analyzer component and the signal analyzer component is responsible for extracting the information corresponding to the relevant signals among the plurality of signals.

Abstract: An example non-transitory computer readable storage medium comprising instructions that when executed cause a processor of a computing device to: in response to a trigger of a system management mode (SMM), verify all processor threads have been pulled into the SMM; in response to a successful verification, enable write access to a non-volatile memory of the computing device via two registers, where the writing access is disabled upon booting of the computing device; and upon exiting the SMM, disable the write access via the two registers.

Abstract: A system has data capture devices collecting data from different points in a network. The captured data is written to a data store and is directed to an output. The data from the different data capture devices can be delivered to a data analytics device. As long as the data analytics device is able to keep pace with the data that is directed to the output, that data is used by the analytics device. If the analytics device is not able to keep pace, the data written to the data store is retrieved and is used until the analytics device has caught up.

Abstract: Disclosed are systems and methods for behavioral modeling based on content genre and utilizing results for content recommendation and other network handling and storage of the content. Viewing events with respect to a content item are aggregated. An affinity is calculated based on the viewing events. Additional viewing events occurring during the delivery of the content item and associated with other content items are also selected. A sampling bonus is added to the affinity if these additional viewing events have a duration below a threshold and the other content items share a same genre as the content item.

Abstract: Retiring instructions out-of-order includes: receiving processor instructions comprising two or more and fewer than all processor instructions generated based on a program, where the processor instructions include a first instruction and a second instruction such that the first instruction precedes the second instruction in a program order of the program; receiving a start instruction that immediately precedes the processor instructions and indicates that the processor instructions are to be retired out-of-order; receiving a stop instruction immediately that succeeds the processor instructions and indicates a stop to out-of-order instruction retirement; and, in response to completing execution of the second instruction before completing execution of the first instruction, retiring the second instruction before retiring the first instruction.

Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

Abstract: An electronic trading system (ETS) implements risk mitigation methods for orders and quotes associated with a market participant on the ETS. The methods determine a measure of risk associated with one or more trading positions. One of the methods globally counts the number of breaches of risk thresholds associated with a trading symbol and market participant across all matching engines on the ETS over a rolling time period, and if this global risk counter exceeds a maximum, disables all further trades by the market participant on the ETS. Another method limits the number of automatic re-enablements that a market participant can request in response to prior breaches of risk thresholds that resulted in disabling any further trading by the market participant on the ETS.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Abstract: A data processing apparatus has processing circuitry with transactional memory support circuitry to support execution of a transaction using transactional memory. In response to an exception mask updating instruction which updates exception mask information to enable at least one subset of exceptions which was disabled at the start of processing of a transaction, the processing circuitry permits un-aborted processing of one or more subsequent instruction of the transaction that follow the exception mask update instruction.

Abstract: A fault tolerant system includes a primary virtual machine and a secondary virtual machine. The primary virtual machine includes a synchronizing information generator and a first interrupt blocker. The synchronizing information generator executes bytecode and outputs synchronizing information based on information related to the executed bytecode. The first interrupt blocker blocks an interrupt inputted from an external location. The secondary virtual machine includes a synchronous execution unit that executes the bytecode based on the synchronizing information and a second interrupt blocker that blocks the interrupt. When the interrupt is acquired, the synchronizing information generator executes the bytecode based on the interrupt. The first interrupt blocker outputs the interrupt to the synchronizing information generator when the interrupt is inputted during execution of an instruction, included in the bytecode, to accept the interrupt.

Abstract: The present disclosure relates to system and methods for predicting performance caused by software code changes. For this purpose, an augmented machine learning model predicts a latency of software module with updated code executed in a production environment. In some aspects, the latency is predicted based on a change of deviation that is determined by comparing the latency of the software module with updated code and the latency of the software module without updated code, whereas the software modules are executed in environments different from the production environment.

Abstract: A control method for an optical transceiver includes interrupting internal repetitive internal processing in response to a command from a host apparatus and executing an interrupt process for transmitting monitoring data. The method sets a processing mode of the interrupt process to a first processing mode when a processing time necessary to execute the interrupt process and one cycle of the repetitive processing is shorter than a threshold value, and to a second processing mode when the processing time necessary to execute the interrupt process and one cycle of the repetitive processing is longer than the threshold value. In the first mode, the interrupt process stores first monitoring data read out from a memory unit in a transmission register, stops the stretching of a clock signal, and subsequently reads out second monitoring data from the memory unit to follow the first monitoring data.

Abstract: An SMI task to be completed across multiple SMI events. An OS agent can be employed to determine a current load on a computing device. Based on the load, the OS agent can create an SMI message that specifies a maximum duration for an SMI event and that segments the SMI data for the SMI task. The OS agent can provide the SMI message to BIOS as part of requesting that the SMI task be performed. During the resulting SMI event, the BIOS can reassemble the segmented SMI data and then perform the SMI task. If this processing cannot be completed within the specified maximum duration for an SMI event, the BIOS can pause its processing and cause a subsequent SMI event to occur during which the processing can be resumed. In this way, the SMI task can be completed across multiple SMI events while ensuring that no single SMI event exceeds the specified maximum duration.

Abstract: It is made possible to consume current without adversely affecting the others. A cable is connected between a first device and a second device. A power line that supplies a current from the first device to the second device, and a current consumption unit that receives supply of a current from the first device through the power line, are included. A detection unit that detects that the second device is in the operating state, and a control unit that cancels a stop state of current consumption of the current consumption unit in response to the detection information, are further included.

Abstract: A method and computer system are disclosed for controlling a system boot of the computer system. Both involve determining that a chassis of the computer system was opened, determining whether the opening of the chassis was authorized, and controlling the system boot of the computer system based on whether the opening of the chassis was authorized.

Abstract: A method and system are provided for identification of constituent events in an event storm in operations management. The method includes: detecting an event storm by detecting an anomaly from a dynamic baseline range of expected event rates in a sample time period; and, when an event storm is detected, for each of a group of events grouped by an event category and occurring in a sample time period of an event storm, identifying the group of events as constituting part of the event storm if the rate of the event occurrences of the group in the sample time period is outside a threshold deviation from an average for that group.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

Abstract: Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.

Abstract: Methods for subscription handling and in-memory alignment of unsynchronized real-time data streams. A method (500) includes receiving a subscription (631) containing a signal identifier (626), and unsynchronized data (640). The method also includes detecting if the unsynchronized data for an actual time of measurement (ATM) timestamp (615) has completely arrived, and aligning (505) the unsynchronized data in predefined time slots (610). The method further includes filling (510) in data gaps (805) in the unsynchronized data for the ATM timestamp, and handling (520) the subscription using values (642) from the unsynchronized data for the ATM timestamp, and performing (515) memory protection when the subscription is handling inefficiently.

Abstract: There is a need to provide a semiconductor device that improves an interrupt capability of a virtual machine. A semiconductor device includes a memory to store a plurality of virtual machines and a virtual machine manager to manage the virtual machines and a CPU to perform the virtual machines and the virtual machine manager. The CPU causes an active virtual machine to perform an interrupt process when information (first information) about an interrupt-processing virtual machine is equal to information (second information) about the active virtual machine. When the first information differs from the second information, the CPU causes the virtual machine manager to stop the active virtual machine and operates the interrupt-processing virtual machine to perform an interrupt process.

Abstract: A monitoring system may include a sensor configured to be mounted inside a computer chassis and generate sensor signals representative of a temperature associated with at least one computer component inside the computer chassis. The monitoring system may also include a sensor processor configured to receive the sensor signals and determine the temperature associated with the at least one computer component based at least in part on the sensor signals. The sensor processor may also be configured to compare the determined temperature with an expected temperature associated with the at least one computer component, and initiate a response when the determined temperature differs from the expected temperature by an amount equal to or greater than a threshold amount.

Abstract: Technologies for processor core soft-offlining include a computing device having a processor with multiple processor cores. On boot, an operating system queries a firmware interface to retrieve a potential offline set of processor cores. The operating system prevents the processor cores of the potential offline set from receiving device interrupts. The computing device detects a platform management event from the firmware interface and, in response to the platform management event, queries the firmware interface to determine a requested offline set of processor cores. Each of the processor cores in the requested offline set is included in the potential offline set. The computing device brings the processor cores of the requested offline set into a low-power state, and then the computing device may start performing a platform management operation. The platform management event may include a memory hot-plug event or a specialized workload event. Other embodiments are described and claimed.

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract: A hypervisor configures a plurality of halt registers, wherein each halt register of the plurality of halt registers is associated with a corresponding latency threshold value, and provides the plurality of halt registers to a guest operating system of a virtual machine. The hypervisor detects that the guest operating system of the virtual machine has accessed a halt register of the plurality of halt registers, determines a latency threshold value associated with the halt register accessed by the guest operating system, and performs a halt operation for a virtual processor of the virtual machine in view of the latency threshold value.

Abstract: A system has data capture devices collecting data from different points in a network. The captured data is written to a data store and is directed to an output. The data from the different data capture devices can be delivered to a data analytics device. As long as the data analytics device is able to keep pace with the data that is directed to the output, that data is used by the analytics device. If the analytics device is not able to keep pace, the data written to the data store is retrieved and is used until the analytics device has caught up.

Abstract: A computing device features one or more hardware processors and a memory that is coupled to the one or more processors. The memory comprises software that is implemented with a security mechanism to protect the availability of a software component operating within a virtual machine, which is controlled by a guest operating system (OS) kernel. The software comprises a virtualization layer operating in a host mode, where the virtualization layer, when executed by the one or more hardware processors, is configured to send one or more virtual interrupts to the guest OS kernel of the virtual machine. A virtual interrupt causes an interrupt service routine within the guest OS kernel to perform a particular service that prevents a protected process (or protected software data structures) from being effected by malware.

Abstract: A system is arranged to receive data which is written to a data store by a writer. A controller is able to read data from the data store. That controller is able to control the rate at which data is read from the data store with respect to the rate at which data is written to the data store. A query function receives a stream of said data substantially in real time and when said stream of data is unavailable in real time, the query function is able to subsequently obtain that unavailable data from said data store.

Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.

Abstract: Address verification on a bus, the bus connecting a plurality of receiving bus nodes and one or more sending bus nodes, the bus providing communication among the bus nodes, including: receiving, by a receiving bus node over the bus, a parity signal and an address signal, the address signal identifying an address of a target receiving bus node; determining, by the receiving bus node, whether the address of the target receiving bus node matches an address of the receiving bus node; responsive to determining that the address of the target receiving bus node matches the address of the receiving bus node, determining, by the receiving bus node, whether the parity signal is an expected parity signal; and responsive to determining that the parity signal is not the expected parity signal, suppressing, by the receiving bus node, an acknowledgment of receipt of the address signal.

Abstract: A CPU control method and apparatus for improving application processing speed and power consumption are provided. An embodiment of the invention provides a method by which a CPU control apparatus controls a CPU, where the CPU control method includes: (a) measuring a reaction time of a user terminal for a running application; (b) computing a first predictive reaction time by stepwise changing a CPU frequency if the reaction time exceeds a preset threshold; (c) computing a second predictive reaction time by stepwise changing a processing weight of the application if the first predictive reaction time exceeds the preset threshold; and (d) repeating said step (c) if the second predictive reaction time exceeds the preset threshold.

Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.

Abstract: Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.

Abstract: A processing unit connected via a system fabric to multiple processing units calls a first single command in a bus protocol that allows sampling over the system fabric of the capability of snoopers distributed across the processing units to handle an interrupt. The processing unit, in response to detecting at least one first selection of snoopers with capability to handle the interrupt, calling a second single command in the bus protocol to poll the first selection of snoopers over the system fabric for an availability status. The processing unit, in response to detecting at least one second selection of snoopers respond with the available status indicating an availability to handle the interrupt, assigning a single snooper from among the second selection of snoopers to handle the interrupt by calling a third single command in the bus protocol.

Abstract: Methods and systems for refreshing an information handling system may include receiving a request for information, searching a group inventory for the information, and responding to the request with the information. The information may correspond to a configuration. The request may be received from a node in a group with a plurality of nodes. The information requested may correspond to an update to the configuration of the node. The group inventory may be sourced from the group. The information in the response may be based on finding a match in the group inventory.

Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The device may be configured according to a mode in which execution of a particular command is unauthorized while the device is configured in the mode. While in the mode, the device may authorize execution of the command to occur during the mod.

Abstract: Testing for pending external interruptions. A Test Pending External Interruption instruction tests for pending external interruptions. The test for pending external interruptions is based on one or more program-specified subclasses, regardless of whether the machine is enabled for those classes of interruption. The instruction provides an indication for those subclasses being tested of whether there are any pending external interruptions for those subclasses.

Abstract: Embodiments relate to configurable processor interrupts. An aspect includes sending, by an application to supervisor software in a computer system, a request, the request including a plurality of exception types to be handled by the application. Another aspect includes determining, by the supervisor software, a subset of the plurality of exception types for which to approve handling by the application. Yet another aspect includes sending a response from the supervisor software to the application notifying the application of the subset of exception types.

Abstract: A technique for handling queued interrupts includes accumulating, by an interrupt routing controller (IRC), respective backlog counts for respective event paths. The background counts track a number of events received but not delivered as interrupts to associated virtual processor (VP) threads upon which respective target interrupt handlers execute. An increment backlog (IB) message is received by the IRC. In response to receiving the IB message, the IRC determines an associated saturate value for an event path specified in the IB message. The IRC increments an associated backlog count for the event path specified in the IB message as long as the associated backlog count does not exceed the associated saturate value.

Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

Abstract: A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call.

Abstract: A computer device includes a processor, a circuit block capable of issuing an interrupt to the processor, and a cacheable memory configured to include a register that is mapped to the logic block for storing interrupt status information of the logic block.

Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.

Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.

Abstract: A task scheduling method is disclosed, where each processor core is programmed with a short list of priorities, each associated with a minimum response time. The minimum response times for adjacent priorities are different by at least one order of magnitude. Each process is assigned a priority based on how its expected response time compares with the minimum response times of the priorities. Lower priorities may be assigned a timeslice period that is a fraction of the minimum response time. Also disclosed is a task division method of dividing a complex task into multiple tasks is; one of the tasks is an input gathering authority task having a higher priority, and it provides inputs to the other tasks which have a lower priority. A method that permits orderly shutdown or scaling back of task activities in case of resource emergencies is also described.

Abstract: A computer device includes a processor, a circuit block capable of issuing an interrupt to the processor, and a cacheable memory configured to include a register that is mapped to the logic block for storing interrupt status information of the logic block.