Abstract: An interrupt controller has an interrupt register unit receiving a plurality of interrupt source signals, an interrupt detector coupled to the interrupt register unit, a counter unit coupled to the interrupt detector, wherein on the first occurrence of an interrupt source signal the counter unit defines a time window during which the interrupt register stores further interrupt source signals, and an interrupt request unit coupled to the counter unit for generating an interrupt request signal.

Abstract: A data processing system includes a first interrupt controller with an interrupt source interface, an interrupt controller interface, a prioritizer, and an interrupt controller output. The data processing system further includes a processing unit providing an interrupt controller interface. Interrupt requests generated by a first plurality of interrupt sources, a second selected interrupt request, a second priority signal, and a second interrupt source index signal generated by a second interrupt controller are received by the first interrupt controller. From the plurality of interrupt requests and the second selected interrupt request, a first single interrupt request is selected and transmitted to the processing unit along with a first priority signal, and a first index signal. The processing unit initiates an appropriate interrupt service routine on the basis of said first index signal.

Abstract: An electronic device, including: a storage device operable to store first priority data associated with a first signal, and second priority data associated with a second signal; and a processor operable to compare the first priority data and the second priority data, and when the second priority data is indicative of a higher priority than the first priority data, to use the second signal while suspending use of the first signal.

Abstract: Managing Message Signaled Interrupts (MSIs). For example, a method of managing MSI requests in a computing system may include receiving a plurality of MSI requests from one or more components of the computing system; directing data of the plurality of MSI requests to be stored sequentially, according to a First In First Out (FIFO) order, in successive entries of a FIFO structure defined in a main memory of the computing system; and directing a processor of the computing system to retrieve data of one or more of the plurality of MSI requests from the FIFO structure to be processed according to the FIFO order. Other embodiments are described and claimed.

Abstract: A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: A method for interrupt priority encoding and vectoring begins with reading pending interrupt bits from an interrupt status register. An entry in a table is located using the pending interrupt bits. The table has a plurality of vector entries for at least one high priority interrupt bit, and a single entry for at least one low priority interrupt bit. A vector address is fetched from the table and a branch is performed to the vector address. An alternate embodiment has high and low priority interrupt vector tables, where the high low priority interrupt vector table is used if no high priority interrupt is present.

Abstract: System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register.

Abstract: An interrupt control circuit includes: a section that generates an interrupt signal for requesting an interrupt in response to occurrence of a plurality of interrupt causes; a section that generates an interrupt vector signal for indicating a storing destination of an interrupt processing program corresponding any of the plurality of interrupt causes; a section that outputs the interrupt signal and the interrupt vector signal to an interrupt process executing circuit; and a section that controls the interrupt signal and an output value of the interrupt vector signal in sync with an interrupt acceptance signal input from the interrupt process executing circuit, the interrupt acceptance signal representing a condition in which an interrupt process is acceptable.

Abstract: A method of determining request transmission priority subject to request channel and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the request channel from which the received requests came have the priority right and whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in a plurality of execution environments (EE) selectively wherein a said execution environment (EE) is activated or suspended, a first configuration register (SCR) coupled to the processing circuit (2610) for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment (EE) is activated (EE_Active); and a second configuration register (SSM_FIQ_EE_y) for associating an identification of that execution environment (EE) with the same interrupt request, the processing circuit (2610) coupled (5910) to the second configuration register (SSM_FIQ_EE_y) to respond to the same interrupt request as a more urgent type of interrupt request when that execution environment (EE) is suspended (5920).

Abstract: A method for scheduling tasks in a computer operating system comprises a background task creating at least one registered service. The background task provides an execution presence and a data present to a registered service and ranks the registered services according to the requirements of each registered service. The background task also allocates an execution presence and a data presence according to each of the registered services such that each of the registered services is given an opportunity to be scheduled in the dedicated pre-assigned time slice.

Abstract: A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.

Abstract: The present invention provides a data processing system having excellent immediacy of interrupting process. Different interrupt request signals are supplied from a circuit module which can be commonly used by a plurality of central processing units to a plurality of interrupt controllers assigned to central processing units, respectively. In response to the input interrupt request signal, each of the interrupt controllers notifies the corresponding central processing unit of an interrupt. The circuit module selects an interrupt controller for supplying an interrupt request signal from the plural interrupt controllers. For example, the circuit module identifies a central processing unit which instructed a start request and supplies an interrupt request signal to an interrupt controller corresponding to the central processing unit. The burden of the interrupting process of the single central processing unit can be lessened.

Abstract: Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Abstract: An interrupt controller (1) is adapted to control the execution of interrupt requests (11, 12) of differing criticality by a processor (7) which is required to execute tasks (3, 17) of differing criticality under the control of a computer operating system (5); the interrupt controller being adapted to recognize critical (11) and non-critical (12) interrupt requests originating from different interrupt sources, and to recognize when the processor (7) is required to execute each of critical (3) and non-critical tasks (17); the interrupt controller being further adapted to pass critical interrupt requests (11) to the processor (7) for execution in preference to non-critical interrupt requests (12), to block non-critical interrupt requests (12) to the processor when they coexist with critical interrupt requests (11) or the processor (7) is required to execute critical tasks (3), and to pass non-critical interrupt requests (12) to the processor (7) when they do not coexist with any critical interrupt requests (11)

Abstract: An interrupt controller efficiently manages execution of tasks by a multiprocessor computing system. The interrupt controller has inputs for receiving service requests for invoking service routines. The service routines have higher priorities than the tasks executed on the processors. Associated with each processor is a register for storing the priority of the task executing on the processor. A comparator coupled to the processors determines the processor executing the task having a lower priority among the priorities of the tasks executing on the processors. For each service request received, a distributor generates an interrupt request for invoking the service routine of the service request on the processor with the lower priority. The register with the lower priority is set to the higher priority of the service routine in response to the interrupt request. For each processor, the interrupt controller has an output for transmitting the interrupt request to the processor.

Abstract: A method, system, and computer usable program product for a smart profiler are provided in the illustrative embodiments. An allowable number of interrupts for use by a profiler application is determined. A count number for a counter is determined. The counter is configured to count occurrences of an event in a data processing system up to the count number. An interrupt is raised when the counter has counted the occurrences of the event up to the count number. The interrupt is processed. The counting of occurrences of the event, raising the interrupt, and processing the interrupt are repeated for a predetermined time. A decision is made whether a total number of interrupts raised in the predetermined period differs from the allowable number. The count number of the counter is adjusted to cause the difference between the total number of interrupts in the predetermined period and the allowable number to decrease.

Abstract: A recording medium with a load distribution program recorded therein for causing a computer system to execute the following processing includes: acquiring, at every first timing, a processor load status and an input/output device load status; referencing, at every second timing, a load distribution policy and a load distribution executing condition for distributing interrupts and using the processor usage rate by the application job; determining whether a processor satisfying the load distribution initiating condition is present; referencing the processor load statuses and input/output device load statuses when a processor satisfying the load distribution initiating condition is present; calculating processor usage rates of all input/output devices interrupting the processor; determining a processor and an input/output device satisfying the load distribution executing condition based on the calculated processor usage rate; and changing the interrupt destination processor of the input/output device satisfying

Abstract: A method for scheduling tasks in a computer operating system comprises a background task creating at least one registered service. The background task provides an execution presence and a data present to a registered service and ranks the registered services according to the requirements of each registered service. The background task also allocates an execution presence and a data presence according to each of the registered services such that each of the registered services is given an opportunity to be scheduled in the dedicated pre-assigned time slice.

Abstract: A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive.

Abstract: Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses the flag registers in a predetermined priority order, using the flag register addresses. Upon detecting that one or more of the flags of a flag register are activated, the flag scan controller causes a doorbell command to be generated. The doorbell command includes the flag register address and the corresponding flags. A system processor receives the doorbell command and services the activated flags. Once the activated flags are serviced, the system processor performs one or more software write operations to clear the flags within the system device. The system processor can simultaneously service multiple flags. The system processor can also simultaneously clear multiple flags.

Abstract: A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive.

Abstract: In one embodiment, a method includes transitioning control to a virtual machine (VM) upon receiving a request from a virtual machine monitor (VMM), determining that the request to transition control is associated with a request to be informed of an open event window, performing an event window check to determine whether an even window of the VM is open, and transitioning control to the VMM if the event window check indicates that the event window of the VM is open.

Abstract: A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24. The interrupt controller is responsive to save state data when interrupt processing is commenced by pre-emption of existing processing, whether that be background processing or another interrupt. If a further interrupt is required to be executed immediately after the interrupt which triggered the pre-emption, then the speed with which interrupt processing can be started is advantageously increased if that subsequent interrupt processing is performed without restoring and then resaving the original state data. The interrupts in this arrangement can be considered to be chained together without intervening save and restore operations.

Abstract: A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.

Abstract: A method and apparatus for generating an interrupt vector associated with either core (internal) generated or off-core (external) generated interrupts is provided. The apparatus includes a number of programmable interrupt priority level fields for storing priority levels for the core generated interrupts, and for the externally generated interrupts, if desired. The apparatus further includes a programmable offset register for storing an offset to be used in calculating the interrupt vector. The apparatus further includes a priority encoder that sorts all of the received interrupts, whether on-core or off-core, according to their priority, utilizing the programmed interrupt priority levels. The priority encoder provides an indication of the received interrupt with the highest priority to a vector generator. The vector generator receives the indication, and calculates an interrupt vector utilizing the programmed offset.

Abstract: A method and a system for automatically diagnosing disability of computer peripheral devices are provided. In the method, a set of interrupt configuration data relevant to a disabled PCI peripheral device, including relevant setting values of a hardware IRQ routing, is input and compared with a PCI IRQ routing table pre-stored in a boot control unit. Then, whether errors exist in the current setting values of the relevant control parameters and flags of all the relevant control units are automatically checked. If an incorrect setting value is found, a corresponding diagnosis result message is displayed for informing the user to make a modification. Therefore, users can know the reasons that cause the computer peripheral device to operate abnormally and make the modification quickly and effectively.

Abstract: An efficient interrupt system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payload communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The devices are configured with messages that each targets a processor. Upon receiving a command to perform an operation, the device may receive an indication of a preferred message to use to interrupt a processor upon completion of that operation. The efficiency with which each interrupt is handled and the overall efficiency of operation of the computer is increased by defining messages for the devices within the computer so that each device contains messages targeting processors distributed across groups of processors, with each group representing processors in close proximity. In selecting target processors for messages, processors are selected to spread processing across the processor groups and across processors within each group.

Abstract: An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in a plurality of execution environments (EE) selectively wherein a said execution environment (EE) is activated or suspended, a first configuration register (SCR) coupled to the processing circuit (2610) for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment (EE) is activated (EE_Active); and a second configuration register (SSM_FIQ_EE_y) for associating an identification of that execution environment (EE) with the same interrupt request, the processing circuit (2610) coupled (5910) to the second configuration register (SSM_FIQ_EE_y) to respond to the same interrupt request as a more urgent type of interrupt request when that execution environment (EE) is suspended (5920).

Abstract: A system includes a plurality of partitions having respective operating systems, and a resource shared by the partitions. The resource has plural segments, where a first one of the segments is accessed to invoke a first interrupt. An operating system of a first one of the plurality of partitions invokes, in response to the first interrupt, a routine to cause generation of a second interrupt to a second one of the plurality of partitions.

Abstract: Various operations are disclosed for improving the operational efficiency of interrupt handling in a virtualized environment. A virtualized interrupt controller may obviate the need for an explicit end-of-interrupt command by providing an automatic EOI capability even when a physical interrupt controller offers no such mechanism. The use of a message pending bit for inter-partition communications facilitates avoiding an EOI command of inter-processor interrupts used in inter-partition communications whenever no further messages are cued for a particular message slot. A virtualized interrupt controller facilitates the selective EOI of an interrupt even when it is not the highest priority in-service interrupt irrespective of whether a physical interrupt controller provides such functionality.

Abstract: An interrupt controller superior in maintenance performance and expandability. An interrupt controller 10 comprises a queue circuit 11 that holds channel numbers corresponding to interrupt inputs in the order of priority levels, and a queue control circuit 12 that changes the order of the channels held in the queue circuit 11 according to a new order of the priority levels when a priority level that corresponds to any channel number is changed. The order of the channel numbers in the queue circuit 11 is changed at a time of setting the priority levels unrelated to interrupt inputs. In order to select an interrupt to be notified to a CPU 20, an interrupt factor selection circuit 15 checks whether or not each channel number held in the queue circuit 11 has an interrupt input in turn from the head of the queue.

Abstract: Some embodiments include apparatus and method to allocate ports of host bus adapters in computer systems to multiple operating systems in the computer systems. Other embodiments are described and claimed.

Abstract: A storage apparatus and method are provided. The storage apparatus including includes a basic storage device having a control unit and an add-on storage device configured to be connected to the basic storage device. The add-on storage device including a first request receiving unit receiving a first operation stop request output from the basic storage device to the add-on storage device second request receiving unit receiving a second operation stop request different from the first operation stop request, communication monitoring unit monitoring communication from the basic storage device, and operation stop processing unit performing processing for stopping the operation of the add-on storage device. The operation stop processing unit determines the validity of the second operation stop request on the basis of a monitoring result obtained by the communication monitoring unit, and stops the operation of the add-on storage device.

Abstract: An apparatus and method for interrupt source signal allocation is provided. An interrupt controller may include an interrupt source allocation unit, an interrupt pending register, a control register, a priority register, and/or an interrupt request signal generator. The interrupt source allocation unit may output one or more interrupt source signals based on one or more priorities, and may allow a user to move an individual interrupt source signal without moving other interrupt source signals. The interrupt pending register may set bits in one or more registers corresponding to the interrupt source signals. The control register may control and transmit the interrupt source signals corresponding to the set bits. The priority register may determine the priorities of the interrupt source signals. The interrupt request signal generator may output an interrupt request signal in response to one or more interrupt source signals received from the priority register.

Abstract: A DMA interrupt coalescer processes interrupts received from a DMA channel of a DMA controller by transmitting an interrupt request to an interrupt controller if a coalescing condition is satisfied after receiving one or more delayable interrupts, or transmitting the interrupt request regardless of the satisfaction of the coalescing condition if a non-delayable interrupt is received. The coalescing condition is satisfied if a non-zero period of time has transpired since a first of the one or more delayable interrupts was received, or if a number of the one or more delayable interrupts received exceeds a programmed value.

Abstract: In a device that can execute multiple media applications, but only one at a time, a media server coordinates among applications, but neither the media server nor the individual applications maintain rules regarding all of the different applications. Each connection used by an application is assigned a priority and communicates that priority to the media server when the connection is established. When an application requests to begin playback, the request is granted if no other application is playing, or if another application is playing on a connection having a priority at most equal to that of the connection used by the requesting application, but is denied if the connection already in use has a higher priority. Resumption of an application that was interrupted by another application on a connection with higher priority is determined by the interrupted application after the interruption ends, based on information communicated by the media server.

Abstract: A processor context stored in a stack area at a time of an interrupt occurrence is saved in a context saving area of an ICB corresponding to an ISR that is interrupted. The ISR corresponding to the interrupt is set to an execution-waiting state. An ICB having a highest priority from among the ICBs that are set to the execution-waiting state is selected. A processor context saved in a context saving area of the selected ICB is stored in the stack area. An ISR corresponding to an ICB selected by an interrupt return command is executed.

Abstract: A method is disclosed to control access to stored information. The method supplies a control unit in communication with a computing device and in communication with stored information. If the computing device requests access to that stored information, the method determines if access to the stored information is available. When access to the stored information becomes available, then the method reserves a communication pathway interconnecting the control unit and the requesting computing device, thereby disallowing the sending of non-MPLF unsolicited status via that reserved communication pathway, and provides a message to the computing device, using that reserved communication pathway, granting access to the stored information.

Abstract: A method for dynamically arranging interrupt pins is provided, which is suitable for arranging a plurality of interrupt pins of a control chip. In this method, a number of interrupts sent from each of a plurality of device paths in a unit time is detected. The device paths are sorted according to the interrupt numbers thereof. Then, from the one in the head of the sequence, the devices paths are arranged to the interrupt pins. Herein, when arranging a device path, an interrupt checking number required to check the device path sending the interrupt every time an interrupt is produced in each of the interrupt pins is calculated. Then, when arranging the next device path, the device path is arranged to the interrupt pin with the least interrupt checking number.

Abstract: A method and system is provided for detecting excessive interrupt processing for a processor. The method includes the operation of defining an interrupt processing period during which measuring of interrupts for a processor takes place. The amounts of time being spent by the processor in an interrupt context can then be measured during the interrupt processing period. A further operation is detecting an interrupt storm occurring for the processor based on the amounts of time spent by the processor in interrupt context during the interrupt processing period.

Abstract: An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.

Abstract: A microcomputer includes a plurality of processing circuits for executing a plurality of interrupt processes each corresponding to one of a first plurality of causes) a cause register circuit for representing whether each of the first plurality of causes has been solved or unsolved, a processing circuit selection register for defining a plurality of correspondences each between one of the first plurality of causes and one of the plurality of processing circuits responsible to execute one the interrupt processes corresponding to the one of the first plurality of causes, and for outputting, in response to occurrence of one of the causes, to the plurality of processing circuits an interrupt signal representing that one of the interrupt processes should be executed, a vector signal indicating an area in which a content of the one of the interrupt processes corresponding to the one of the causes, and a first selection signal representing which one of the processing circuits should execute the one of the interrupt

Abstract: One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt mask value is written to the TPR. In addition, the interrupt mask value is also written into a shadow copy of the TPR. The shadow copy is written each time that the TPR is written. Another embodiment disclosed relates to a method of reducing a latency to read a TPR of an IPF type microprocessor. When a command is received to read an interrupt mask value from the TPR, the interrupt mask value is read from the shadow copy at a memory location, instead of from the task priority register itself.

Abstract: A method for processing an interrupt signal within a microprocessor based system is described. The method includes storing a received interrupt signal within an interrupt cause register of an interrupt controller, outputting an interrupt command from the interrupt controller to an interrupt collector, asserting an interrupt signal to the microprocessor from the interrupt collector, and shifting the cause value field into a cause array. The interrupt command include an identifier field, a cause register ID field, and a cause value field, and content of the cause value field is based on a content of the interrupt cause register. The interrupt signal is asserted based on receipt of the identifier field and cause register ID field by the interrupt collector, and the shifting of the cause value field into a cause array within the interrupt collector occurs while the microprocessor services the receipt of the identifier field and cause register ID field from the interrupt collector.

Abstract: An interrupt controller (1) is adapted to control the execution of interrupt requests (11, 12) of differing criticality by a processor (7) which is required to execute tasks (3, 17) of differing criticality under the control of a computer operating system (5); the interrupt controller being adapted to recognize critical (11) and non-critical (12) interrupt requests originating from different interrupt sources, and to recognize when the processor (7) is required to execute each of critical (3) and non-critical tasks (17); the interrupt controller being further adapted to pass critical interrupt requests (11) to the processor (7) for execution in preference to non-critical interrupt requests (12), to block non-critical interrupt requests (12) to the processor when they coexist with critical interrupt requests (11) or the processor (7) is required to execute critical tasks (3), and to pass non-critical interrupt requests (12) to the processor (7) when they do not coexist with any critical interrupt requests (11)

Abstract: The present invention relates to a data processing system comprising a first interrupt controller with an interrupt source interface, an interrupt controller interface, prioritizing means, and an interrupt controller output. The Data processing system further comprises a processing unit providing an interrupt controller interface. The invention also is related to a method for handling interrupt requests. Accordingly, interrupt requests generated by a first plurality of interrupt sources, a second selected interrupt request, a second priority signal, and a second interrupt source index signal generated by a second interrupt controller are received by the first interrupt controller Among said plurality of interrupt requests and said second selected interrupt request a first single interrupt request is selected and transmitted along with a first priority signal, and a first index signal to the processing unit; which initiates an appropriate interrupt service routine on the basis of said first index signal.

Abstract: A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the

Abstract: A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies between nodes are made known and predictable greatly simplify the task of coordinating quiesce responses within the system. When latencies are not fixed and topologies such as open or closed bus architectures are be used a more dynamic approach is required to ensure system serialization. Adaptive quiesce logic on each node's SCE can dynamically identify the role of the node within the system and automatically configure itself to guarantee that no enabled processor within the entire system receives a quiesce indication before all processors have reached the stopped state. This is also true for systems where nodes are being concurrently added or removed during system operation. Bus states process quiesce requests.

Abstract: The invention discloses a computing system such as a computer, a Personal Digital Assistant, or a mobile phone, being connected both to an internal network and an external network and being able to quickly and safely switch therebetween without being shut down while ensuring a physical separation between the two networks. When a user inputs a request of switching, a switching unit will set a trigger thereof and generate a consequent non-maskable interrupt to CPU. After receives the NMI, the CPU controls the switching unit to run a switch program kept therein to back up a current status of the system. Then the switch program backs up a current status, controls the switching unit to interrupt all serving programs and loads the other status other than the current status to the computing system, and finally control the switching unit to reset the trigger.