Abstract: A method and a device for balancing an interrupt load of a multicore processor are provided, the multicore processor includes multiple cores and an interrupt controller for controlling interrupt handling of the cores, characterized in that the method includes: pre-configuring a default processing core and a scheduling core group corresponding to an interrupt device, wherein the default processing core is one core in the scheduling core group; configuring the interrupt controller to route the interrupt device to the corresponding default processing core; and controlling the interrupt controller to route the interrupt device to one or multiple cores in the scheduling core group to which the default processing core belongs, when the number of interrupts of the interrupt device exceeds an interrupt threshold or a processing amount of the default processing core exceeds an interrupt load.

Abstract: A method and apparatus for balancing power savings and performance in handling interrupts is herein described. When an amount of interrupt activity is above a threshold, a performance mode of interrupt handling is selected. During the performance mode, interrupts and/or interrupt sources are distributed among multiple physical sockets, i.e. multiple physical processors. However, if the interrupt activity is below a threshold for a number of periods, which denotes low interrupt activity, then a power save mode is selected. Here, interrupts and/or sources are primarily assigned to a single processor to allow other physical processors to save power. Furthermore, after interrupts are assigned to a physical processor, the interrupts may be further distributed among cache domains of the processor. In addition, high activity classes, interrupt sources, interrupts, or categories may be further assigned to specific processing elements for servicing.

Abstract: Methods for processing more securely are disclosed. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these mechanisms effectively reduces APIC attacks and increases the security of proprietary, confidential or otherwise secure data stored in SMRAM.

Abstract: Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.

Abstract: Certain aspects of a method and system for processing status blocks based on interrupt mapping may be disclosed. Exemplary aspects of the method may include determining whether a particular status block has been processed by at least one CPU based on comparing a value of a first register with a value of a second register, wherein the first register may comprise a running index value of at least one client segment within the particular status block and the second register may comprise a current running index value of at least one client segment. An interrupt may be generated, if the value of the first register is not equal to the value of the second register. The particular status block may be processed by at least one CPU based on the generated interrupt.

Abstract: An energy-saving circuit applies to a peripheral device for connection to a data bus of a host system. The energy-saving circuit includes a monitoring circuit for monitoring a communication via the data bus, a holding circuit for holding a connection state of the peripheral device, at least one switching element for interrupting a supply voltage for the peripheral device, and a control circuit. The control circuit is set up to recognize by means of the monitoring circuit the beginning of an idle state of the data bus, to hold the connection state of the peripheral device by activation of the holding circuit upon recognition of the idle state, and to interrupt the feeding of a supply voltage for the peripheral device by opening the at least one switching element.

Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.

Abstract: A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.

Abstract: In one embodiment, a system for controlling a plurality of devices having at least two operating modes comprises a first software operating layer configured to control the operation of at least one of the devices in a first operational mode and a second software operating layer configured to control the operation of at least one of the devices in a second operational mode. In another embodiment, a control system for controlling a plurality of devices connected by a communications network comprises a user interface configured to receive the selection of a cycle of operation; a first system element isolated from the network and configured to implement the selected cycle of operation to define a first control state; and a second system element exposed to the network and configured to implement the selected cycle of operation to define a second control state.

Abstract: A method for distributing interrupt load to processors in a multiprocessor system. The method includes executing current transactions with multiple processors (104, 106, 108) where each transaction is associated with one of the processors, generating an interrupt request, estimating a transaction completion time for each processor and directing the interrupt request (102) to the processor having the least estimated transaction completion time. Estimating a transaction completion time occurs periodically so that information pertaining to transaction times is stored and continually updated. According to one aspect of the invention, the step of estimating a transaction completion time for each processor occurs when the interrupt request is generated. According to another aspect of the invention, the step of communicating the interrupt request includes communicating the interrupt request to an intermediary processor prior to estimating the transaction completion time.

Abstract: A method includes recording a user-level interrupt as undeliverable in a mailbox at least partially based on an interrupt domain identifier and an interrupt recipient identifier included in a user-level interrupt message associated with the user-level interrupt. The recording is at least partially based on an indication that the user-level interrupt is undeliverable to a recipient application thread executing on a processor core of a plurality of processor cores in a multi-core system.

Abstract: A method includes delivering a user-level interrupt message indicative of a user-level interrupt to one or more recipients according to a user-level interrupt delivery configuration selected from a plurality of user-level interrupt delivery configurations. The one or more recipients correspond to one or more application threads executing on one or more processor cores of a plurality of processor cores in a multi-core system. A method includes generating an indicator of a user-level interrupt being undeliverable to one or more intended recipients of a user-level interrupt message according to a failed delivery notification mode configuration. The user-level interrupt may be issued by an application thread executing on a first processor core of a plurality of processor cores in a multi-core system.

Abstract: Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode in which the plurality of processing elements share a single task to process the single task in parallel. The processor may delay entering the parallel processing mode based on the prediction. The processor may reduce overhead that stores a context of the plurality of processing elements when the interrupt occurs.

Abstract: An external device access apparatus according to the present invention includes: an address control unit that accepts a prefetch request and a prefetch data readout request from a master and performs a prefetch operation and a prefetch data readout operation; a readout data storage unit that stores data read out through the prefetch operation; a storage operation status holding unit that holds a prefetch operation status indicating whether or not the prefetch operation has been completed; and an acceptance signal generation unit that outputs, to the master, an acceptance signal indicating that the prefetch data readout request has been accepted from the master. First information indicating a status of the prefetch operation is outputted to the master based on the prefetch operation status.

Abstract: A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests.

Abstract: A technique is disclosed for generating a plurality of output frames based on a single input frame. An input interface is configured to receive at least a portion of the input frame. An output controller is configured to receive, for each of the plurality of output frames, a new header, and combine each new header with at least a portion of the input frame. An output frame may be generated for which no corresponding input frame exists. An input interface is configured to receive an indication that the output frame should be generated. An output controller is configured to receive a generated header and combine the generated header with a dummy payload to form the output frame.

Abstract: A method for configuration of a program with a plurality of configuration variables to operate on a computer system that includes obtaining a plurality of priority semantics for the plurality of configuration variables, wherein the plurality of priority semantics are heterogeneous, assigning a value for each of the plurality of configuration variables based on the plurality of priority semantics, and configuring the program using the value to operate on the computer system.

Abstract: In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management Interrupt (SMI) interface to the firmware. An SMI function call in SMI format is generated and sent to an SMI Interface Wrapper module between the operating system and the firmware. The SMI function call is received over the SMI interface at the SMI Interface Wrapper. In the SMI Interface Wrapper, function data from the SMI function call is extracted to provide function call data. A 16-bit function call with the function call data is generated by the SMI Interface Wrapper and passed to the firmware.

Abstract: In a computer system, a method of controlling coalescence of interrupts includes dynamically basing a current level of interrupt coalescing upon a determination of outstanding input/output (I/O) commands for which corresponding I/O completions have not been received. Deliveries of interrupts are executed on the basis of the current level and in an absence of enabling timing-triggered delivery of an interrupt.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: In process control based on partition setting which is a process corresponding to a plurality of operating systems (OSs), a configuration is implemented in which an interrupt request can be processed efficiently. In process control for switching processes which are based on the plurality of OSs, it is configured to set an interrupt processing partition as an interrupt processing execution period corresponding to an interrupt processing request so as to coincide with a pre-set partition switching timing. Further, a processing schedule is set, taking a maximum allowable delay time, a minimum allowable delay time into account. As a result of the present configuration, an increment in the number of partition switching processes can be kept to 1, and thus efficient data processing becomes possible.

Abstract: A method, processor, and system are disclosed. In one embodiment method includes a first processor core among several processor cores entering into a system management mode. At least one of the other additional processor cores apart from the first processor core remain operational and do not enter the system management mode. Then, once in the system management mode, the first processor core responds to an inter-processor interrupt.

Abstract: In one embodiment, a system for controlling a plurality of devices having at least two operating modes comprises a first software operating layer configured to control the operation of at least one of the devices in a first operational mode and a second software operating layer configured to control the operation of at least one of the devices in a second operational mode. In another embodiment, a control system for controlling a plurality of devices connected by a communications network comprises a user interface configured to receive the selection of a cycle of operation; a first system element isolated from the network and configured to implement the selected cycle of operation to define a first control state; and a second system element exposed to the network and configured to implement the selected cycle of operation to define a second control state.

Abstract: Embodiments of the present disclosure disclose a method for controlling power consumption of an embedded system. The method obtains a data transmission index that is between a bus module and a bus, compares the obtained data transmission index with a preset numeric value range, and adjusts an operation frequency or an operation voltage of the bus module when the data transmission index exceeds the preset numeric value range. Embodiments of the present disclosure further provide a system and a relevant apparatus for controlling power consumption of the embedded system. In comparison with the conventional art, embodiments of the present disclosure effectively monitor the load of the bus module, and adjust the operation parameters of the module according to the monitoring result to enable the module to operate under proper operation parameters and to thereby reduce unnecessary power consumption.

Abstract: A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering two or more processor cores from a plurality of processor cores to form a group of sequestered processor cores for handling the management interrupt. Generated management interrupts are directed to the group of sequestered processor cores and not to non-sequestered processor cores. At least one of the sequestered processor cores handles the management interrupt without disrupting the current operation of the non-sequestered processor cores.

Abstract: A multiprocessor system with multiple watchdog timers, the timers causing all the processors in the system to concurrently process a common interrupt signal asserted by any of the watchdog timers timing out. The processors, in response to the common interrupt signal, store data residing in their local memories into a memory common to all the processors. The stored data is then stored in a permanent storage device for later analysis. Thereafter, all of the processors are reset.

Abstract: A system and method for transitions a computing system between operating modes that have different power consumption characteristics. When a system management unit (SMU) determines that the computing system is in a low activity state, the SMU transitions the central processing unit (CPU) into a low power operating mode after the CPU stores critical operating state of the CPU in a memory. The SMU then intercepts and processes interrupts intended for the CPU, modifying a copy of the critical operating state. This effectively extends the time during which the CPU stays in lower power mode. When the SMU determines that the computing system exits a low activity state, the copy of the critical operating state is stored in the memory and the SMU transitions the CPU into a high power operating mode using the modified critical operating state.

Abstract: In one embodiment, an interrupt acceptance control circuit is provided. The interrupt acceptance control circuit may monitor one or more guest interrupt controllers in a system in response to an IPI (or device interrupt) issued in a guest, to determine if each targeted vCPU in the guest has accepted the interrupt. If not, the interrupt acceptance control circuit may communicate the lack of acceptance to the VMM, in one embodiment. The VMM may attempt to schedule the vCPUs that have not accepted the interrupt, for example.

Abstract: An information processing device of the present invention comprises a main CPU capable of taking at least two states which are an operating state and a sleeping state, a sub-CPU having power consumption lower than that of the main CPU and capable of taking at least two states which are an operating state and a sleeping state, and a process request determining section for determining which of the main CPU and the sub-CPU is caused to execute a process related to a request from a peripheral device. The process request determining section determines whether the main CPU is in the sleeping state or the operating state, and when the main CPU is in the sleeping state, determines whether or not the sub-CPU can be caused to execute the process, and when the main CPU is in the operating state, determines whether or not the main CPU can be caused to execute the process, and depending on a result of the determination, causes the main CPU or the sub-CPU to execute the process.

Abstract: This disclosure describes a processor system that allows non-real time code to execute normally, while permitting a real time interrupt in hardware or software to execute with minimal added latency.

Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: Input/output (I/O) interrupts are avoided at the completion of I/O operations. A task requests (implicitly or explicitly) an I/O operation, and processing of the task is suspended awaiting completion of the I/O operation. At the completion of the I/O operation, instead of an I/O interrupt, an indicator associated with the task is set. Then, when the task once again becomes the current task to be executed, the indicator is checked. If the indicator indicates the I/O operation is complete, execution of the task is resumed.

Abstract: Approaches that allow the context of an SMI task to be saved between SMIs. Upon entering an SMI handler for a task, a new task context stack is created. Thereafter, the SMI handler uses the task context, leaving the original stack unchanged. When the time limit for a single SMI is almost reached, the CPU is directed back to the original stack, and the task context stack persists in memory and retains the context of the task in hand. The soft SMI exits with an indication to signify that a new SMI should be invoked to continue processing. The entity that caused the first soft SMI then invokes another, passing in an indication to signify that this is a continuation of the prior task. On entering the SMI handler, the handler notes the request for continuation, switches to the saved task context stack and continues processing where it left off.

Abstract: A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state.

Abstract: System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register.

Abstract: In a device control apparatus, a processor that operates according to software, an OS storage unit stores Operating Systems that operate on the processor, and a storage unit stores privileged software which operates on the processor. The privileged software calls one of the Operating Systems when the processor receives an interrupt from a device, and the Operating System controls the device. Furthermore, a detecting unit detects an interrupt to the processor, a judging unit judges whether the Operating System has called the privileged software from the storage unit in a first predetermined time from detection of the interrupt, and a resetting unit resets the processor when the judging unit judges that the Operating Systcm 9em has not called the privileged software from the storage unit.

Abstract: Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode in which the plurality of processing elements share a single task to process the single task in parallel. The processor may delay entering the parallel processing mode based on the prediction. The processor may reduce overhead that stores a context of the plurality of processing elements when the interrupt occurs.

Abstract: A data processing apparatus comprises a processing unit which is responsive to a plurality of interrupt signals to carry out a corresponding interrupt routine. On receipt of an interrupt signal, the processing unit stores data values from a plurality of registers onto a data stack and carries out the corresponding interrupt routine. Thereafter the processor returns the data values from the data stack to the registers and carries on the processing it was performing when the interrupt was received. If a higher priority interrupt is received whilst the processor is transferring register values to or from the data stack, that transferral is abandoned and the processing unit immediately begins transferring data values from the registers to the data stack in response to the higher priority interrupt.

Abstract: A method, information processing system, and computer readable medium, mitigate processor assignments. A first processor in a plurality of processors is assigned to a first communication port in a plurality of communication ports. An interrupt associated with the first communication port is generated. An assignment of a processor other than the first processor to handle the interrupt is inhibited.

Abstract: A multi-core processor which includes a plurality of processor dies. The multi-core processor has a first processor core which processes a first task and a second processor core which processes a second task. The first processor core and the second processor core are formed on each of the plurality of processor dies. When the first processor core makes a request for the second task processing in processing the first task, information on the second task is stored in a memory area used by the first processor core and interrupt notification is made to each of the second processor cores provided respectively on the plurality of processor dies. Each of the second processor cores having received the interrupt notification accesses the memory area used by the first processor core provided on the same processor die as the processor die on which the second processor core is provided.

Abstract: Disclosed herein is a system and method of operating a processor before and after a reset has been asserted. Prior to a reset being asserted the processor operates in one of a plurality of states wherein primary code may be executed by the processor depending on said state. Upon a reset being asserted the processor begins executing code for a reset routine. The processor also executes a process such that the processor operates in the same state it was in prior to the reset upon the reset no longer being asserted.

Abstract: Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Abstract: An interrupt controller (1) is adapted to control the execution of interrupt requests (11, 12) of differing criticality by a processor (7) which is required to execute tasks (3, 17) of differing criticality under the control of a computer operating system (5); the interrupt controller being adapted to recognize critical (11) and non-critical (12) interrupt requests originating from different interrupt sources, and to recognize when the processor (7) is required to execute each of critical (3) and non-critical tasks (17); the interrupt controller being further adapted to pass critical interrupt requests (11) to the processor (7) for execution in preference to non-critical interrupt requests (12), to block non-critical interrupt requests (12) to the processor when they coexist with critical interrupt requests (11) or the processor (7) is required to execute critical tasks (3), and to pass non-critical interrupt requests (12) to the processor (7) when they do not coexist with any critical interrupt requests (11)

Abstract: A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.

Abstract: An interrupt control unit provides controls on an interrupt from an accelerator to a CPU based on a packet transmitted to or received from a controlled object. The interrupt control unit includes: a storage part for storing therein an interrupt control timing table in which a condition of switching a mode of the interrupt control is described; and an interrupt control mode switching part for switching the mode of the interrupt control to the CPU between a permission mode and a mask mode, based on the interrupt control timing table in the storage part.

Abstract: A recording medium with a load distribution program recorded therein for causing a computer system to execute the following processing includes: acquiring, at every first timing, a processor load status and an input/output device load status; referencing, at every second timing, a load distribution policy and a load distribution executing condition for distributing interrupts and using the processor usage rate by the application job; determining whether a processor satisfying the load distribution initiating condition is present; referencing the processor load statuses and input/output device load statuses when a processor satisfying the load distribution initiating condition is present; calculating processor usage rates of all input/output devices interrupting the processor; determining a processor and an input/output device satisfying the load distribution executing condition based on the calculated processor usage rate; and changing the interrupt destination processor of the input/output device satisfying

Abstract: A multitasking processor and a task switching method thereof are provided. The task switching method includes following steps. A first task is executed by the multitasking processor, wherein the first task contains a plurality of switching-point instructions. An interrupt event occurs. Accordingly, the multitasking processor temporarily stops executing the first task and starts to execute a second task. The multitasking processor executes a handling process of the interrupt event and sets a switching flag. After finishing the handling process of the interrupt event, the multitasking processor does not perform task switching but continues to execute the first task, and the multitasking processor only performs task switching to execute the second task when it reaches a switching-point instruction in the first task.

Abstract: The present invention provides a method for cooling a CPU. The method includes the steps of: setting a passive cooling mode; setting a critical temperature and a reference temperature that is lower than the critical temperature; setting a plurality of temperature intervals between the reference temperature and the critical temperature; predetermining a duty cycle corresponding to each temperature interval; detecting a current temperature of the CPU; comparing the current temperature with the reference temperature and the critical temperature; entering into the passive cooling mode if the current temperature is between the reference temperature and the critical temperature; confirming which temperature interval the current temperature falls in; confirming a corresponding predetermined duty cycle according to the temperature interval; and switching the CPU between a working status and a sleeping status according to the confirmed predetermined duty cycle. A related system is also disclosed.

Abstract: A data processing system supporting one or more virtual processing apparatuses is provided with external interrupt interface hardware 26 and virtual interface hardware 28. Hypervisor software responds to an interrupt received by the external interrupt interface hardware 26 to write data characterising that interrupt into list registers 18 of the virtual interface hardware 28. A guest operating system for the virtual machine of the virtual data processing apparatus being emulated may then read data from the virtual interface hardware 28 characterising the interrupt to be processed by that virtual machine. The virtual machine and the guest operating system interact with the virtual interface hardware 28 as if it were external interface hardware. The hypervisor software is responsible for maintaining the data within the virtual interface hardware 28 to properly reflect queued interrupts as received by the external interface 26.