Abstract: A method includes receiving a request for an allocation of memory resources based on quality of service (QoS) parameters. The method further includes provisioning, via a QoS manager component, a plurality of physical functions to provide the requested allocation of resources. At least two of the plurality of physical functions can be provided to meet a QoS criteria.

Abstract: The present disclosure provides a multipath device working system, including a processor and a touch display module, a control management module, a wireless communication module, a USB module, a microphone, and a loudspeaker that are respectively connected to the processor. The touch display module is configured to display a user operation interface and obtain a control instruction from a user. Both the wireless communication module and the USB module are configured to perform data transmission between the multipath device working system and an external communication device. The control management module is configured to manage a plurality of software communication terminals on the external communication device. The processor is configured to separately perform data processing on data transmitted by the touch display module, the control management module, the wireless communication module, the USB module, the microphone, and the loudspeaker.

Abstract: A computer program component configured to collect configuration item data from information technology resources of an air-gapped network for an information technology configuration management database is provided. Configuration item data collected from the information technology resources of the air-gapped network is obtained using the provided computer program component, wherein the obtained configuration item data is physically transferred between a device within the air-gapped network and a device outside the air-gapped network at least in part via a portable physical storage medium, and the collected configuration item data has been reviewed and filtered within the air-gapped network prior to being physically transferred via the portable physical storage medium. The obtained configuration item data is imported to the information technology configuration management database outside the air-gapped network.

Abstract: A system including a fabric manager, a memory mapper, and a switch is described. The memory mapper receives and stores mapping information from the fabric manager that maps memory locations in a plurality of hosts to corresponding memory locations in a plurality of physical devices. The switch receives at least a portion of the mapping information from the memory mapper, receives a request from a host, and accesses memory that is identified by the request on a physical device of the plurality of physical devices.

Abstract: An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.

Abstract: Systems and methods for memory management for virtual machines. An example method may include receiving, by a host computing system, a memory access request initiated by a peripheral component interconnect (PCI) device, wherein the memory access request comprises a memory address and an address translation flag specifying an address space associated with the memory address; and responsive to determining that the address translation flag is set to a first value indicating a host address space, causing a host system input/output memory management unit (IOMMU) to pass-through the memory access request.

Abstract: A data storage system includes: a plurality of data storage devices; a motherboard containing a baseboard management controller (BMC); and a network switch configured to route network traffic to the plurality of data storage devices. The BMC is configured to identify a group of data storage devices among the plurality of data storage devices based on device-specific information received from the plurality of data storage devices and send identifiers of the group of data storage devices to a querying party.

Abstract: The present invention provides a control method of a server, wherein the control method includes the steps of: periodically controlling a first register and a second register of a first node to have a first value and a second value, respectively; periodically controlling a third register and a fourth register of a second node to have a third value and a fourth value, respectively; controlling the first register and the fourth register to synchronize with each other, wherein the first value is different from the fourth value; controlling the second register and the third register to synchronize with each other, wherein the second value is different from the third value; and periodically checking if the third register has the third value and the fourth register has the fourth value to determine if the first node fails to work.

Abstract: An adaptive interface storage device. In some embodiments, the adaptive interface storage device includes: a rear storage interface connector; an adaptable circuit connected to the rear storage interface connector; a first multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the first multiplexer. The adaptive interface storage device may be configured to operate in a first state or in a second state. The adaptive interface storage device may be configured: in the first state, to present a device side storage interface according to a first storage protocol at the front storage interface connector, and in the second state, to present a device side storage interface according to a second storage protocol, different from the first storage protocol, at the front storage interface connector.

Abstract: A thunderbolt device module is provided. The thunderbolt device module of the invention includes a first interface protocol component, a thunderbolt controller and a second interface protocol component. A root complex of an electronic device is via a bus, conforming to a PCIe interface protocol, directly or indirectly electrically coupled to the second interface protocol component. The first interface protocol component and the second interface protocol component both conform to a predetermined interface protocol. In particular, the predetermined interface protocol is not the PCIe interface protocol, but supports the PCIe interface protocol. The thunderbolt controller is electrically coupled to the first interface protocol component. The second interface protocol component is electrically coupled to the first interface protocol component. The communication between the second interface protocol component and the first interface protocol component conforms to the predetermined interface protocol.

Abstract: Disclosed are techniques to regenerate SYNC bits of a High-Speed data packet lost by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may lose some SYNC bits at the beginning of the SYNC pattern. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. If the end of the SYNC is read before a programmable number of SYNC bits have been transmitted, the repeater/hub generates additional SYNC bits for transmission until the programmable number of SYNC bits are transmitted. The repeater/hub then resumes transmitting the rest of the High-Speed data packet starting from the payload.

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

Abstract: A data processing system includes a central processing unit (CPU) and accelerator cards coupled to the CPU over a bus, each of the accelerator cards having a plurality of data processing (DP) accelerators to receive DP tasks from the CPU and to perform the received DP tasks. At least two of the accelerator cards are coupled to each other via an inter-card connection, and at least two of the DP accelerators are coupled to each other via an inter-chip connection. Each of the inter-card connection and the inter-chip connection is capable of being dynamically activated or deactivated, such that in response to a request received from the CPU, any one of the accelerator cards or any one of the DP accelerators within any one of the accelerator cards can be enabled or disabled to process any one of the DP tasks received from the CPU.

Abstract: Systems, methods, and apparatuses relating to performing an attachment of an input-output memory management unit (IOMMU) to a device, and a verification of the attachment. In one embodiment, a protocol and IOMMU extensions are used by a secure arbitration mode (SEAM) module and/or circuitry to determine if the IOMMU that is attached to the device requested to be mapped to a trusted domain.

Abstract: An integrated circuit includes a primary initiator domain (ID) circuit including having a processor core, a responder domain (RD) control circuit, and a reset controller. Secondary ID circuits, each include a processor core and a reset controller. RD circuitry is coupled to communicate with the primary ID circuit and the secondary ID circuits and includes RD resource circuits. The RD control circuit is configured to allocate each of the RD resource circuits to a first initiator domain consisting of the primary ID circuit or one of the secondary ID circuits, and when one of the secondary ID circuits enters a reset mode of operation, the RD resource circuit allocated to the one of the secondary ID circuits enters a reset while the remaining RD resource circuits are not affected by the reset.

Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.

Abstract: Alternate sideband signaling in a Peripheral Component Interconnect (PCI) express (PCIE) link may be enabled over existing sideband lines in a conventional PCIE link. For example, the default sideband communication of PCIE may be changed to a Universal Asynchronous receiver/transmitter (UART), line multiplex UART (LM-UART), serial peripheral interface (SPI), I2C, or I3C mode of communication. This change may be negotiated between the host and slave of the communication link, with a transition occurring after the negotiation concludes. The new mode of communication may include or encode the conventional PCIE sideband signals.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. The drive aggregator associates the host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the plurality of component solid state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have an overlapping region that are hosted on the same set of memory units such that the memory units can be addressed in any of the logical address spaces having the overlapping region.

Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

Abstract: A dynamic switching method is applied to an electronic switching device. Judge whether insertion and withdrawal times between the electronic switching device and a USB cable reach a preset threshold value. Start a UART function of the electronic switching device temporarily. Judge whether an instruction of starting the UART function sent by the USB cable is received. If a recognition program unit receives the instruction of starting the UART function, the recognition program unit starts the UART function. Execute the UART function. Judge whether the electronic switching device receives an instruction of stopping the UART function. Switch to an initial status. Change a start value of a UART circuit unit into an initial value of the UART circuit unit. Charge the electronic switching device through the USB cable.

Abstract: A bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is arranged to communicate with a host via a PCIe bus. The network subsystem is arranged to communicate with an NVMe-TCP device via a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is arranged to deal with data transfer associated with the NVMe-TCP device without intervention of the host.

Abstract: A CDN traffic is optimized by a client-side system that maps the servers in the CDN system. Content requests from client devices for domain names are forwarded to servers in the CDN system that may be selected from the map to prevent a cache miss in the a server for a particular request for content.

Abstract: An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes instructing a PCIe fabric communicatively coupling a plurality of physical computing components including PCIe devices and one or more PCIe switches to establish a first PCIe communication path between the management processor and a target PCIe device. The method also includes directing at least configuration data to the target PCIe device using the first PCIe communication path and instructing the PCIe fabric to remove the first PCIe communication path between the management processor and the target PCIe device. The method also includes instructing the PCIe fabric to establish a second PCIe communication path between a selected PCIe device and the target PCIe device configured according to the configuration data.

Abstract: Methods, systems, and computer storage media for providing a Shell PCIe Bridge (SPB) and shared-link-interface services that support a shared common PCIe physical link between SPB clients in a PCIe system. In operation, shared-link-interface operations include accessing, at a Shell PCIe Bridge (SPB), an outbound transaction for a PCIe endpoint vendor IP or an inbound transaction for an SPB client. The SPB supports a shared common PCIe physical link based on a shared-link-interface comprising vendor-agnostic downstream custom interface and a vendor-specific upstream PCIe endpoint interface. The shared-link-interface operations further include processing the outbound transaction or the inbound transaction based on shared-link-interface services. In this way, processing transaction comprises executing shared-link-interface operations that provide protection enhancements associated with sharing a physical PCIe link.

Abstract: A firmware enumerates the buses of root bridges in the computing system. If an OOR condition occurs during enumeration of the buses, the firmware determines the number of required buses for each root bridge causing an OOR condition. The number of required buses for bridge devices connected to each root bridge causing an OOR condition can be identified using the same set of bus numbers. Once the firmware has determined the number of buses required by each root bridge, including those not causing an OOR condition, the firmware reallocates the number of available buses between the root bridges such that each root bridge is allocated a number of the available buses greater than or equal to the number of required buses. The firmware stores data identifying the allocation and restarts the computing device. Upon rebooting, the computing system utilizes the new allocation of bus numbers to eliminate the OOR condition.

Abstract: Hardware transactions or other techniques, such as custom PCIe handling devices, are used to atomically move pages from one host's memory to another host's memory. The hosts are connected by one or two non-transparent bridges (NTBs), which make each host's memory and devices available to the other, while allowing each host to reboot independently.

Abstract: A USB device and a firmware updating method for the USB device are provided. The firmware updating method includes the following steps. Firstly, a communication protocol is provided. Then, the communication protocol is installed in the at least one microcontroller unit of the USB device. Then, an application program is produced according to the communication protocol. The application program is installed in an electronic computer. The application program contains at least one update firmware information. Then, the at least one update firmware information is transmitted from the electronic computer to the at least one microcontroller unit through the communication protocol. Consequently, at least one original firmware information in the at least one microcontroller unit is replaced by the at least one update firmware information.

Abstract: A management method for managing a memory storage device compatible with a PCIe (PCI Express) standard is disclosed. The memory storage device has a plurality of pins configured to couple to a host system. The management method includes: transmitting a first command to the memory storage device through at least one first pin among the pins to control the memory storage device to enter a target link status; and when the memory storage device is in the target link status, transmitting a second command to the memory storage device through a second pin among the pins to control the memory storage device to leave the target link status. The second pin is not a pin dedicated to control the memory storage device to enter or leave the target link status.

Abstract: An audio-visual transmission device connected with a camera and a receiver is provided and includes a wireless module, a processor and a universal serial bus (USB) port. The wireless module is used for wireless connection with the camera to receive an audio-visual data transmitted from the camera. The processor transmits a connection request signal to the camera through the wireless module. The universal serial bus (USB) port is used for transmitting the audio-visual data. The camera transmits a connection acknowledgment signal and the audio-visual data back to the processor via the wireless module according to the connection request signal, and the receiver is connected to the audio-visual transmission device through the USB port to receive the audio-visual data.

Abstract: An electronic device including a PDIC, a charging IC, and a processor. The PDIC determines whether an external device is connected to the USB port, through a first pin of a USB port. The charging IC outputs a first voltage, which is a voltage obtained by boosting a voltage provided by a battery, to the external device through a second pin, when the external device is connected to the USB port. The processor is configured to determine whether the external device connected to the USB port is a first external device having a specified VID and a specified PID, through a third pin of the USB port, and to transmit a first signal, which controls the charging IC to output a second voltage having a magnitude less than the first voltage, to the charging IC when the first external device is connected to the USB port.

Abstract: A system includes a storage device; a storage device controller; a first interface configured to connect the storage device controller to the storage device; and a second interface configured to connect the storage device controller to a host device, wherein the storage device is configured to operate in a first mode or a second mode based on a status of a signal at the second interface based on instructions received from the host device.

Abstract: Apparatuses, methods, and computer-readable media are provided for operating a port manager to detect a first link condition or a second link condition of a circuitry. Under the first link condition, a first link between a downstream port of the circuitry and an upstream port of a switch is compatible to a first protocol, and a second link between a downstream port of the switch and an upstream port of a device is compatible to the second protocol. Under the second link condition, the first link exists and is compatible to the first protocol, while there is no second link being compatible to the second protocol. The port manager is to operate the downstream port of the circuitry according to the second protocol on detection of the first link condition, or according to the first protocol on detection of the second link condition. Other embodiments may be described and/or claimed.

Abstract: A front adapter for connecting to a control device, has a connection device connected to a predetermined system cable for connecting at least one field component, at least one wireless communication interface for wirelessly transmitting and receiving signals to or from at least one wireless one transmitting and/or receiving device which can be connected to a first field unit, and/or at least one bus-capable communication interface for transmitting and receiving signals via a signal bus to or from at least one bus-capable transmitting and/or receiving device which can be connected to a second field device, and a control and/or evaluation device which is adapted to control the transmitting of signals between the control device and the at least one wireless transmitting and/or receiving device and/or the at least one bus-capable transmitting and/or receiving device.

Abstract: The present disclosure provides an information handling system (IHS) and related methods that provide secure shared memory access (SMA) to shared memory locations within a Peripheral Component Interconnect (PCI) device of an IHS. The IHS and methods disclosed herein provide secure SMA to one or more operating system (OS) applications that are granted access to the shared memory. According to one embodiment, the disclosed method provides secure SMA to one or more OS applications by receiving a secure runtime request from at least one OS application to access shared memory locations within a PCI device, authenticating the secure runtime request received from the OS application, creating a secure session for communicating with the OS application, and providing the OS application secure runtime access to the shared memory locations within the PCI device.

Abstract: A hypervisor managing a virtual machine (VM) running on a host computer system, modifies a virtual machine control structure (VMCS) associated with the VM to trigger a VM exit upon detecting a transition of the VM to a specified power state. Upon detection of the VM exit, a timer is initialized to trigger another VM exit, and execution of the VM in the specified power state is resumed.

Abstract: An image processing apparatus, which complies with a particular setting protocol including a procedure to receive setting information for a first communication system from an OS of an information processing device, includes a first communication interface for a first communication system, a second communication interface for a second communication system, and a controller configured to transmit, to the information processing device via the second communication interface, compliance information representing that the image processing apparatus complies with the particular setting protocol, after sharing mutual compliance recognition with the information processing device through transmitting the compliance information, receive the setting information from the OS via the second communication interface in accordance with the particular setting protocol, the mutual compliance recognition being recognition that the image processing apparatus and the OS comply with the particular setting protocol, and configure sett

Abstract: Described are mechanisms and methods to facilitate power saving in Type-C connectors. Some embodiments may comprise an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port, a first circuitry, and a second circuitry. The first circuitry may be operable to place toggled values on the CC signal path. The second circuitry may be operable to couple the ground signal path to a detection signal path. The placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device, and may be disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device.

Abstract: A convertible I/O signal processor is convertible between different operating configurations for connecting multiple field devices to the I/O signal processor by selectable types of electrical connectors such as cables, terminal blocks, and the like. The I/O signal processor includes a signal processing module connected to a signal processor and an interface module removably connected to the signal processing module. The interface module includes electrical connectors for receiving/transmitting I/O signals from and to field devices. The interface module and the signal processing module define I/O channels extending between the electrical connectors and the signal processor. The interface module in embodiments includes I/O module connectors that enable removable I/O modules to be interposed in the I/O channels.

Abstract: A reliable and scalable data repository service can be supporting cooperative transactions. In an example, multiple data producers may use the data repository service to upload data in one or more transactions. Data contained in one transaction may be treated as an atomic unit. In an embodiment, the data repository service manages multiple candidate transactions associated with an election transaction such that at most one candidate transaction may begin and/or commit a given time. During a commit of a candidate transaction, the data uploaded during the candidate transaction may become associated with the election transaction. The data repository service may maintain metadata associated with each of the candidate transactions. In response to a request for data associated with the election transaction, the metadata may be used, in conjunction with a user-specified isolation level, to locate the data uploaded some of the candidate transactions for the election transaction.

Abstract: A switching system includes a first switching device and a second switching device. The first switching device and the second switching device are coupled using a network. The first switching device includes a plurality of PCIe upstream ports configured to connect to at least one host, the second switching device comprises at least one PCIe downstream port configured to connect to at least one input/output (I/O) device, and the second switching device is configured to receive a first data packet from the first switching device using the network, convert the first data packet to a second data packet complying with a PCIe protocol, and transmit the second data packet to a target I/O device of the second data packet.

Abstract: An electronic device according to an embodiment of the present invention comprises: a universal serial bus (USB) interface; a processor electrically connected to the USB interface; and a memory electrically connected to the processor, wherein the memory may store instructions configured to, when executed, cause the processor to: enter a security mode; in the security mode, receive, from an external device connected to the electronic device via the USB interface, a USB class code corresponding to the external device; determine whether the USB class code is included in a white list of connectable devices allowed to be connected to the electronic device in the security mode; and control a communication connection between the external device and the electronic device according to whether the USB class code is included in the white list. Other embodiments are also possible.

Abstract: The disclosed computer-implemented method for controlling access to a peripheral device may include receiving an input/output request related to a process attempting to access the peripheral device. The method can also include determining an access state for the process indicative of whether the process will be allowed to gain access to the peripheral device. The access state can be based on a context property of the process. The method can further include responding to the input/output request with initiation of a virtual peripheral output from a virtual peripheral device if the access state is indicative of the process not being allowed access to the peripheral device. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes.

Abstract: A virtualization system includes at least one storage device, a plurality of computing nodes, each computing node coupled to at least one of the storage devices, each computing node comprising a physical function (PF) agent, and a plurality of virtual machines, where the PF agent of a first computing node of the computing nodes is configured to receive from a virtual machine of the virtual machines a request for retrieving or writing data and to obtain placement information indicating a second computing node of the computing nodes for retrieving or writing data, and the PF Agent of the first computing node is configured to communicate with the PF Agent of the second computing node to retrieve data from the second computing node or write data to the second computing node based on the placement information.

Abstract: An electronic device includes a connector that includes a first terminal for receiving power from a power supply apparatus, a second terminal, a third terminal, and a fourth terminal; a control unit that controls power received from the power supply apparatus via the first terminal; and a determination unit that determines a power supply capability of the power supply apparatus by using the second terminal or the third terminal and the fourth terminal, wherein the determination unit determines the power supply capability of the power supply apparatus by using the third terminal and the fourth terminal before a predetermined transition occurs in the second terminal.

Abstract: An electronic device includes a connector that includes a first terminal for receiving power from a power supply apparatus, a second terminal, a third terminal, and a fourth terminal; a receiving power control unit that controls power received from the power supply apparatus via the first terminal; a determination unit that determines a power supply capability of the power supply apparatus by using the second terminal or the third terminal and the fourth terminal; and a control unit that restricts, before the power supply capability of the power supply apparatus is determined by using the third terminal and the fourth terminal, power to be received from the power supply apparatus via the first terminal when a predetermined transition occurs in the second terminal.

Abstract: According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.