Abstract: Provided are a method, system, and article of manufacture, wherein a primary storage control unit receives an information unit from a remote host over a fibre channel connection, wherein persistent information unit pacing is implemented over the fibre channel connection. Information is maintained on how many large writes have been received at the primary storage control unit over at least one logical path established over the fibre channel connection between the primary storage control unit and the remote host, wherein a large write is an input/output (I/O) operation for which a number of data information units that are processed exceeds a default value of an information unit pacing credit.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: A disk control device stores write requests from a cache memory or reads commands from a host in a queue for a disk drive in chronological order. When the number of write requests stored in the queue for the disk drive is greater than a predetermined value, the storage location of write requests is changed to a queue for an extra disk drive, and the write requests are stored in the queue for the extra disk drive. When the number of write requests stored in the queue for the disk drive becomes smaller than a predetermined threshold, the write requests stored in the extra disk drive are written back to the disk drive.

Abstract: A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: In a multi-queue memory system, a plurality of read count pointers (one for each queue) are stored in a read address file, and used to generate empty flags. A read count pointer associated with a first queue is retrieved from the read address file, and it is determined whether the first queue should be available for a re-read operation. If so, the retrieved read count pointer is stored as a first read mark value. The read count pointer is incremented in response to each read operation performed from the first queue, thereby creating an adjusted read count pointer. If a re-read operation is to be performed from the first queue, the first read mark value is stored in the read address file. Otherwise, the adjusted first read count pointer is stored in the read address file. Similar operations are performed on the write side of the multi-queue memory system.

Abstract: A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.

Abstract: A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to acquire access hint information which represents a data access interval to the main memory, a second acquiring device to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device, a determining device to determine a preload unit count based on the data access interval represented by the access hint information and the transfer delay time represented by the system information, and a management device to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the temporary memory ahead of a data access of the data.

Abstract: A primary storage control unit receives an information unit from a remote host over a fibre channel connection. The primary storage control unit adjusts an information unit pacing parameter included in a response sent from the primary storage control unit to the remote host, wherein the information unit pacing parameter indicates the number of information units that the remote host is allowed to send to the primary storage control unit without waiting for any additional response from the primary storage control unit.

Abstract: Embodiments of the invention provide a method and apparatus for initializing a computer system, wherein the computer system includes a processor, a volatile memory, and a non-volatile memory. In one embodiment, the method includes, when the computer system is initialized, automatically copying initialization code stored in the non-volatile memory to the volatile memory, wherein circuitry in the volatile memory automatically creates the copy, and executing, by the processor, the copy of the initialization code from the volatile memory.

Abstract: A method of coupling a multimedia source device to a multimedia sink device by providing a source device having a transmitter unit coupled thereto, providing sink device having a receiver unit coupled thereto, receiving a source data stream in accordance with a native stream rate by the transmitter unit, coupling the transmitter unit and the receiver unit by way of a linking unit, forming a multimedia data packet stream formed of a number of multimedia data packets and generating a transport schedule for transferring the multimedia data packet stream in accordance with a link rate between the transmitter unit and the receiver unit wherein the multimedia data.

Abstract: A system includes a read/write channel and a hard disk controller. The hard disk controller includes a latency-independent interface that communicates with the read/write channel. A serial control data circuit transmits a serial control data signal including serial control data, wherein the serial control data signal has a variable number m of words, wherein each of said m words comprises n bits, and wherein at least one of said n bits of each of said m words includes information indicating whether a subsequent word of said serial control data signal will follow. A data circuit that transmits or receives data under the control of the serial control data signal.

Abstract: A method and apparatus for generating identification numbers for PCI Express that provides unique generation and substantially increased system performance. A system having a PCI Express fabric and PCI devices connected thereto generates unique TAG identification numbers for transactions with substantially increased performance. The system generates and prepares up to three available TAG IDs in advance, before a request is granted. When a completion-required request receives a grant, it picks up the TAG ID from the storage rather than generating it on the fly. This enables the system to process back-to-back TLP requests without any dead cycles.

Abstract: Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core.

Abstract: Methods and apparatuses are described for a communication system. The communication system may include one or more initiator agents, where each agent couples to its own Intellectual Property core. The communication system may also include two or more target agents, where each agent couples to its own Intellectual Property core. The communication system may also include an interconnect using an end-to-end width conversion mechanism. The conversion mechanism converts data widths between the initiator agent and a first target agent. Two or more branches of pathways in the interconnect exist between the initiator agent and the two or more target agents. The conversion mechanism to use a lookup table that includes data width information of the initiator agent and the two or more branches of pathways to the two or more target agents to concurrently pre-compute width conversion signals for each of the target agent branches.

Abstract: A method, computer program product, and distributed data processing system that enables host software or firmware to map PCI adapter virtual resources to PCI bus addresses that are associated with a system image is provided. Virtual addresses maintained in a protection table segment assigned to a system image are mapped to physical addresses defined in entries of an address table segment assigned to the system image. Discontiguous memory regions identified in entries of the address table segment may thus be mapped to a contiguous virtual address space.

Abstract: In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted.

Abstract: A serial ATA interface interfaces an ASIC with a HDD. A transfer start monitoring unit monitors start of data transfer between the ASIC and the HDD and a transfer completion monitoring unit monitors completion of the data transfer. A power management control unit controls power consumption of the ASIC and the HDD based on monitoring results obtained from the transfer start monitoring unit and the transfer completion monitoring unit.

Abstract: A method is provided for transmitting data from a transmitting device (121) to a receiving device (125). The transmitting device transmits a first data frame (200) to a receiving device a first time (3100). Then it consecutively transmits the first data frame to the receiving device second through Nth times (3101-310N), each of second through Nth first data frame transmissions being made a first predetermined time period (350) after a respective previous first data frame transmission. After this, the transmitting device transmits a second data frame (200) to the receiving device a second predetermined time period (360) after the Nth first data frame transmission. In this method, N is an integer greater than 1, and the second predetermined time period is less than the first predetermined time period.

Abstract: A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to acquire access hint information which represents a data access interval to the main memory, a second acquiring device to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device, a determining device to determine a preload unit count based on the data access interval represented by the access hint information and the transfer delay time represented by the system information, and a management device to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the temporary memory ahead of a data access of the data.

Abstract: A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent DMA transfer operation, without waiting for a processor to read the transferred data count. The transferred data count may be written to memory at an address specified in a transferred data count save address register; may be saved to a transferred data count register dedicated to the DMA channel; or may be saved to a transferred data count register shared between two or more DMA channels. The processor may read the transferred data count and, if applicable, clear the relevant transfer data count register, subsequent to the DMA controller beginning another DMA operation on that DMA channel.

Abstract: A technique of protection of personal data is provided, in which there is no need to repeatedly instruct search conditions, and also provided is a technique of protection of personal data in which operation cost can be reduced. Respective personal data include multiple items and an item value of each of the items. A information processing apparatus selects at least one of the items for each of multiple personal data. The information processing apparatus counts, for each of the multiple personal data, the number of personal data that include a combination of the same item values as an item value of the selected item. As a result, the information processing apparatus outputs only item values of items having the number of personal data equal to or larger than a threshold, to an output device.

Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a cache line size without a remainder, a valid data length is set equal to the length field. However, if the frame size divided by the cache line size results in a remainder, the length field is set to align the data with the cache line size. The data transfer is then initiated using these fields.

Abstract: Local drive presence is provided for local and remote drives by maintaining a plurality of uninterrupted protocol connections between a plurality of I/O controllers and a plurality of device interfaces through which peripheral bus commands are transmitted. Preferably, the I/O controllers are each housed in a separate server blade and provide each blade with access to the local and remote drives. At each of the device interfaces, rather than attaching an actual storage device, peripheral bus commands received at the device interfaces are serialized and conditionally passed or suppressed to and from the shared drive which is shared amongst the plurality of uninterrupted protocol connections. Preferably, the plurality of uninterrupted protocol connections is maintained such that the shared drives can be simultaneously shared. In one embodiment, the local drives are provided in a media tray which is shared amongst a plurality blades.

Abstract: A device (1) for indicating downloading of a data item (3) by a user computer (5) from a first computer (7) using a data communication network (9) is disclosed. The device (1) comprises a processor (13) being configured for receiving an upload instruction for uploading the data item (3) from a second computer (15) to the user computer (5) via the data communication network (9). The upload instruction has been generated by a first markup language tag referring to the data item (3). The first markup language tag has been generated by a browser executable script uploaded to the user computer (5) from the first computer (7). The first markup language tag differs from a second markup language tag in a cache memory of the user computer (5) causing the user computer (5) to download from the second computer (15). The first and second markup language tags were generated by the browser executable script. The processor is also configured for indicating that the upload instruction has been received.

Abstract: A communications system is provided in which a host may receive data from a slave device over a polling bus. The slave device first reports to the host an initial amount of data to be transferred. The host can then initiate a data transfer from the slave device in order to retrieve the specified amount of data. As that initial data is being transferred over the bus, if additional data to be transferred to the host is received by the slave device, the slave device will report that supplemental amount of data to the host along with the initial data. The host may then immediately schedule a supplemental data transfer from the slave device in order to retrieve the additional data. The slave device may utilize a self-decrementing counter in order to keep track of the packets that require transfer but have not yet been reported to the host. The amount of data reported by the slave device to the host device may be provided as a count of packets in which the packets have a predetermined maximum size.

Abstract: One embodiment of a long-distance synchronous bus includes a sending unit and a receiving unit. The sending unit and receiving unit are configured to use credit-based handshaking signals to regulate data flow between themselves. The receiving unit includes a skid buffer for storing data packets received from the sending unit. The sending unit transmits one data packet to the receiving unit for each credit in possession and consumes one credit for each such transmitted data packet. The receiving unit transmits one credit to the sending unit for each data packet that is read out of the skid buffer. In another embodiment, transmitted data may be broadcast to multiple receiving units by routing the data from the sending unit to the multiple receiving units and maintaining separate credit-based handshaking signals for each receiving unit.

Abstract: A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.

Abstract: A method, computer program product, and distributed data processing system that allows a single physical I/O adapter to validate that a memory mapped I/O address referenced by an incoming I/O operation is associated with a virtual host that initiated the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing a PCI family I/O adapter and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A mechanism is provided that allows a single physical I/O adapter to validate that a memory mapped I/O address referenced by an incoming memory mapped I/O operation used to initiate an I/O transaction is associated with a virtual host that initiated the incoming memory mapped I/O operation.

Abstract: An information processing device for reducing the time required for the data transfer as much as possible while displaying information of the data transfer state in synchronization with the data transfer. The information processing device is equipped with a counter for counting the number of pieces of data having been transferred in a data transfer. When a large number of pieces of data is to be transferred in the data transfer, the number of pieces of data having been transferred is displayed every time a certain number of pieces of data, not one piece of data, are transferred.

Abstract: A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent DMA transfer operation, without waiting for a processor to read the transferred data count. The transferred data count may be written to memory at an address specified in a transferred data count save address register; may be saved to a transferred data count register dedicated to the DMA channel; or may be saved to a transferred data count register shared between two or more DMA channels. The processor may read the transferred data count and, if applicable, clear the relevant transfer data count register, subsequent to the DMA controller beginning another DMA operation on that DMA channel.

Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a cache line size without a remainder, a valid data length is set equal to the length field. However, if the frame size divided by the cache line size results in a remainder, the length field is set to align the data with the cache line size. The data transfer is then initiated using these fields.

Abstract: Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one embodiment, a network adapter has a microengine which obtains read target data from a cache coupled to the network adapter to respond to a read command packaged in a packet sent by an initiator over a network. If the network adapter cache does not have the target data addressed by the read command, the read command is forwarded to a target controller coupled to a storage unit to process the read command.

Abstract: A data processor including a central processing unit and a data transfer control unit is disclosed. The data transfer control unit has an address register for storing a transfer address. The data transfer control unit transfers data according to a transfer unit size selected from a plurality of transfer unit sizes. If the address register contains an odd address as an initial value, the data transfer control unit transfers data according to a different transfer unit size that is smaller than the selected transfer unit size. If the data transfer control unit determines that a remaining quantity of data to be transferred is smaller than the selected transfer unit size, the selected transfer unit size is switched to a smaller transfer unit size selected from the plurality of transfer unit sizes.

Abstract: A portable computer system includes a portable computer equipped with a graphic chip, and an LCD monitor receiving a video signal from the graphic chip and displaying the video signal. The portable computer system further includes an external video signal input part provided at the portable computer and receiving an external video signal from an external computer, an A/D converter provided at the portable computer and converting the external video signal inputted through the external video signal input part into a digital signal, and a control part controlling the video signal and the digital signal from the graphic chip and the A/D converter to be outputted to the LCD monitor. With this configuration, the present invention provides a portable computer system enhancing the utility of the LCD monitor by receiving an external video signal from an external computer and displaying it on an LCD monitor.

Abstract: Provided are a method, system, and program for querying a plurality of adaptors in a system. A request is received to determine connection information for the adaptors in the system. A master task spawns a plurality of tasks to query the adaptors. Each spawned task updates adaptor information with information gathered from querying the adaptor. If no tasks are available to query at least one adaptor that has not been queried, then the master task queries one adaptor and updates the adaptor information with information gathered by querying the adaptor.

Abstract: A pattern may be written to an allocated section of host memory to track how much data has been received in the host memory from a direct memory access controller coupled to a First In, First Out memory. A driver may send the most recently written sample of data from the host memory to an application requesting sampled data. The driver may determine the amount of data written to the host memory by reading the allocated section of host memory and determining the size of a portion of memory, that previously had the pattern, that has been written over with data. The driver may determine if more data than a predetermined amount of data has been written to the host memory or is available to be written to the host memory, and if necessary, send an indication to the application.

Abstract: A storage controller includes a first memory that stores a plurality of data blocks that include first and second noncontiguous data segments. A queue module stores data lengths and data start addresses of the first and second data segments. A read assembly module communicates with the first memory and the queue module, receives a request to read the first and second data segments from a host, reads the plurality of data blocks from the first memory, extracts the first and second data segments from the read plurality of data blocks based on the data lengths and data start addresses after the plurality of data blocks is read from the first memory, and transfers the first and second data segments contiguously to the host.

Abstract: A portable computer system includes a portable computer and an integrated device both having wireless data transmission interface. The integrated device is connected to various peripheral devices with different interfaces and controlled by corresponding external port signals. When the portable computer wants to access the peripheral devices, a signal processor integrates and encodes all the external port signals to generate a single encoded signal to be fed to the integrated devices via the wireless transmission interface. After the integrated device receives the encoded signal, a signal processor decodes it to reproduce individual external port signals to be transferred to each corresponding peripheral device to control the operation thereof. During the encoding process, the signal processor may set the priorities according to the properties of each signal and add the identification information of the portable computer.

Abstract: A system includes a read/write channel and a hard disk controller. The hard disk controller includes a latency-independent interface that communicates with the read/write channel. A serial control data circuit transmits a serial control data signal including serial control data, wherein the serial control data signal has a variable number m of words, wherein each of said m words comprises n bits, and wherein at least one of said n bits of each of said m words includes information indicating whether a subsequent word of said serial control data signal will follow. A data circuit that transmits or receives data under the control of the serial control data signal.

Abstract: In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other packet flow, a self-synchronous transfer control circuit having a function of controlling transfer operation is used, by which the number of packet copies output from a data holding register is managed by a counter, and the number of copies represented by the copy request packet and the counter count value are compared by a comparator, to determine completion of the packet copying operation.

Abstract: In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more direct memory access (DMA) machines; and (2) assigning a programmable priority of access to the memory bandwidth to a processing unit. The programmable priority of the processing unit allows priority allocation between the one or more DMA machines and the processing unit to be adjusted dynamically. Numerous other aspects are provided.

Abstract: Embodiments of the invention include a system for an integrated circuit development. Elements of the development system include hardware and software objects. Boundaries of the objects may include register structures, which regulate data transfer between and within objects. Protocols, including forward and reverse protocols indicate when data is ready to be accepted, and when it is valid and ready for use. Further, specific protocol information indicates the beginning and end of a group of data. Specialized objects include fork and join objects. Fork objects have more register structures for output than they do for input, while join objects have fewer register structures for output than they do for input.

Abstract: Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case throughput rate (without use of SFBs) is computed, and maximization factor equaling a desired throughput rate divided by the worst case throughput rate is computed. A number of SFBs is determined as equaling one less than the maximization factor. By placing the SFBs at appropriate locations in the data transfer path, the desired throughput rate may be attained when transferring large volumes of data.

Abstract: The present invention provides for the scheduling of requests to one resource from a plurality of initiator devices. In one embodiment, scheduling of requests within threads and scheduling of initiator device access is performed wherein requests are only reordered between threads.

Abstract: A fast with-in range comparator is implemented in digital logic. A packet arrives at a device for processing. Initial packet data that is available in a first read cycle, is used to compute data that is necessary for later cycles. The initial data and the subsequently data are then used to test a single value against a range of values. In a method of the present invention a range is separated into two ranges. An upper limit of the first range is tested to determine whether the value is below the upper limit. If this test fails, the value is tested to determine whether the value is between the upper limit of the first range and the upper limit of the full range. The ranges are tested by constructing a bit vector. Data representing the capability of a communicating port, is then used to index into the bit vector. The outcome of the index is a value that signifies whether the port can support the packet or not.

Abstract: A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus having a transmit channel, a receiving component, and a sending component configured to broadcast a payload to the receiving component over the transmit channel, interrupt the broadcast of the payload to signal a new bus operation to the receiving component over the transmit channel, and resume the broadcast of the payload over the transmit channel. The processing system may include an algorithm that prevents small payloads from being interrupted to initiate a new bus operation. The algorithm may also be used to limit the number of times a single write operation may be interrupted to initiate a new bus operation.

Abstract: Multi-dimensional data routing fabric simultaneously transfers multiple data packets between data processing components. Data packets are transported by arrays of data routing junctions dispersed along multiple routing dimensions. Data routing junctions are interconnected along each of routing dimensions with a mesh of data routing lines. Data transfers are accomplished by source components launching data packets into the multi-dimensional data routing fabric, and destination components receiving the routed data packets from the fabric. Each packet is guided by a chain of adjacent data routing junctions to converge on its destination. Individual data routing junctions along the packet's path make routing decisions by comparing the current location and direction of movement of the packet to the location of its destination. Based on the results of these comparisons, data packets are passed straight through to the next junction ahead, or are turned to an adjacent junction to the side of the current path.

Abstract: A data transfer control device and method is devoted to control data transfer (i.e., DMA transfer) between a main memory whose storage capacity is arbitrarily set and a buffer memory (e.g., a FIFO memory) incorporated in a peripheral module, wherein a first register is arranged to store a first value representing a first number of times for transferring m-bit data to suit the storage capacity of the buffer memory, and a second register is arranged to store a second value representing a second number of times for transferring m-bit data to match the amount of transferring data stored in the main memory. A controller is arranged to control transferring of m-bit data based on the first value while controlling writing operations for the buffer memory. It determines the timing to output an interrupt signal to a CPU managing the main memory on the basis of the second value.

Abstract: A queue monitoring system and method determines when one or more transmit queues have reached a state that requires action by the host processing device, without the need for periodic polling of transmit status or excessive interrupt servicing. The queue monitoring implements an interrupt mechanism that generates an interrupt if one or more of the transmit queues has gone from a non-empty state to an empty state, and remained in the empty state for a (programmable) period of time. The combination of queue status checking (when adding new transmit data) with the queue monitoring interrupt mechanism removes the need for periodic polling of queue status and handling of interrupts generation on the completed transmission of data from one or more transmit buffer.

Abstract: A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first deice when it is determined that the first device should release the bus.