Abstract: The present invention is directed to a system and method employing a dynamic logical identifier. In an aspect of the present invention, a method for accessing data utilizing an input/output interface may include providing an identifier for accessing a target device by a host and generating a logical identifier from the obtained identifier by the host. The logical identifier is transferred to an input/output interface and a look-up table is accessed utilizing the logical identifier by an input/output interface controller. The look-up table is included on the input/output interface, wherein the look-up table provides access between the input/output interface and the target device so as to enable the host to access the target device.

Abstract: A computer network system includes a plurality of computers each including a central processing unit (CPU), a memory and at least one peripheral device, a connection fabric having selectable first and second sides, the first side being coupled to a first computer of the plurality of computers and the second side being coupled to at least a second computer of the plurality of computers. Each of the first and second computers performs a negotiation to determine which one of the first and second computers controls resources of the other of the first and second computers.

Abstract: A bus system is provided.

Abstract: A microchip card enables a user to access at least one chosen application on a particular server by means of any communication terminal using at least one mode of communication and fitted with a reader compatible with the microchip card. The card includes memory for storing sets of parameters specific to the mode(s) of communication used by the terminal and to the chosen application(s) and a system which can recognize the mode(s) of communication the terminal in which it is inserted can use. A selector system connected to the memory and to the recognition system selects a set of parameters corresponding to a recognized mode of communication of the terminal and to the chosen application. The selected parameter set is delivered to the terminal to enable access to the chosen application from that terminal.

Abstract: The present invention comprises an efficient and portable method and algorithm module for servicing large numbers of IO descriptors which may interface to a large network environment or to a large number of IO devices and services. The method and algorithm module queries those descriptors that are most likely to have activity, but also reliably queries all descriptors over time, and dynamically adjusts the frequency of queries to maintain maximum efficiency as conditions change. It also queries all descriptors within a reasonable time, and has minimal overhead and uses standard system interfaces.

Abstract: An information processing system which makes it possible to protect information stored in the ROM of the system from unauthorized access by means of a debug tool. The information processing system includes a ROM for storing an unlocking program and a user program; a CPU for executing said unlocking program and said user program stored in said ROM; an on-chip debug circuit serving to output debug information of said user program as executed by said information processing system; and a debug function disabling circuit serving to disable debug functions of said on-chip debug circuit at power up and to enable the debug functions of said on-chip debug circuit when said unlocking program has been executed.

Abstract: A method and system are disclosed for dynamically changing the priority of memory requests to access a memory device in a disk drive system. In particular, the disk drive system includes a hard disk controller having a processing element for performing various operations and a buffer for providing an interface to a memory device, such as a random access memory. The buffer includes arbitration block to prioritize memory requests to access the memory device. A priority modification block is included to modify the assigned priorities so that the priority assigned to a pending memory request submitted by the processing element is increased. The priority modification block triggers the modification of priorities upon the occurrence of an event, such as the reception of an interrupt by the processing element or a memory request submitted by the processing element timing out.

Abstract: According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed. A data queue coupled to a command queue is arranged to store a time indicating when the data transfer will appear on the data bus between the controller for an already issued request to the target device as well as arranged to store the burst bit and the read/write bit (r/w). The system also includes a collision detector coupled to the data queue and the command queue arranged to detect the possible collisions on the data bus between the issued command that is stored in the command queue and already issued commands that are stored in the data queue. A queues and link controller is coupled to the collision detector and the data queue and the command queue and is arranged to store and reorder commands to be issued wherein the controller calculates the new issue time of commands as well as a time when the data appears on the data bus.

Abstract: In a telephone exchange the functional units of call control communicate by way of a common message bus. If a unit wants to know only one thing from the data of a message, then due to the fixed structure of the message all other data contained in the message must also be received. Unnecessary data is thus transmitted in the message bus. The procedure according to the invention is such that the service requester states in the request message exactly what it wants to know. Since the data structure of the service provider, that is, the position of each individual data and the length of the data field, is known to the service requester, only those entries of the data structure are stated in the request message where the requested data is located. The service provider fetches only this data from its data structure and sends it in the reply message to the message bus. Thus, both the request message and the reply message form a dynamic message pair.

Abstract: A technique for serially controlling an array of optical sensor chips over a pair of signal lines. After broadcasting an initializing reset command to all chips over serial lines, a determine-address command is broadcast to commence unique address determination. On subsequent clock signals, each chip locks its address into an on-board register. Following this process, each chip can be addressed individually. Subsequently, when each array chip is directed to read data out, the data is output to a single common bus line to the controller. Alternatively, individual chip outputs may be connected directly to the controller, or the outputs of odd and even chip pairs may be tied together for broadcast readout of all odd chips or all even chips.

Abstract: A computer system processes system management interrupt (SMI) requests from plural system management (SM) requesters. Different SM requesters are provided with different priority levels such that high priority system management interrupts can be serviced without waiting for lower priority system management interrupts to be serviced completely. In particular, the system executes a first SMI handler routine in response to receiving a first SMI from a first SM requester. In response to receiving a second SMI asserted by a second SM requester, the system determines whether the second SMI request has been assigned a higher priority than the first SMI request. If so, then the system interrupts executing the first SMI handler routine and executes a second SMI handler routine corresponding to the second SMI request. Otherwise, the system completes executing the first SMI handler routine and then executes the second SMI handler routine.

Abstract: According to the present invention, techniques for re-reordering command and data packets in order to restore an original order of out-of-order memory requests are described. In one embodiment, a method of increasing data bandwidth by reordering incoming memory requests in order to avoid gaps between commands on a command bus and data packets on a data bus while maintaining the original incoming memory request order is disclosed. A best position in a command queue is calculated for each new incoming command by a reordering block coupled to the command queue. Read data is stored in a data queue while the associated incoming commands are stored in their respective original order in a FIFO register included in a re-reordering block. The data is stored in its original order in a data queue while incoming data from the memory is stored in a read-data buffer included in the re-reordering block according to the order stored in the data queue.

Abstract: A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests.

Abstract: In a method of and a system for managing reselection of an initiator by a target on a SCSI bus, the target attempts to secure control of the bus for a first reselection cycle to reselect the initiator. If the target fails to secure control of the bus for the first reselection cycle and the target is selected by the initiator for a selection cycle, the target processes the selection cycle. However, concurrently with processing the selection cycle, substantially immediately after the bus becomes free, and before the target completes processing the selection cycle, the target attempts to secure control of the bus for a second reselection cycle to reselect the initiator.

Abstract: The invention is a processing method and a processor architecture which contains multiple processors on the same silicon but which does not make a fixed compromise by statically assigning processing units to the processors but rather dynamically assigns such processing units so that they may be efficiently shared. The invention may provide the same functionality as was obtained with static allocation, and may be implemented on a single chip with much lower area for the same level of performance. The preferred architecture uses a mode bit that may be programatically set for passing control from a general purpose instruction decoder to a finite state machine. The preferred architecture further includes a multiplexer that uses the mode bit as its selection input.

Abstract: According to the present invention, an apparatus for prioritizing access to external devices includes a request queue suitably arranged to store any number of requesting device requests of the external devices, a request queue controller unit coupled to the request queue suitably arranged to fetch any of the requests stored therein, a responds queue suitably arranged to store any number of responses from the external devices.

Abstract: A method and apparatus for allowing several applications to share a single video overlay resource via multiplexing are disclosed. The multiplexing is accomplished from the application end through a multiplexing abstraction layer provided to the developers of end applications as an application program interface. Through the application program interface, each application may, at any time, request, release, or modify the attributes of the video overlay device such as picture quality, tuning, source, etc. The application program interface provides all basic functionality of the hardware as accessible through other means including normal operating system support and device driver services.

Abstract: A method and apparatus for allowing several applications to share a single video overlay resource via multiplexing are disclosed. The multiplexing is accomplished from the application end through a multiplexing abstraction layer provided to the developers of end applications as an application program interface. Through the application program interface, each applications may, at any time, request, release, or modify the attributes of the video overlay device such as picture quality, tuning, source, etc. The application program interface provides all basic functionality of the hardware as accessible through other means including normal operating system support and device driver services.

Abstract: Data communications device and method for arbitrating access to a system memory of the communications device via a peripheral component interconnect (PCI) bus in a network interface having a memory management unit for managing transmit data transfers from the system memory to a transmit buffer memory, and receive data transfers from a receive buffer memory to the system memory. The memory management unit includes an arbitration block having an arbiter state machine, which receives requests for access to the PCI bus in order to provide the transmission and reception of data, descriptors and status information. The arbiter state machine grants the PCI bus access to a request having a higher priority in accordance with a preset priority scheme.

Abstract: All nodes in a network are classified into hierarchical groups. Each node belongs to any group in all hierarchical groups from the highest order group to the lowest order group. The node is assigned a hierarchical address corresponding to each hierarchical group. Thus, the amount of routing information required for data transfer can be reduced, thereby efficiently transmitting data.

Abstract: An apparatus and method which provide increased data flow through a compute platform by optimizing data flow between an external device and the internal circuitry without the need for user intervention. A port router is provided which includes a controller switch, a port switch, and one or more connections between the controller switch and the port switch. The controller switch, the port switch and the one or more connections are adapted to provide dynamic re-routing of connections between the port switch inputs and the controller switch outputs. A method is also provided for dynamically routing ports to internal circuitry of a compute platform.

Abstract: An apparatus is described for controlling pipelined memory access requests in a computer system. A graphics controller is coupled with a system memory by an AGP interface, which has separate write and read request queues. To control the ordering of the write and read requests relative to one another, each of the requests has an associated age tag assigned to it. In the event a read request is received by the AGP interface, an age tag value is assigned to it that corresponds with the number of previously received and currently pending write requests. Similarly, when a write request is received by the AGP interface, an age tag value is assigned that corresponds with the number of previously received and currently pending read requests. Employing such age tags provides AGP-compliant ordering of the write and read requests, while also providing write-passing-read capability without the attendant complex logic circuitry and time delays associated with conventional implementations.

Abstract: A method is described for controlling data transfer operations between a main memory and other devices in a computer system. Data transfer request signals and associated latency identification values are received. Each of the latency identification values corresponds with a maximum time interval in which to service the respective data transfer request. The latency identification values are periodically modified and compared to indicate the current highest priority request. In the event that service of a particular requested data transfer operation must be provided imminently, priority override functionality is provided. In this way, those devices having particular latency requirements can be provided with timely access to the main memory, and need not have separately dedicated memory or buffers.

Abstract: A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests.

Abstract: A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption. The system also includes a tracker to keep track of the number of times each of the factors occurs and a priority changer to change the priority of the devices as a function of the intrinsic priority and the number.

Abstract: A multiple logical FIFO system uses a single main register file to store payload data in association with link data so as to form one linked list data structure for each logical FIFO in the system. A write pointer register file stores one write pointer for each logical FIFO. A read pointer register file stores one read pointer for each logical FIFO. A free register identifier indicates a free register address at all times unless the overall system is full. The free register address corresponds to one free register within the main register file. In a first embodiment, the free register identifier is implemented using a priority encoder. In a second embodiment, the free register identifier is implemented using a conventional FIFO buffer. In a third embodiment, the free register identifier is implemented using one of the logical FIFO buffers stored in the main register file.

Abstract: According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed. A data queue coupled to a command queue is arranged to store a time indicating when the data transfer will appear on the data bus between the controller for an already issued request to the target device as well as arranged to store the burst bit and the read/write bit (r/w). The system also includes a collision detector coupled to the data queue and the command queue arranged to detect the possible collisions on the data bus between the issued command that is stored in the command queue and already issued commands that are stored in the data queue. A queues and link controller is coupled to the collision detector and the data queue and the command queue and is arranged to store and reorder commands to be issued wherein the controller calculates the new issue time of commands as well as a time when the data appears on the data bus.

Abstract: According to the present invention, an apparatus for prioritizing access to external devices includes a request queue suitably arranged to store any number of reqeusting device requests of the external devices, a request queue controller unit coupled to the request queue suitably arranged to fetch any of the requests stored therein, a responds queue suitably arranged to store any number of responses from the the external devices.

Abstract: A method of dynamically changing draining priority in a first-in/first out (“FIFO”) device to prevent over-run errors is described. The method includes the steps of detecting data received in the FIFO, asserting a request to drain the FIFO, detecting when an amount of data received in the FIFO has reached a predetermined high watermark value, and asserting a higher priority request to drain the FIFO. The method further includes the steps of detecting when the amount of data received in the FIFO has fallen below the predetermined high watermark value, maintaining assertion of the higher priority request, detecting when the amount of data in the FIFO has fallen below a predetermined hysteresis value, and deasserting the higher priority request to drain the FIFO.

Abstract: A method and apparatus for communicating a plurality of commands from a first device to a second device over a data communication link coupling the first and second devices, the plurality of commands including at least a first command and a second command. The first and second commands are transmitted over the data communication link from the first device to the second device in a single data transmission such that only a single propagation delay through the data communication link is incurred in transmitting both the first and second commands over the data communication link.

Abstract: Data processing apparatus is described comprising a processor and at least one peripheral device. The processor is arranged to service the peripheral device either in an interrupt mode in which the peripheral device is serviced in response to interrupt signals generated by the peripheral device or in a timed mode in which the peripheral device is periodically polled and serviced if required. The apparatus has a dynamic switching arrangement for switching from the interrupt mode to the timed mode depending upon conditions dynamically determined within the apparatus, at least one of said conditions being that the rate at which the peripheral device generates interrupt signals exceeds a predefined or programmable threshold frequency. The rate of polling in the timed mode is less than the threshold frequency.

Abstract: A recording apparatus is disclosed that, in use, is connected with a host apparatus, receives recording information from the host apparatus by direct memory access ("DMA") and can print received recording information by using a recording head. A first memory access circuit receives recording information from the host apparatus by DMA. A second memory access circuit supplies received recording information to the recording head with a timing appropriate for recording, using DMA. A priority circuit controls the respective priorities assigned to various types of DMA to ensure that all types of DMA demands can be accommodated within an acceptable length of time.

Abstract: The present invention relates to a slot control method of a multi-port network switch and a switch structure therefor. More particularly, the present invention relates to a slot control method of a shared memory structure with a fixed sequence and a dynamic slot effect. According to the present invention, a slot processor is provided in a slot controller of a network switch for controlling and sequentially allowing a plurality of transportation ports connected to the slot controller to perform data transmission in a fixed round-robin manner while a maximum allowable slot time is set. The slot controller continuously detects whether active transportation port sends an operation request signal or whether the maximum allowable slot time is exceeded. If there is no operation request signal or the allowable slot time is exceeded, data transmission of the next transportation port is allowed and performed immediately, thereby reducing the packet latency.

Abstract: A system and method is provided for enhancing the efficiency with which commands from and initiating device to a resource are processed by the resource. The system includes a command queue, a plurality of command reorder slots coupled to the command queue, and command selection logic coupled to the resource and the command reorder slots. Commands ready for processing are loaded into the command reorder slots, and the command selection logic applies an efficiency criterion to the loaded commands. A command meeting the efficiency criterion is transferred to the resource for processing. The system may also include response reordering logic, which is coupled to the command reorder logic. The response reorder logic returns to original command order data provided in response to reorder read commands.

Abstract: An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines, before the end of a prior interrupt service routine for a prior interrupt, a predicted interrupt time point when a subsequent interrupt will be generated by the at least one peripheral device. The host system operates in a polling mode if the predicted interrupt time point is before a predetermined time period after the end of the prior interrupt service routine. Thus, the host system avoids the processing resources needed for context switching time when the subsequent interrupt is generated closely in time from the prior interrupt. The host system operates in an interrupt mode if the predicted interrupt time point is after the predetermined time period after the end of the prior interrupt service routine.

Abstract: A shared resource lock mechanism is provided which enables processors in a multi-processor environment which each share common resources to obtain locks on those resources. The lock mechanism also includes a reserve feature which provides a mechanism for a processor to maintain a lock on a resource for several input/output cycles. The lock mechanism combines the lock feature and the reserve feature in a single structure. This combination allows a processor to manipulate both the lock data and reserve data in a single transaction. Thus, in transactions requiring manipulation of both the lock and reserve elements, overhead is significantly reduced. In addition a unification of software routines which manipulate the lock and reserve data is achieved.

Abstract: A dynamic allocation system and method is provided for allocating memory bandwidth associated with a store and forward memory communicating between a node processsor and a network. Dynamic allocation is controlled by a state machine in a network adapter, which monitors on a real time basis the active users of the network adapter memory, the node processor writing or reading adapter memory, the network sending port, and the network receiving port. Bandwidths are allocated to users with instant response to user bandwidth demand changes. Programmable options allow a node processor to control bandwidth allocations for various user scenarios.

Abstract: An interrupt controller comprises a plurality of interrupt handling elements that are given different identification numbers for identification to which priorities are assigned. A first priority encoder accepts a plurality of level signals which are given different level numbers respectively representing the priorities assigned to the identification numbers, and then encodes the level number assigned to the highest-priority level signal included among all level signals at a low potential so as to generate an interrupt level number representing the encoded level number.

Abstract: A system and method for dynamically resizing queues used in a network switch to accommodate potential congestion situations without experiencing data loss. In one embodiment, partition pointer registers are used to indicate when resizing is desirable. The control logic then determines when it is safe to update the size of the queue such that no data loss occurs and timely updates the queue size.

Abstract: A round robin arbitration circuit arbitrating N requests has a register storing one of N values, a priority encoder selecting one of N priority patterns according to the value in the register and assigning priorities to the requests based on the selected priority pattern, thereby conducting arbitration between the requests, a circuit updating the value in the register among the N values in a predetermined order synchronously with the arbitration, and a circuit updating the value in the register among the N values in the predetermined order at regular intervals that are asynchronous with the arbitration. At the regular intervals that are asynchronous with the arbitration, a jump is made in the predetermined updating order of the values to be set in the register. Accordingly, even if live-lock occurs, it will be solved when such a jump is made to make the number of priority patterns disagree with the number of requests issued in a loop.

Abstract: The system and method store data into disk devices without loss of data, even when write requests having time limits are concentrated on a specific disk. When a write request for a given disk device is issued, if it is determined that some of this write request and other access requests having time limits for this disk device would not be executed within the respective time limits, the system writes the data temporarily into another disk device.

Abstract: A shared resource access priority encoding/decoding and arbitration scheme takes into account varying device requirements, including latency, bandwidth and throughput. These requirements are stored and are dynamically updated based on changing access demand conditions.

Abstract: A communication control system provides dynamic centralized control of subsystem communications. In a preferred embodiment, a dedicated subsystem communications coordinator is coupled to a main control bus which is utilized for subsystem communication. The coordinator is further coupled to each subsystem for enabling subsystem communication. The coordinator preferably assigns each pending communication a time-based transfer-window channel designation which, while asserted on the control lines of the main control bus, signals corresponding enabled subsystems to transfer data. The coordinator further preferably monitors all subsystem communications for limiting message length and for continuously determining the most effective main control bus utilization according to current system-wide communications needs.

Abstract: The present invention relates to a peripheral control system for controlling at least one peripheral device. The peripheral control system comprises a first computer electrically connected to a peripheral device comprising a memory for storing programs and data, and a processor for executing the programs stored in the memory; at least one peripheral driver program stored in the memory in an executable file format for driving the peripheral device. The peripheral driver program comprises a DDE (Dynamic Data Exchange) module; a peripheral management module (TWAIN) stored in the memory in a subroutine file format for managing the peripheral driver program, the peripheral management module comprising another DDE module for communicating with the DDE module of the peripheral driver program in standard DDE protocol; and at least an application program stored in the memory in an executable file format.

Abstract: A master (1) and a slave (3) are connected via a transmission line (5) for sending a clock CL; another transmission line (6) for bidirectionally sending data DT; and still another transmission line (7) for sending a control signal CE. Having turned a control signal CE into "L," the master (1) transmits an address code as data DT to the slave (3). Referring to the content of the transmitted address code, the slave (3) detects whether it is a data transmission from the master (1) to the slave (3) or vice versa. While a control signal CE remains "H," data transmission takes place. Data output from the slave (3) to the data line (6) is managed by a bus driver (22). The bus driver (22) is turned off during a period from when the clock CL became "H" to when a control signal CE becomes "L" after data transmission so that data transmission from the master (1) will not be adversely affected.

Abstract: A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is associated with a priority weight that indicates a probability that the associated requester will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requesters. In response to the current priorities of the requesters, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.

Abstract: The invention is directed to a stability control system for an automatic control system, which includes a controlled system, a measuring unit for measuring a response characteristic of the controlled system, and a computing unit for processing the response characteristic to obtain a standard frequency transfer function and a varied frequency transfer function with a permissive variation to the standard frequency transfer function. A band division unit is provided for dividing the standard frequency transfer function and the varied frequency transfer function into a plurality of bands, respectively. A modeling unit is provided for mathematically approximating the standard frequency transfer function for each band and the varied frequency transfer function for each band, to obtain a standard approximate model and a varied approximate model, respectively. A variation computing unit is provided for computing a variation of the varied approximate model to the standard approximate model for each band.