Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a plurality of fetch requests, determine a first number of requests, second number of requests, and a third number of requests of the plurality of fetch requests, and balance an execution of the first number of requests, the second number of requests, and the third number of requests so that a first ratio of the data requests to the PRP requests and a second ratio of the data requests to the HMB requests is about 1. The plurality of fetch requests includes PRP requests, HMB requests, and data requests. The first number of requests corresponds to a number of the PRP requests. The second number of requests corresponds to a number of the HMB requests. The third number of requests corresponds to a number of the data requests.

Abstract: A network device may communicate with another network device via a media access control security (MACsec) key agreement (MKA) communication link, wherein an MKA session has been established between the network device and the other network device. The network device may determine that the other network device is unavailable. The network device may cause, based on determining that the other network device is unavailable, an MKA state of the network device to be placed in a paused state. The network device may receive, after causing the MKA state of the network device to be placed in the paused state, a packet from the other network device via the MKA communication link. The network device may determine, based on the packet, that the MKA session has not ended. The network device may continue, based on the MKA session having not ended, the MKA session by reactivating the MKA state.

Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

Abstract: A data management and storage (DMS) cluster of peer DMS nodes manages data of an application distributed across a set of machines of a compute infrastructure. A DMS node associates a set of machines with the application, and generates data fetch jobs for the set of machines for execution by multiple peer DMS nodes. The DMS node determining whether each of the data fetch jobs for the set of machines is ready for execution by the peer DMS nodes. In response to determining that each of the data fetch jobs is ready for execution, the peer DMS nodes execute the data fetch jobs to generate snapshots of the set of machines. The snapshots may be full or incremental snapshots, and collectively form a snapshot of the application.

Abstract: A computer architecture for graph processing employs a high-bandwidth memory closely coupled to independent processing elements for searching through a graph using a first set of processing elements operating simultaneously to determine neighbors to a current frontier and second processing elements operating simultaneously to determine a next frontier, this process being repeated to search through graph nodes.

Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.

Abstract: Techniques for background task scheduling based on shared background bandwidth are described. A method for background task scheduling based on shared background bandwidth may include receiving a request to perform one or more background tasks on a storage server of a storage service in a provider network, determining a priority of each of the one or more background tasks, wherein each background task is associated with a size parameter and a temporal parameter, and wherein the priority of each of the one or more background tasks is based at least on its associated size parameter and temporal parameter, determining a task type associated with each background task, adding each background task to one of a plurality of task queues associated with different task types, wherein each task queue is associated with a bandwidth allocation, and scheduling the one or more background tasks to be performed based on their priority and the bandwidth allocation.

Abstract: Methods, apparatus, systems and articles of manufacture to reduce computing device power consumption are disclosed. Examples determine an idle period based on hardware residency of the computing device, and set a timer to wake up a central processing unit (CPU) from a low power idle state after the idle period, the CPU to exit the low power idle state in response to expiration of the idle period.

Abstract: A mobile game device and a game console share an image file relating to a game; the mobile game device and the game console are connected so as to be able to transmit data with each other via a wire or wirelessly, and the game console is connected to an image-file-providing server retaining an image file via a network; the game console acquires an image file from the image-file-providing server and the mobile game device acquires an image file from the game console, by which the image file is shared between the game instruments.

Abstract: A microcomputer is provided for each of industrial apparatuses to synchronously control them and includes a CPU, a peripheral module, and a communication interface. The peripheral module controls an external apparatus based on a specified control parameter. The communication interface includes a time register that is synchronized with the other apparatuses in time series. The communication interface issues a CPU interrupt and a peripheral module interrupt to the CPU and the peripheral module, respectively, if a successively settled correction time matches the time register. In response to the peripheral module interrupt, the peripheral module changes the control parameter from a current value to an update value. In response to the CPU interrupt, the CPU starts an update program to calculate the next update value for the control parameter and writes the calculated value to the peripheral module.

Abstract: Disclosed is an improved approach for managing access to resources by workloads in a computing system. A much more accurate and useful technique is provided for determining disk utilization, and for using the calculated disk utilization to enforce workload constraints and limits. The technique may be used by any application that is attempting to share storage between multiple workloads can use the present solution, as well as any operating system and workload manager that need to manage workloads and resources.

Abstract: A movable barrier operator transmits a message to a remote peripheral platform and, upon determining that the remote peripheral platform is presently able to carry out a given functionality, responsively permits a particular function to be carried out by the movable barrier operator. Conversely, upon determining that it cannot be ascertained whether the remote peripheral platform is presently able to carry out the given functionality, the movable barrier operator responsively prevents the movable barrier operator from carrying out the particular function. Also, upon detecting that a targeted remote platform does not acknowledge a previously re-transmitted message and further upon detecting that this same remote platform has also not acknowledged a subsequent wirelessly-transmitted second message, the system can switch to automatically retransmitting that second message a lesser number of times than would otherwise be required.

Abstract: A processing system includes an interchip interface that comprises an interchip interface module having an arbiter to allocate a dedicated time slice in every fixed number of time slices, to assign a first priority to store data item(s) from a first-type channel having a first datapath width in memory during the dedicated time slice. In the remaining time slices of the fixed number of time slices, the arbiter further arbitrates among multiple channels of one or more types other than a first type, where the multiple channels correspond to at least one datapath width different from the first datapath width, and channels with wider datapath win the arbitration. The arbiter further arbitrates among two or more channels of the same type if a certain type of channel(s) wins the arbitration in a time slice. A method for implementing the same is also disclosed.

Abstract: In embodiments of an idle time service, it can be determined that processing on a device is in an idle state. An execution duration of applications that are scheduled to be executed by a processor of the device can then be extended to reduce power consumption by the device. In other embodiments, it can be determined that an application configured to execute on a device is a background application. The execution duration of the background application can then be extended to reduce power consumption by the device.

Abstract: A storage apparatus capable of achieving both an improvement in efficiency of data transfer processing and an improvement in availability and a method of controlling the storage apparatus are provided.

Abstract: A storage apparatus capable of achieving both an improvement in efficiency of data transfer processing and an improvement in availability and a method of controlling the storage apparatus are provided.

Abstract: Systems and methods are described for arbitrating access of a communication bus. In one embodiment, a method includes performing steps on one or more processors. The steps include: receiving an access request from a device of the communication bus; evaluating a bus schedule to determine an importance of the device based on the access request; and selectively granting access of the communication bus to the device based on the importance of the device.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.

Abstract: Systems and methods are provided that may be implemented to manage machine-specific System Profile Unique Data (SPUD) information for one or more information handling systems. Such SPUD information may be managed and transported through in-band and/or out-of-band processing and communications, and may be employed to make restoration of machine-specific data possible either through network data communications and/or local system data communications.

Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

Abstract: A processing system includes an interchip interface that comprises an interchip interface module having an arbiter to allocate a dedicated time slice in every fixed number of time slices, to assign a first priority to store data item(s) from a first-type channel having a first datapath width in memory during the dedicated time slice. In the remaining time slices of the fixed number of time slices, the arbiter further arbitrates among multiple channels of one or more types other than a first type, where the multiple channels correspond to at least one datapath width different from the first datapath width, and channels with wider datapath win the arbitration. The arbiter further arbitrates among two or more channels of the same type if a certain type of channel(s) wins the arbitration in a time slice. A method for implementing the same is also disclosed.

Abstract: A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can change the execution state of the first thread. Reservation circuitry of the processing device that was executing the first thread monitors the reservation. In the event that the reservation cleared, such as by the second thread modifying data at the predetermined memory address, the first thread is reinstated to its prior execution state. By using a hardware reservation mechanism to monitor for clearing of a set reservation, repeated memory accesses to the memory address by the first thread can be minimized or avoided while in the polling loop and other threads can be allowed to execute at the processing device with reduced interference from the waiting thread.

Abstract: Embodiments relate to systems and methods for implementation on a mobile device to force the mobile device into a secure state upon detection or determination of a triggering event. Once it is determined that a triggering event has occurred, each application operating on the mobile device is caused to immediately unreference sensitive objects and a secure garbage collection operation is performed upon the unreferenced sensitive objects to render data associated therewith unreadable. The mobile device is then caused to enter a secure state, in which the mobile device cannot be accessed without authorization. A microprocessor within the mobile device is configured to determine the existence of the triggering event according to a configuration data structure and to perform the secure garbage collection.

Abstract: Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words of one or more data packets. A plurality of one-port memories store the received data portions. Each one-port memory has a width W segmented into S portions of width W/S, where W/S is related to N. A second logic module provides one or more N-bit data words, from the one-port memories, corresponding to the received m N-bit data portions. In a sequence of clock cycles, the data portions are alternately transferred from corresponding segments of the one-port memories in a round-robin fashion, and, for each clock cycle, the second logic module constructs data out read from the one-port memories.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.

Abstract: A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage device in communication with the storage controller, where that data storage device reservation is held by a first communication path group comprising a first plurality of communication paths configured in the communication link. If the method detects a failed communication path configured in the first communication path group, the method configures a second communication path group by removing the failed communication path from the first communication path group, wherein the second communication path group maintains the data storage device reservation.

Abstract: An image forming apparatus capable of both normal printing and special-purpose printing includes a first identification unit, a second identification unit, and a selection unit. The first identification unit identifies a type of print data. The second identification unit identifies a type of print material. The selection unit selects a print resource in accordance with a combination of the type of print data identified by the first identification unit and the type of print material identified by the second identification unit. The selection unit selects the print resource so as to prevent unauthorized printing from being performed when the print data is for special-purpose printing.

Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.

Abstract: Methods and apparatus for efficiently transporting data through network tunnels. In one embodiment, a tunneled device advertises certain capabilities to peer devices of a network, and discovers capabilities of peer devices of the network. In a second embodiment, each device of a tunneled network derives a network parameter from a transit protocol parameter for use in data networking.

Abstract: A priority control device comprises a clock generator for generating a clock signal, a time interval generating unit having a plurality of signal routes and each of the signal routes has a different signal passing time respectively, and a logic control unit coupled to the outputs of the signal routes. The time interval generating unit determines the timing of receiving input signals according to the clock signal. The logic control unit receives the output signals of the signal routes for generating the control signals.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: Method and device for arbitration for time division multiple access using delta-sigma modulation for an integrated circuit are described. A method for arbitrating access to a shared resource among multiple devices includes obtaining a first arbitration factor. The first arbitration factor is first delta-sigma modulated to produce a first slot signal. The first slot signal is for Time Division Multiple Access-arbitrated access to the shared resource.

Abstract: In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.

Abstract: A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made.

Abstract: Architecture that allows programmatic association of devices to sessions and redirects input to the desired session. When the solution is active, input from the devices is not realized by the standard operating system input stack, thereby allowing even reserved key sequences such as Ctrl-Alt-Del to be intercepted and redirected to a desired session. Moreover, in addition to redirecting input to a specific session, the architecture facilitates the filtering of input from unwanted/unmapped devices, the interception and filtering or redirection of reserved key sequences such as Ctrl-Alt-Del, and the maintenance of input state for each session.

Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.

Abstract: Transmission of probe configuration data is initiated upon recognition by the probe of a prescribed condition. Probe configuration data protocol includes a data frame, subdivided into a desired number of time slots. Unlike measurement data protocol, where inter-pulse pair timing within a slot varies based on a magnet position or temperature sensor resistance, configuration data protocol in accordance with the invention uses fixed inter-pulse timing to represent the various states of digital data. In such manner, at least a portion of the time slots making up the particular data frame can be used for containing data sent from the probe, and which can then be interpreted by the receiving processing device as at least one bit of binary code allocated to each individual slot of the portion of time slots.

Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: In a communication apparatus, a write controller writes received data in a temporary memory which serves as short-time storage. A read controller reads data out of the temporary memory. A discard controller controls discard operation of the data read out of the temporary memory.

Abstract: A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a periodic authorization signal to cause the memory access controller to remove the inhibition and write a predetermined amount of data to the memory through a data bus, and 2) releasing the data bus following writing of the predetermined amount of data to the memory by inhibiting the memory access controller from writing further data.

Abstract: A disk drive is disclosed including a disk comprising a plurality of refresh zones, and a head actuated over the disk. The disk drive further comprises control circuitry for receiving access commands from a host. The control circuitry refreshes a refresh zone in a plurality of segments with an interval between each segment, and processes at least one of the access commands during the interval between at least two of the segments, wherein a size of each segment and the interval ensures an average throughput of access commands received from the host does not fall below a first threshold.

Abstract: Provided are a human interface device and a wireless communication method thereof. The wireless communication method of the human interface includes the steps of: setting up an occupancy channel of the host digital terminal and the wireless input unit by communicating data for setting up the occupancy channel through the emergency channel; transmitting, at the wireless input unit, operation data through the occupancy channel, and receiving, at the host digital terminal, the operation data; and when the operation data is not generated until a predetermined time lapses, enabling the wireless input unit and the host digital terminal to operate in an operation standby state, and confirming whether there is interference on the occupancy channel. Accordingly, efficiency of a frequency band is increased, and cost and size of the product can be reduced.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: A method for employing a second bus controller on a data bus having a first bus controller including: (a) recording appearances of predetermined character groups on the data bus; (b) noting patterns of the appearances preceding a qualifying quiet period on the data bus; a qualifying quiet period being a time interval having a duration greater than a predetermined duration with no traffic on the data bus; (c) employing the patterns to determine probability of occurrence of a qualifying quiet period following at least one pattern; and (d) permitting the second bus controller to control operation of the data bus during a respective qualifying quiet period when the probability of occurrence for the respective qualifying quiet period is greater than a predetermined value.

Abstract: A device interface circuit unit transfers a command and data in packet format between the unit and the host. A transport layer is provided with a receive FIFO, a command detection circuit and a send FIFO, and an application layer is provided with a receive task file register and a send task control file register. An available time is generated for each break point of a packet during data transfer in order to receive another command packet from the host. When the command packet is received from the host in the available time during data transfer, the data transfer is suspended and the received command is decoded to execute a process for continuing or canceling the data transfer, after which the data transfer is resumed.

Abstract: A master device for communicating with a number of slave devices through a communication link having a limited resource. The master device comprises a transceiver adapted for communicating with the slave devices on the communication link and a controller adapted for detecting the number of slave devices. The controller is adapted for determining an individual resource associated with a slave device to be consumed from the communication link, wherein a sum of the individual resources of all slave devices is lower than the limited resource and wherein the transceiver is adapted for assigning the individual resources to the associated slave devices.

Abstract: A mobile hub is proposed, the mobile hub includes a circular buffer for storing events, a timer for monitoring the storage period of an event stored in the buffer, and an event manager designed for discarding an event from the buffer when a time-out of the associated timer is exceeded. As no event can block the buffer any more a small-scale buffer can be used for the mobile hub.