Data Compression And Expansion Patents (Class 710/68)
  • Patent number: 11966597
    Abstract: A data service implements a configurable data compressor/decompressor using a recipe generated for a particular data set type and using compression operators of a common registry (e.g., pantry) that are referenced by the recipe, wherein the recipe indicates at which nodes of a compression graph respective ones of the compression operators of the registry are to be implemented. The configurable data compressor/decompressor provides a customizable framework for compressing data sets of different types (e.g., belonging to different data domains) using a common compressor/decompressor implemented using a common set of compression operators.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: April 23, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Dmitri Pavlichin, Shubham Chandak, Itschak Weissman, Christopher George Burgess
  • Patent number: 11922014
    Abstract: According to one embodiment, a controller of a memory system manages a first table maintaining a relationship between a logical address and a physical address, compresses first data corresponding to a first address of a write command, specifies a size of second data obtained by compressing the first data, determines allocation of the second data on a memory based on the size of the second data, stores a second address corresponding to a physical area where a head of the second data is stored and a physical area number used to store the second data in an entry of the first logical address in the first table, and stores the first address, offset of a position of a leader of the second data in the physical area, and the size of the second data in the physical area.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Keiri Nakanishi, Kensaku Yamaguchi, Takashi Takemoto
  • Patent number: 11917003
    Abstract: Examples disclosed herein relate to propagating changes made on a file system volume of a primary cluster of nodes to the same file system volume also being managed by a secondary cluster of nodes. An application is executed on both clusters, and data changes on the primary cluster are mirrored to the secondary cluster using an exo-clone file. The exo-clone file includes the differences between two or more snapshots of the volume on the primary cluster, along with identifiers of the change blocks and (optionally) state information thereof. Just these changes, identifiers, and state information are packaged in the exo-clone file and then exported to the secondary cluster, which in turn makes the changes to its version of the volume. Exporting just the changes to the data blocks and the corresponding block identifiers drastically reduces the information needed to be exchanged and processed to keep the two volumes consistent.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: February 27, 2024
    Assignee: VMware, Inc.
    Inventors: Richard Spillane, Yunshan Luke Lu, Wenguang Wang, Maxime Austruy, Christos Karamanolis, Rawlinson Rivera
  • Patent number: 11895629
    Abstract: A multiple access method includes: obtaining, by a user equipment (UE), first source information; extracting a semantic feature of the first source information to obtain a first semantic feature sequence; performing a joint source-channel coding on the first semantic feature sequence to obtain a first semantic information sequence; mapping the first semantic information sequence into preset time-frequency resources of an uplink multiple access channel; and transmitting the first semantic information sequence through the uplink multiple access channel.
    Type: Grant
    Filed: October 12, 2023
    Date of Patent: February 6, 2024
    Assignee: Beijing University of Posts and Telecommunications
    Inventors: Kai Niu, Zijian Liang, Ping Zhang, Jincheng Dai, Chao Dong, Xiaodong Xu, Chen Dong
  • Patent number: 11892957
    Abstract: A system is disclosed. An upstream interface enables communication with a processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for data, and a storage device acceleration module to assist the acceleration module in executing the acceleration instruction.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 6, 2024
    Inventors: Ramdas P. Kachare, Fred Worley, Harry Rogers, Wentao Wu, Nagarajan Subramaniyan
  • Patent number: 11853105
    Abstract: A system is disclosed. An upstream interface enables communication with a processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for data, and a storage device acceleration module to assist the acceleration module in executing the acceleration instruction.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: December 26, 2023
    Inventors: Ramdas P. Kachare, Fred Worley, Harry Rogers, Wentao Wu, Nagarajan Subramaniyan
  • Patent number: 11699477
    Abstract: A semiconductor device may implement a command-over-data function on a multi-level signaling data bus architectures. The multi-level signaling data bus architecture may support a multi-level communication architecture that includes a plurality of channels each including conversion of M bitstreams to N multi-level signals, where M is greater than N. A bitstream includes a plurality of bits provided serially, with each bit of the bitstream provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus, and to transmit commands using at least a second assigned state of the data bus.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 11693820
    Abstract: The present disclosure provides a cooperative access method, system, and architecture of an external storage.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: July 4, 2023
    Assignees: VeriSilicon Microelectronics (Chengdu) Co., Ltd., VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventor: Yongliang Li
  • Patent number: 11681611
    Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Omid Azizi, Amin Firoozshahian, Andreas Kleen, Mahesh Madhav, Mahesh Maddury, Chandan Egbert, Eric Gouldey
  • Patent number: 11651112
    Abstract: An apparatus to facilitate enabling stateless accelerator designs shared across mutually-distrustful tenants is disclosed. The apparatus includes a fully-homomorphic encryption (FHE)-capable circuitry to establish a secure session with a trusted environment executing on a host device communicably coupled to the apparatus; generate, as part of establishing the secure session, per-tenant FHE keys for each tenant utilizing the FHE-capable circuitry, the per-tenant FHE keys utilized to encrypt tenant data provided to an FHE-capable compute kernel of the FHE-capable circuitry; process tenant data that is in an FHE-encrypted format encrypted with a per-tenant FHE key of the per-tenant FHE keys; and store the tenant data that is in the FHE-encrypted format encrypted with the per-tenant FHE key of the per-tenant FHE keys.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: May 16, 2023
    Assignee: INTEL CORPORATION
    Inventors: Alpa Trivedi, Carlos Rozas
  • Patent number: 11609844
    Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 21, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Keiri Nakanishi, Konosuke Watanabe, Kohei Oikawa, Daisuke Iwai
  • Patent number: 11507299
    Abstract: An electronic device according to various embodiments of the present invention comprises a host device and a block device electrically connected to the host device, wherein the block device comprises a first memory and a controller electrically connected to the first memory, and the controller receives a write request for first data form the host device, determines whether the first data is pattern data configured in a form in which an assigned number of bit values are repeated, and, in response to the first data being determined to be the pattern data, controls the first memory to store the assigned number of bit values of the first data in a logical to physical mapping table after mapping the assigned number of bit values to a logical address indicated by the write request.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 22, 2022
    Inventors: Manjong Lee, Changheun Lee
  • Patent number: 11507511
    Abstract: Techniques for storing data involve estimating a hit ratio of a digest cache associated with a target storage device, the digest cache recording a digest of data that is stored in the target storage device after preprocessing; generating, according to a determination that the hit ratio is lower than a predetermined threshold, a digest for target data to be stored and performing the preprocessing; and storing, according to a determination that the digest of the target data is missing in the digest cache, the preprocessed target data in the target storage device, and recording the digest of the target data in the digest cache. Such techniques can achieve good system performance in both cases of high data repetition and low data repetition.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: November 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Leihu Zhang, Chen Gong, Shuo Lv
  • Patent number: 11500636
    Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Joseph Nuzman, Jonas Svennebring, Doddaballapur N. Jayasimha, Samantika S. Sury, David A. Koufaty, Niall D. McDonnell, Yen-Cheng Liu, Stephen R. Van Doren, Stephen J. Robinson
  • Patent number: 11398260
    Abstract: A network device includes a linear feedback shift register circuit and a value updating circuit. The linear feedback shift register circuit is configured to perform an auto crossover mechanism according to at least one clock signal and a plurality of first bits, in order to control at least one port of a first interface circuit to connect with a second interface circuit. The value updating circuit is configured to perform at least one of a plurality of operations according to exclusive information. The plurality of operations includes: generating a plurality of initial values, in which the value updating circuit is configured to utilize the plurality of initial values to update at least one partial bits of the plurality of first bits; or setting a period of the at least one clock signal, in which the exclusive information includes operational information or production information of the network device.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: July 26, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Zhi-Dao Wang, Wei Zhao
  • Patent number: 11394636
    Abstract: Systems and methods are described to provide mechanisms for establishing a private anonymity network that allows network packets to be forwarded via an obfuscated network signal path that is highly configurable. The techniques described herein may allow users to establish a private obfuscated network signal path that utilizes a number of access points, load balancers, and packet forwarders that can collectively provide path randomization and node ephemerality in a manner that may not be feasible or available in public anonymity networks.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: July 19, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: David Walker, Andrew Langhorn
  • Patent number: 11379597
    Abstract: Method and system for determination of authenticity of an electronic document by comparing the document in question with itself at a later date or with a copy thereof, which method comprises two phases wherein the first phase is the entry of the original document and the second phase is the verification of the identity between the document to be authenticated and the original one. The method requires a double levelled system comprising of a satellite system accessible by the user and a central core system. Only values which are derived from the document in a predetermined way are stored in the core system and the core system generates an individual first code which is associated with the document. During verification a transformed control value is generated in the same way as previously from the document and the associated code, then based on the first code following a transformation access is provided to the transformed control value stored in the core system.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: July 5, 2022
    Inventors: Ádám Bosznay, Péter Eckhardt, Mihály István Lantos, Csaba Sár, Péter Sütheö
  • Patent number: 11294568
    Abstract: A request to store a file is received, an in response to that request multiple data segments are stored in a buffer memory. A first one of those data segments is selected for migration based on a life expectancy of the first data segment, and is migrated from the buffer memory to another memory. Migrating the first data segment includes generating at least one encoded data segment by encoding the first data segment, storing the first data segment to a location in the another memory, and storing addressing information indicating the location in the another memory.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: April 5, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: Andrew Baptist, Jason K. Resch
  • Patent number: 11290532
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a request for a set of data at a first data storage tier, looking up corresponding metadata to each portion of the requested set of data, using the metadata to recall each of the portions of the requested set of data from object storage, and using the portions of the requested set of data to recompile a master object, the master object having a 1-to-1 mapping to the requested set of data. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 29, 2022
    Assignee: International Business Machines Corporation
    Inventors: Joseph W. Dain, Joseph M. Swingler
  • Patent number: 11263500
    Abstract: A method for designating a given image as similar/dissimilar with respect to a reference image is provided. The method includes normalizing the image. Normalizing includes performing pre-processing and a lossy compression on the given image to obtain a lossy representation. The pre-processing includes at least one of cropping, fundamental extracting, gray scale converting and lower color bit converting. The method also includes comparing the lossy representation of the given image with a reference representation, which is a version of a reference spam image after the reference spam image has undergone a similar normalizing process as normalizing. The method further includes, if the lossy representation of the given image matches the reference representation, designating the given image similar to the reference image. The method yet also includes, if the lossy representation of the given image does not match the reference representation, designating the given image dissimilar to the reference image.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 1, 2022
    Assignee: Trend Micro Incorporated
    Inventors: Jonathan James Oliver, Yun-Chian Chang
  • Patent number: 11258523
    Abstract: Provided are an electronic device for determining failure of a signal path and a component, and a method for operating the electronic device according to various embodiments. The electronic device comprises: at least one connection part for connection to an external device; a first signal path including an amplifier for amplifying a signal transmitted to the outside of the electronic device; a second signal path for obtaining another signal from the outside of the electronic device; an antenna port electrically connected to the first signal path and the second signal path through a filter circuit; and a communication module, wherein the communication module may be configured to transmit a transmission signal through the first signal path to the antenna port, obtain at least a part of the transmission signal through the second signal path, and determine whether the electronic device is defective on the basis of the transmission signal and information associated with at least a part of the transmission signal.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoonkook Son, Yongjun An, Yuseon Lee, Hanyeop Lee, Joosung Kim, Hyoseok Na, Doil Ku, Hyunsang Kang, Juho Van, Chulseung Pyo
  • Patent number: 11200109
    Abstract: Techniques involve in response to receiving, from a failure analysis device, a request for obtaining a to-be-analyzed data block in a set of raw data blocks in a data file related to a failure of an operating system, determining a position of the to-be-analyzed data block in a compressed file for the data file, the request comprising a position of the to-be-analyzed data block in the data file. The techniques further involve determining, based on the position of the to-be-analyzed data block in the compressed file, a compressed data block in the compressed file corresponding to the to-be-analyzed data block. The techniques further involve sending the compressed data block to the failure analysis device for analyzing the failure. Accordingly, the time for analyzing the failure may be saved, the amount of data transmission and the resources occupied by decompression may be reduced, and the processing efficiency may be improved.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: December 14, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Haohan Zhang, Dezheng Zhang, Liangliang Liu, Lei Shi, Wangyuan Li
  • Patent number: 11157290
    Abstract: A method and circuit for waking up an I2C device are disclosed. The method includes determining whether a start signal is received; determining whether a next signal immediately received after the start signal is an address signal when the start signal is received; matching the next signal immediately received after the start signal with an address of the I2C device when the next signal is the address signal; and generating a wake-up signal to wake up the I2C device when the next signal immediately received after the start signal is matched with the address of the I2C device.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 26, 2021
    Assignee: AUTOCHIPS WUHAN CO., LTD.
    Inventors: Huilan Fu, Jie Zhang, Shujie Lu
  • Patent number: 11157423
    Abstract: A pipelined-data-transform-enabled data mover system includes a data mover device coupled to a memory system. The data mover device reads initial data from memory location(s) included in the memory system, and include at least one first data mover element that performs at least one intermediate data transform operation on the initial data in order to produce intermediate data. The data mover device also includes at least one second data mover element that subsequently performs at least one final data transform operation on the intermediate data in order to produce final data. The data mover device then writes the final data to memory location(s) included in the memory system. The data mover device may be configured by a processing system via a single descriptor that configures the data mover device to perform multiple read operations from different memory locations in the memory system in order to read the initial data.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: October 26, 2021
    Assignee: Dell Products L.P.
    Inventor: Shyamkumar T. Iyer
  • Patent number: 11113113
    Abstract: Systems, apparatuses, and methods for efficiently selecting compressors for data compression are described. In various embodiments, a computing system includes at least one processor and multiple codecs such as one or more hardware codecs and one or more software codecs executable by the processor. The computing system receives a workload and processes instructions, commands and routines corresponding to the workload. One or more of the tasks in the workload are data compression tasks. Current condition(s) are determined during the processing of the workload by the computing system. Conditions are determined to be satisfied based on comparing current selected characteristics to respective thresholds. In one example, when the compressor selector determines a difference between a target compression ratio and an expected compression ratio of the first codec exceeds a threshold, the compressor selector switches from hardware codecs to software codecs.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: September 7, 2021
    Assignee: Apple Inc.
    Inventors: Derek R. Kumar, Thomas Brogan Duffy, Jr.
  • Patent number: 11086822
    Abstract: A communication system and methods for data compression and the management of data transmitted between computing devices in a communication network are provided. Compression dictionaries generated from data previously maintained at a recipient computing device and a transmitting computing device are maintained at each respective device. The compression dictionaries are made up of fixed length data chunks from the data previously maintained on the computing device that can be matched to data to be compressed or de-compressed. Data can be transmitted without requiring the exchange of the compression dictionaries between the recipient computing device and the transmitting computing device.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: August 10, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Holger Kraus
  • Patent number: 11055461
    Abstract: Semiconductor device design automation by receiving an initial semiconductor design, identifying scannable cells according to the semiconductor design, determining scannable cell locations, identifying a cluster of scannable cells among the scannable cells according to the locations, forming a scan chain configured to connect at least some of the scannable cells of the cluster, identifying a scan chain cluster including the scan chain logical connections; and generating a scan chain scan-multiplexer location for scan chain clusters.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Manuel Beck, Marvin von der Ehe
  • Patent number: 11048419
    Abstract: A technique for managing storage of compressed data includes generating and enforcing a minimum slot size requirement. The minimum slot size is based at least in part on collected performance metrics that indicate a degree of compressibility of data received, compressed, and written by the data storage system. As new data arrive, the new data are compressed and stored in slots at least as big as the minimum slot size, in many cases effecting an over-allocation of storage space and improving the likelihood that subsequent overwrites will fit into existing slots.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 29, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Yining Si, Kamakshi Viswanadha, Ajay Karri
  • Patent number: 11032577
    Abstract: According to an embodiment, a method may include segmenting a first image into a first block and a second block, generating first compression loss data corresponding to the first block and second compression loss data corresponding to the second block, identifying a first compression property, segmenting a second image into a third block and a fourth block and compressing the second image, wherein the compressing includes compressing the third block according to the first compression property, generating third compression loss data corresponding to the third block, when a difference between the first compression loss data and the third compression loss data meets a first predetermined condition, compressing the fourth block according to the first compression property, and when the difference meets a second predetermined condition, compressing the fourth block according to a second compression property. Other various embodiments are possible as well.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyungju Chun, Sungoh Kim, Youngjo Kim, Hyunhee Park, Arang Lee, Jongbum Choi, Changsu Han, Hajoong Park, Donghyun Yeom
  • Patent number: 11005605
    Abstract: The efficiency of signal transmission is improved. A communication apparatus includes a memory unit, a communication control unit, and an updating unit. A retransmission interval value is stored in the memory unit. The communication control unit transmits a first signal and receives a response signal corresponding to the first signal from a receiver. If the received response signal is a negative response signal, the first signal is retransmitted at a time interval longer than or equal to the retransmission interval value stored in the memory unit, from the transmission of the first signal. The updating unit updates the retransmission interval value stored in the memory unit, according to a time from the transmission of the first signal to the reception of the positive response signal corresponding to the first signal.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 11, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takayuki Suzuki
  • Patent number: 10964358
    Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jason T. Zawodny, Kelley D. Dobelstein, Timothy P. Finkbeiner, Richard C. Murphy
  • Patent number: 10956047
    Abstract: The instant disclosure provides an accelerated computer system and an accelerated method for writing data into discrete pages. The accelerated method includes executing write commands, with each write command including write data and a write address such that the write address corresponds to a write page of the first pages in a sector of a hard drive, identifying whether the write pages are successive according to the write addresses, acquiring stored data by reading the sector according to the write addresses if the write pages are discrete, writing the data stored in the first pages into the second pages of a memory, writing write data bit by bit into the second pages according to the write addresses, and writing the data stored in the second pages into the first pages.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 23, 2021
    Assignee: ACCELSTOR TECHNOLOGIES LTD
    Inventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang
  • Patent number: 10956241
    Abstract: A computer program product can include a non-transitory computer readable storage medium storing a unified container. The unified container can include a header structure, wherein the header structure has a fixed length and specifies a number of section headers included in the unified container. The unified container can include a plurality of section headers equivalent to the number of section headers specified in the header structure. The unified container can include a plurality of data sections corresponding to the plurality of section headers on a one-to-one basis. The plurality of data sections includes a first data section including a hardware binary and a second data section including a software binary. The hardware binary and the software binary are configured to program a programmable integrated circuit. Each section header specifies a type of data stored in the corresponding data section and specifies a mapping for the corresponding data section.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 23, 2021
    Assignee: Xilinx, Inc.
    Inventors: Hem C. Neema, Sonal Santan, Soren T. Soe, Stephen P. Rozum, Nik Cimino
  • Patent number: 10929040
    Abstract: In a half-compressed RAID 1 system a first copy of a data set is maintained in an uncompressed state and a second copy of the data set is maintained in a compressed state, where corresponding compressed and uncompressed blocks are stored on different physical devices. The result is RAID 1 reliability with storage space consumption similar to RAID 5-3+1. Compression striping in which the compressed and uncompressed data is distributed across two or more storage devices can be used to reduce data access response time. Further, delayed compression can be used to reduce the time required to perform WRITE ops. Compression may also be performed based on resource availability or storage tier hierarchy.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: February 23, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: Michael Trachtman
  • Patent number: 10915445
    Abstract: A method, computer readable medium, and system are disclosed for a distributed cache that provides multiple processing units with fast access to a portion of data, which is stored in local memory. The distributed cache is composed of multiple smaller caches, and each of the smaller caches is associated with at least one processing unit. In addition to a shared crossbar network through which data is transferred between processing units and the smaller caches, a dedicated connection is provided between two or more smaller caches that form a partner cache set. Transferring data through the dedicated connections reduces congestion on the shared crossbar network. Reducing congestion on the shared crossbar network increases the available bandwidth and allows the number of processing units to increase. A coherence protocol is defined for accessing data stored in the distributed cache and for transferring data between the smaller caches of a partner cache set.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: February 9, 2021
    Assignee: NVIDIA Corporation
    Inventors: Wishwesh Anil Gandhi, Tanmoy Mandal, Ravi Kiran Manyam, Supriya Shrihari Rao
  • Patent number: 10895987
    Abstract: Disclosed are a memory compression method of an electronic device and an apparatus thereof. The method for compressing memory in an electronic device may include: detecting a request for executing the first application; determining whether or not the memory compression is required for the execution of the first application; when the memory compression is required, compressing the memory corresponding to an application in progress in the background of the electronic device; and executing the first application.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 19, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoungik Kang, Jinyoung Park, Heesub Shin, Seungwook Lee
  • Patent number: 10896026
    Abstract: A data conversion apparatus includes a memory and a processor coupled to the memory. The processor is configured to acquire first data. The processor is configured to acquire a part of second data corresponding to a part of the first data. The processor is configured to search for a combination of processes based on an attribute indicating a processing time for performing each process among processes for converting the part of the first data into the part of the second data. The combination of processes is used for converting a remainder of the first data into a remainder of the second data. The processor is configured to output the combination of processes.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: January 19, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Yui Noma
  • Patent number: 10866888
    Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Omid Azizi, Amin Firoozshahian, Andreas Kleen, Mahesh Madhav, Mahesh Maddury, Chandan Egbert, Eric Gouldey
  • Patent number: 10853234
    Abstract: A memory controller controls first and second memory, and includes a control unit. In response to a first write command from a host, which designates a logical address for first data to be written to the first memory, the control unit determines whether mapping of the logical address is presently being managed in a first mode with a first cluster size or a second mode with a second cluster size that is smaller than the first cluster size, changes first mapping data for the logical address stored in a first table in the second memory, from the first cluster size to the second cluster size, if the mapping of the logical address is being managed in the first mode and the first mapping data can be compressed at a ratio lower than a first compression ratio, and writes the first data to a physical address of the first memory.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Sho Kodama
  • Patent number: 10838862
    Abstract: Aspects disclosed herein include memory controllers employing memory capacity compression, and related processor-based systems and methods. In certain aspects, compressed memory controllers are employed that can provide memory capacity compression. In some aspects, a line-based memory capacity compression scheme can be employed where additional translation of a physical address (PA) to a physical buffer address is performed to allow compressed data in a system memory at the physical buffer address for efficient compressed data storage. A translation lookaside buffer (TLB) may also be employed to store TLB entries comprising PA tags corresponding to a physical buffer address in the system memory to more efficiently perform the translation of the PA to the physical buffer address in the system memory. In certain aspects, a line-based memory capacity compression scheme, a page-based memory capacity compression scheme, or a hybrid line-page-based memory capacity compression scheme can be employed.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: November 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Mattheus Cornelis Antonius Adrianus Heddes, Natarajan Vaidhyanathan, Colin Beaton Verrilli
  • Patent number: 10812582
    Abstract: Examples disclosed herein relate to propagating changes made on a file system volume of a primary cluster of nodes to the same file system volume also being managed by a secondary cluster of nodes. An application is executed on both clusters, and data changes on the primary cluster are mirrored to the secondary cluster using an exo-clone file. The exo-clone file includes the differences between two or more snapshots of the volume on the primary cluster, along with identifiers of the change blocks and (optionally) state information thereof. Just these changes, identifiers, and state information are packaged in the exo-clone file and then exported to the secondary cluster, which in turn makes the changes to its version of the volume. Exporting just the changes to the data blocks and the corresponding block identifiers drastically reduces the information needed to be exchanged and processed to keep the two volumes consistent.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: October 20, 2020
    Assignee: VMware, Inc.
    Inventors: Richard Spillane, Yunshan Luke Lu, Wenguang Wang, Maxime Austruy, Christos Karamanolis, Rawlinson Rivera
  • Patent number: 10803018
    Abstract: The embodiments described herein relate to managing compressed data to optimize file compression. A first compression is performed on a first set of data to create first compressed data. The first compressed data is stored in one or more blocks of a first compression group. A size of free space of a last block of the first compression group is discovered and calculated. A second compression is performed on a second set of data to create second compressed data. At least a portion of the second compressed data is supplied to the first compression group for padding into the last block in response to determining that the size of the free space is sufficient. An unpadded portion of the second compressed data is stored in one or more blocks of a second compression group.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: M. Corneliu Constantinescu, Leo Shyh-Wei Luan, Wayne A. Sawdon, Frank B. Schmuck
  • Patent number: 10783078
    Abstract: In one aspect, a method includes splitting empty RAID stripes into sub-stripes and storing pages into the sub-stripes based on a compressibility score. In another aspect, a method includes reading pages from 1-stripes, storing compressed data in a temporary location, reading multiple stripes, determining compressibility score for each stripe and filling stripes based on the compressibility score. In a further aspect, a method includes scanning a dirty queue in a system cache, compressing pages ready for destaging, combining compressed pages in to one aggregated page, writing one aggregated page to one stripe and storing pages with same compressibility score in a stripe.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: September 22, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: David Meiri, Anton Kucherov, Vladimir Shveidel
  • Patent number: 10764045
    Abstract: A system receives data of one or more types from one or more sources having distinct identities for storing the data in a distributed storage system. The system stores metadata associated with storing the data in data structures in the distributed storage system. The system selects a portion of the data and a portion of the metadata associated with storing the data in the distributed storage system. The system compresses the selected portions of the data and the metadata, encrypts the compressed data and metadata using a single key or using a separate key for each data type, and stores the encrypted compressed data and metadata in the distributed storage system. The system also encrypts unencrypted metadata and associated data during defragmentation procedure.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 1, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rushi Srinivas Surla, Shane Kumar Mainali, Andrew Edwards, Maneesh Sah, Weiping Zhang
  • Patent number: 10754653
    Abstract: A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed instruction. The memory may be configured as a paged instruction cache to store pages of compressed instructions intermixed with pages of uncompressed instructions. Methods of determining a mix mask for efficiently translating compressed instructions is also described. A genetic method uses pairs of mix masks as genes from a seed population of mix masks that are bred and may be mutated to produce pairs of offspring mix masks to update the seed population. A mix mask for efficiently translating compressed instructions is determined from the updated seed population.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: August 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sergei Larin, Lucian Codrescu, Anshuman Das Gupta
  • Patent number: 10735462
    Abstract: According to the presently disclosed subject matter, malware induced data compression is harnessed for detecting infection of a host computer by the malicious software, which caused data compression. To this end, compressed ratio of the compressed data received from a host computer is compared with an expected compression ratio and based on the comparison it is determined whether the received data is suspected of being infected by a malware.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: August 4, 2020
    Assignee: Kaminario Technologies Ltd.
    Inventors: Ran Sheri, Yogev Vaknin
  • Patent number: 10725965
    Abstract: Definitions are received for allowable activity windows and epochs. Each epoch specifies a retention duration and allowable activity window. There can be a retention policy specifying that copies created during a particular time period of the allowable activity window are to be retained past a retention duration of an initial epoch. A determination is made as to whether a copy was created during the particular time period specified in the retention policy. If the copy was not created during the particular time period, the retention duration of the initial epoch is added to a creation time of the copy to obtain a date after which the copy should be deleted. If the copy was created during the particular time period, a retention duration of a subsequent epoch is added to the creation time to obtain the date. The date is then associated with the copy.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 28, 2020
    Assignee: EMC IP Holding Company LLC
    Inventor: John Rokicki
  • Patent number: 10628060
    Abstract: Providing a data processing manner, wherein: a SSD compresses a data; the SSD storing the compressed data; the SSD sends a feedback information to a controller, wherein the feedback information indicates a remaining capacity of the SSD after the compressed data is stored.
    Type: Grant
    Filed: April 22, 2018
    Date of Patent: April 21, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Liming Wu, Jianye Yao, Bin Huang, Hongqiang Cao, Chao Xu, Yibin Li
  • Patent number: 10602174
    Abstract: A system for lossless pixel compression for random video memory access is described herein. The system includes an encoder and a decoder. The system also includes a memory that is to store instructions and that is communicatively coupled to the encoder and decoder. Further the system includes a processor. The processor is coupled to the camera, the display, and the memory. When the processor is to execute the instructions, the processor is to predict a data value based on values of local neighbors and generate an error term based on the predicted data value. The processor is also to losslessly compress a plurality of cachelines based on the error term and predictions.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: James M. Holland, Scott W. Cheng
  • Patent number: 10572187
    Abstract: According to an embodiment, a controller includes a write control unit configured to make a control that converts data requested to be written by an external device into pieces of cluster data with a size of a cluster of a storage medium, compresses each piece of cluster data, determines a corresponding physical address of a write destination in the storage medium according to a predetermined rule, and writes the compressed pieces of cluster data to the storage medium using the physical address of the write destination. The write control unit also makes a control that writes a correspondence between the physical address and a corresponding logical address to a storage unit. The controller also includes a read control unit configured to a control that reads a piece of cluster data from the storage medium using an acquired physical address, and decompresses the read piece of cluster data.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: February 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Fukutomi, Shinichi Kanno