Abstract: Embodiments for implementing an enhanced network stack framework in a computing environment. A plurality of network buffers coherently attached between one or more applications and a network interface may be shared while bypassing one or more drivers and an operating systems using an application buffer, a circular buffer and a queuing and pooling operation.

Abstract: To allow arithmetic processing using a plurality of processing nodes to be executed with a smaller memory size, an arithmetic processing apparatus for executing processing using a hierarchical type network formed by the plurality of processing nodes, comprises: a storage unit configured to store a parameter used by each of the plurality of processing nodes for arithmetic processing and a calculation result of the arithmetic processing in each of the plurality of processing nodes; and a buffer control unit configured to switch, based on a configuration of the hierarchical type network, a buffer system of the parameter and the calculation result in the storage unit in at least one layer of the hierarchical type network.

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. A computing system includes one or more clients for processing applications. A memory controller transfers traffic between the memory controller and two channels, each connected to a memory device. A client sends a 64-byte memory request with an indication specifying that there are two 32-byte requests targeting non-contiguous data within a same page. The memory controller generates two addresses, and sends a single command and the two addresses to two channels to simultaneously access non-contiguous data in a same page.

Abstract: Systems and methods allow users to leverage multiple disparate cloud solutions, offered by disparate service providers, in a unified and cohesive manner. A system includes an engine configured to receive performance metrics from two or more disparate cloud services, select target resources among the two or more disparate cloud services to run tasks based on the performance metrics, a multiservice load balancing scheme, and task parameters. Resources can be scaled up or down in the two or more disparate cloud services based on task loads.

Abstract: An apparatus (300) for processing data comprises a plurality of memory access request sources (102,104) which generate memory access requests. Each of the memory access request sources has a local memory (106,108), and the apparatus also includes a shared memory (110). When the memory access requests are atomic memory access requests, contention may arise over common data. When this occurs, the present technique triggers a switch of processing data in the local memory of a memory access request source to processing data in the shared memory.

Abstract: A method for managing data includes obtaining, by a hypervisor on a host computing device, a write request for storing first data, and in response to the write request: identifying a first set of memory segments associated with the first data using a memory mapper, wherein the first set of memory segments is associated with a memory device, making a first determination that the memory device is local to the host computing device, and in response to the first determination: storing the first data in the first set of memory segments.

Abstract: An image processing apparatus recognizes a character string included in image data generated by a reading unit, displays the recognized character string, receives a selection, performed by a user, of the displayed character string. The image processing apparatus thereafter determines, as a storage destination for the image data, a folder named with the character string that is based on the received selection and thereby stores the image data in the determined storage destination. Additionally, the image processing apparatus, in response to a reading instruction being issued once, reads images of a plurality of documents to generate image data, receives a plurality of times selection, performed by the user, of the displayed character string, and determines, as storage destinations, a plurality of folders named with the respective character strings that are based on the selection received a plurality of times.

Abstract: An erasure code (EC)-based data processing method implemented by a storage controller includes obtaining K data chunks, dividing each of the K data chunks into two data slices, encoding the 2*K data slices based on a parity matrix including 2*M rows and 2*(K+M) columns of elements, to obtain 2*M parity slices, and separately storing the K data chunks and the M parity chunks in different storage devices.

Abstract: Data processing jobs are concentrated into instances of computing environments which instances are added to guarantee availability, while other instances may become idle and removed. Such data processing jobs are each assigned to a program running on (at least) one processor, while at the same time running such jobs in the smallest practical number of Virtual Computing Environments, while also ensuring sufficient Virtual Computing Environments are on standby for new jobs as they arise, while facilitating maintenance functions.

Abstract: The present disclosure relates to a matrix transposition device and method, and a display device. The matrix transposition device includes a first counting unit, an input module, second counting units, and a first data selection unit. The first counting unit numbers a matrix element and outputs a first signal. The input module is coupled to the first counting unit, and is input with the matrix element after receiving the first signal; each. Each column of matrix elements corresponds to one of the second counting units, each of the second counting units outputs a set of second signals, and each set of the second signals includes number information of the matrix elements in a column corresponding to the second counting unit. The first data selection unit receives the second signals in an order of columns of a matrix, and orderly outputs column elements of the matrix as row elements of a transposed matrix.

Abstract: A first data block of multiple data blocks is identified in a first portion of the memory component, the first data block being identified based on a read count associated with the first data block satisfies a first threshold criterion. A determination is made as to whether a second portion of the memory component has an amount of unused storage to store data stored at the first data block, wherein the second portion of the memory component is associated with a lower read latency than the first portion. In response to determining that the second portion of the memory component has the amount of unused storage to store the data stored at the first data block, data stored at the first data block in the first portion of the memory component is relocated to a second data block in the second portion of the memory component. An error rate is evaluated on each word line in the first data block.

Abstract: Aspects of the disclosure provide for mechanisms for memory management of virtual machines in a computer system. A method of the disclosure includes: releasing a memory page of a guest memory of a virtual machine; sending, by the virtual machine, a first notification to a hypervisor, the first notification comprising an indication that a memory page associated with the virtual machine is to be rendered inaccessible; and receiving, by the virtual machine, a second notification indicative of detection of an attempt to access the memory page.

Abstract: Technologies are described herein to track information storage resources in a quantum circuit during compile time or runtime of a program by which quantum algorithms are built.

Abstract: A method for secure hardware initialization during a start-up process comprises activating a protected portion of a physical memory, allocating a part of the protected portion of the physical memory for use by direct memory access, DMA, drivers and non-DMA related hardware initialization instructions, and using a memory management tool, allocating a first part of the physical memory, accessible by a device via the memory management tool, for use by data.

Abstract: A memory module operable to communicate data with a memory controller via a N-bit wide memory bus comprises memory devices arranged in a plurality of N-bit wide ranks. The memory module further comprises logic configurable to receive a set of input address and control signals associated with a read or write memory command and output registered address and control signals and data buffer control signals. The memory module further comprises circuitry coupled between the memory bus and corresponding data pins of memory devices in each of the plurality of N-bit wide ranks. The circuitry is configurable to enable registered transfers of N-bit wide data signals associated with the memory read or write command between the N-bit wide memory bus and the memory devices in response to the data buffer control signals and in accordance with an overall CAS latency of the memory module, which is greater than an actual operational CAS latency of the memory devices.

Abstract: Embodiments of system and methods for providing centralized management of a software defined automation (“SDA”) system are disclosed. The SDA system comprises of a collection of controller nodes and logically centralized and yet physically distributed collection of compute nodes by monitoring activities of the compute nodes. In accordance with some embodiments, one or more components of the system monitor execution, network and security environments of the system to detect an event in a first environment. In response to the detected event, at least one component in the first environment is remediated, the remediation of the first environment creating a trigger to cause remediation of at least one component in each of a second and third environments.

Abstract: According to one or more embodiments of the present invention, a computer implemented method includes receiving a query for an amount of storage in memory of a computer system to be donated to a secure interface control of the computer system. The secure interface control can determine the amount of storage to be donated based on a plurality of secure entities supported by the secure interface control as a plurality of predetermined values. The secure interface control can return a response to the query indicative of the amount of storage as a response to the query. A donation of storage to secure for use by the secure interface control can be received based on the response to the query.

Abstract: Disclosed herein are system, method, and computer program product embodiments for appropriately routing requests for data stored in multiple storage mediums. An embodiment operates by maintaining a first and second data stored on a first storage medium in communication with a second storage medium. Thereafter, a replicate of the first data stored in the first storage medium may be created for the second storage medium to store a replica data mirroring the first data. Subsequently, a request for retrieval of the first data may be received. Afterward, a previous update time of the second storage medium in receiving the replicate of the first data stored in the first storage medium may be determined. Lastly, based on the previous update time, the request may be forwarded to the first storage medium or second storage medium.

Abstract: Provided are an apparatus and a method for generating an identification key with improved reliability by: providing a plurality of resistances which are generated according to a random connection state between conductive layers of a semiconductor due to process variation of the semiconductor; discriminating a first group which has a resistance value greater than a first threshold value and less than a second threshold value among the plurality of resistances; and reading at least one resistance which does not belong to the first group out of the plurality of resistances and reading an identification key in the form of a digital value.

Abstract: Presented herein are techniques enable existing hardware input/output resources, such as the hardware queues (queue control registers), of a network interface card to be shared with different hosts (i.e., each queue mapped to many hosts) by logically segregating the hardware I/O resources using assignable interfaces each associated with a distinct Process Address Space Identifier (PASID). That is, different assignable interfaces are created and associated with different PASIDs, and these assignable interfaces each correspond to a different host (i.e., there is a mapping between a host, an assignable interface, a PASID, and a partition of a hardware queue). The result is that that the hosts can use the assignable interface to directly access the hardware queue partition that corresponds thereto.

Abstract: Methods and apparatus are described for simultaneously buffering and reformatting (e.g., transposing) a matrix for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). Examples of the present disclosure increase the effective double data rate (DDR) memory throughput for streaming data into GEMM digital signal processing (DSP) engine multifold, as well as eliminate slow data reformatting on a host central processing unit (CPU). This may be accomplished through software-defined (e.g., C++) data structures and access patterns that result in hardware logic that simultaneously buffers and reorganizes the data to achieve linear DDR addressing.

Abstract: An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory operationally connected with the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Abstract: A method, according to one embodiment, includes receiving, at a first node of a distributed database system from one or more caller nodes of the distributed database system, a predetermined number of service tasks to add to a value in a row stored in the distributed database system at a write daemon. Additionally, a time of receipt of the predetermined number of service tasks is recorded. Further, the predetermined number of service tasks are combined to a single row in the distributed database system at the write daemon. Further still, a number of operations to attend to the predetermined number of service tasks is reduced by sending the predetermined number of service tasks to at least two bucket daemons on at least two other nodes of the distributed database system.

Abstract: In an information processing device serving as a PCIe system including a host device and a plurality of memory devices, one of the plurality of memory devices is defined as a master memory. The other memory devices are defined as slave memories, and are logically coupled to the master memory. The plurality of memory devices thus constitute a single virtual storage. When accessing is performed from a root complex to the plurality of memory devices constituting the single virtual storage, the root complex hands over a bus master to the master memory. The master memory receives a command regarding the accessing from the root complex, changes address information used for the accessing in the command regarding the accessing, based on a logical relationship with the slave memories, and sends changed command regarding the accessing to the slave memories.

Abstract: Embodiments include methods, computing systems and computer program products for identifying and tracking frequently accessed registers in a processor of a computing system. Aspects include: creating a list of top accessed registers of certain registers in processor, each register having a corresponding register usage counter, initializing each register usage counter, starting a register usage monitoring mode, examining each register usage counter, and updating list of top accessed registers, stopping register usage monitoring mode, and updating a register file partition assignment when the list of top accessed registers is identified. Once the list of top accessed registers is identified, stopping the programs and bring its threads of execution to quiescent, moving registers between register file partitions until all registers on the list of top accessed registers are in the fully-ported register file partition, and resuming executions of the program and its threads.

Abstract: Systems and methods for automated failure recovery of subsystems of a management system are described. The subsystems are built and modeled as services, and their management, specifically their failure recovery, is done in a manner similar to that of services and resources managed by the management system. The management system consists of a microkernel, service managers, and management services. Each service, whether a managed service or a management service, is managed by a service manager. The service manager itself is a service and so is in turn managed by the microkernel. Both managed services and management services are monitored via in-band and out-of-band mechanisms, and the performance metrics and alerts are transported through an event system to the appropriate service manager. If a service fails, the service manager takes policy-based remedial steps including, for example, restarting the failed service.

Abstract: Systems, apparatuses and methods may provide for technology that receives, at a remote access controller of a computing system, configuration data associated with a non-volatile memory of the computing system, wherein the configuration data is received while the computing system is in a sleep state. The technology may also store the configuration data and provide a host processor of the computing system with access to the configuration data. In one example, receipt of the configuration data bypasses a memory configuration-related reboot of the computing system and the configuration data is received via an out-of-band management interface.

Abstract: Systems, devices, and methods related to non-volatile memory are described. A non-volatile memory array may be employed as a main memory array for a system on a chip (SoC) or processor. A controller may interface between the non-volatile memory array and the SoC or processor using a protocol agnostic to characteristics of non-volatile memory operation including different page sizes or access time requirements, etc. A virtual memory bank at the controller may be employed to facilitate operations between the SoC or processor and the non-volatile memory array. The controller may be coupled with a buffer to facilitate rapid data operation, and the controller may be configured to selectively access data at the non-volatile array to account for data stored in the virtual memory bank or the buffer. The controller, the virtual memory bank, and the buffer may be configured on one chip separate from the SoC or processor.

Abstract: A service manages a plurality of virtual machine instances for low latency execution of user codes. The service can provide the capability to execute user code in response to events triggered on various event sources and initiate execution of other control functions to improve the code execution environment in response to detecting errors or unexpected execution results. The service may maintain or communicate with a separate storage area for storing code execution requests that were not successfully processed by the service. Requests stored in such a storage area may subsequently be re-processed by the service.

Abstract: A system and method can support asynchronous request/response in a network environment. A network protocol can utilize a load balancer to balance requests, such as HTTP requests, over a fast network interface, such as InfiniBand, to one or more nodes of an application server cluster. The system and method can attach headers to the requests such that the requests can be sent in an interleaved manner. The system and method can further allow for sending of large requests by breaking up the large requests into smaller portions, and sending each portion, interleaved, with other requests.

Abstract: A method for recording a duration of use of a data block is disclosed, as well as a data storage device implementing that method. The data block is either an in-use data block or an empty data block. The method includes steps of: receiving and writing data into one of the in-use data blocks and writing a program time and a time interval of the data into the in-use data block. Wherein the time interval is a difference between the program time and an initial program time of the in-use data block, and the initial program time was recorded when the in-use data block wrote a first piece of data.

Abstract: Apparatuses, methods and storage mediums associated with updating firmware of a component of a computer platform, are disclosed herein. In some embodiments, a processor includes an instruction decoder; and a storage having microcode arranged to implement an instruction to verify updates to firmware of a component of a computer platform hosting the processor and the component. The computer platform may include a component firmware update manager. The firmware of a component may include a firmware update plug-in. Other embodiments are also described, and may be claimed.

Abstract: A computer-implemented method for managing a database space includes writing, via a processor, a purge rule to a database management system (DBMS). When the purge rule is executed by the DBMS they automatically purge data in one or more databases at regular intervals. The method includes executing, via a DBMS processor, the purge rule. The purge rule is configured to define, via the DBMS processor, a purge object having purge object attributes without user intervention, and purge, via the DBMS processor, the data based on the purge rule at intervals defined by the purge rule attributes and without user intervention.

Abstract: Generally described, the present application relates to systems and methods for the managing virtual machines instances using a physical computing device and an offload device. The offload device can be a separate computing device that includes computing resources (e.g., processor and memory) separate from the computing resources of the physical computing device. The offload device can be connected to the physical computing device via a bus interface. The bus interface can be a high speed, high throughput, low latency interface such as a Peripheral Component Interconnect Express (PCIe) interface. The offload device can be used to offload virtualization and processing of virtual components from the physical computing device, thereby increasing the computing resources available to the virtual machine instances.

Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

Abstract: A method for performing access control in a memory device, the associated memory device and the controller thereof are provided. The method includes: according to at least one predetermined arrangement pattern, writing a plurality of sets of symbols into a plurality of storage regions of a memory as a plurality of redundant array of independent disks (RAID) groups, respectively; and utilizing a RAID engine circuit in the memory device to perform a plurality of operations related to data protection, such as: determining a series of reading patterns corresponding to the predetermined arrangement pattern; according to a reading pattern of the series of reading patterns, reading a plurality of symbols from each RAID group of the RAID groups; and performing exclusive-OR (XOR) operations on the symbols to convert the symbols into at least one XOR result, for performing data protection.

Abstract: A server LPAR operating in a virtualized computer shares pages with client LPARs using a shared memory region (SMR). A virtualization function of the computer receives a get-page-ID request associated with a client LPAR to identify a physical page corresponding to a shared page included in the SMR. The virtualization function requests the server LPAR to provide an identity of the physical page. The virtualization function receives a page-ID response comprising the identity of a server LPAR logical page that corresponds to the physical page. The virtualization element determines a physical page identity and communicates the physical page identity to the client LPAR. The virtualization element receives a page ID enter request and enters an identity of the physical page into a translation element of the computer to associate a client LPAR logical page with the physical page.

Abstract: A read request for a data object is received from a first processing thread. Responsive to the read request, it is determined whether a cached version of the data object is available from a global cache. If the cached version of the data object is not available from the global cache, a result is immediately returned to the first processing thread to indicate that the data object is not available from the global cache. The first processing thread is freed from waiting for the data object to become available from the global cache. A cache refresh message is enqueued, for the data object, in a message queue to cause a second different processing thread to subsequently dequeue the cache refresh message for the data object and build the data object in the global cache using underlying data persisted in and retrieved from a primary data source among the one or more primary data sources.

Abstract: A method for responding to a command sequence includes receiving a signal from a host carrying a plurality of commands in the command sequence, detecting a non-consecutive clock associated with a start of a current command in the command sequence, and generating a control signal in an active state to indicate detection of the non-consecutive clock.

Abstract: A programmable device including a memory and at least one processor coupled to the memory is provided. The memory stores a plurality hybrid objects. Each hybrid object of the plurality of hybrid objects includes a native object wrapped by an interpreted object. The at least one processor can be coupled to the memory. The at least one processor can be configured to identify a message to execute an operation on one or more hybrid objects of the plurality of hybrid objects; clone, in response to reception of the message, each native object within the one or more hybrid objects to create one or more cloned native objects; wrap each cloned native object of the one or more native objects with a new interpreted object to create one or more new hybrid objects; and execute the operation on the one or more new hybrid objects.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, a trigger event associated with an Ethernet switch. Ethernet based control information may be encapsulated into an InfiniBand based packet. The InfiniBand based packet with the Ethernet based control information may be transmitted over the InfiniBand fabric from a source to a destination. The Ethernet based control information may be decapsulated from the InfiniBand based packet at the destination.

Abstract: A partial memory die is removed from an edge of a wafer such that the partial memory die is missing a portion of the memory structure that was not printed on the wafer. A usable portion of the incomplete memory structure is determined and one or more rectangular zones in the usable portion of the incomplete memory structure are identified. During operation of the memory system, the memory system receives logical addresses for memory operations to be performed on the partial memory die and determines physical addresses that corresponding to the logical addresses. The memory system performs an out of bounds response for a physical address that is on the partial memory die but outside of the one or more rectangular zones. The memory system performs memory operations for physical addresses that are inside the one or more rectangular zones.

Abstract: A semiconductor memory device includes first and second read modes, a first memory cell and a second memory cell; a first word line electrically connected to a gate of the first memory cell and a gate of the second memory cell; a first bit line electrically connected to the first memory cell; a second bit line electrically connected to the second memory cell; a first sense amplifier configured to determine data read from the first memory cell at a first timing in the first and second read modes; a second sense amplifier configured to determine data read from the second memory cell at a second timing different from the first timing in the first read mode; a second sense amplifier configured to determine data read from the second memory cell at a second timing different from the first timing in the first read mode; a delay circuit; and a controller.

Abstract: Resource migration negotiation is disclosed. A request is received, from a remote physical node in a plurality of physical nodes, for a resource. An operating system is run collectively across the plurality of physical nodes. The request includes information pertaining to a guest thread running on the remote physical node. Based at least in part on at least some of the information included in the request, it is determined whether to send the requested resource or reject the request. A response is provided based at least in part on the determination.

Abstract: Determining whether to perform atomic or conventional reference counting is provided. A single bit of a reference count corresponding to a reference-counted resource is read to determine whether to atomic reference counting is to be performed. It is determined whether the single bit of the reference count is set. In response to determining that the single bit is set, an atomic operation for atomic maintenance of the reference count corresponding to the reference-counted resource is performed by adjusting the reference count by a value of two. In response to determining that the single bit is not set, a conventional adjustment operation is performed for maintenance of the reference count corresponding to the reference-counted resource.

Abstract: Upon receiving an erase command and a first logical address, a controller in a first mode sets, as an erasure waiting area, an erasure unit area assigned with a first physical address associated with the first logical address in a first table. The controller in the first mode replaces, in the first table, the first physical address with a physical address assigned to an erasure completion area. The controller in a second mode sets the erasure waiting area as the erasure completion area. Upon receiving a release command to release the second mode at some point in time of data erasure from the erasure waiting area, the controller changes the operation mode to a third mode. The controller operating in the third mode erases un-erased data from the erasure waiting area and changes the operation mode from the third mode to the first mode.

Abstract: A semiconductor memory device according to an embodiment includes: first to 32nd memory cells; first to 16th bit lines connected to the first to 16th memory cells; 17th to 32nd bit lines connected to the 17th to 32nd memory cells; a first word line connected to gates of the first to 32nd memory cells; first to 16th sense amplifiers configured to determine data read from the first to 16th memory cells at a first timing; and 17th to 32nd sense amplifiers configured to determine data read from the 17th to 32nd memory cells at a second timing. The first timing is different from the second timing.

Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.