Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock because the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: The present invention discloses a system and method for simultaneously identifying a most recent advanced load instruction employing a particular register and determining whether the instruction conflicts with a store instruction thereby requiring a recovery operation. Fully associative tables are advantageously employed for identifying the most recent load instruction, for comparing store instruction address information with addresses employed in advanced load instructions, and for logging a validity status associated with a register number. Parallel operation of load vs. check register numbers and load instruction and store instruction memory addresses conserves time and preferably enables a hit/miss determination for a particular check instruction to be completed in single machine cycle.

Abstract: Apparatus for addressing a data memory (21), with the apparatus (1) having:

Abstract: A processor is provided for calculating an output pointer to a first data item by combination of an input pointer to a second data item with an offset. The processor includes logic for generating, in a single operation, a zero value for the output pointer when the input pointer is zero and an output pointer value calculated as the offset value added to, or subtracted from, the input pointer value when the input pointer is non-zero.

Abstract: An information processing apparatus has a DRAM for storing at least predetermined data, a system bus to which the DRAM is connected, a CPU for controlling the DRAM, and a CPU bus to which the CPU is connected. The information processing apparatus also has an SRAM connected to the system bus and the CPU bus, for storing data transferred from the DRAM, an address counter for generating an address of the SRAM based on an initial value, and a DMA controller for controlling data transfer between the DRAM and the SRAM using the address generated by the address counter. At a certain time, the DMA controller outputs an address D2 next to an initial address in the DRAM via the system bus to the DRAM, reads data B from the address D2, and outputs the data B via the system bus to the SRAM. At the same time, the address counter increments a stored address S1 into an address S2, and outputs the address S2 to the SRAM, which stores the data B at the address S2.

Abstract: A load/store unit comprising a load/store buffer and a memory access buffer. The load store buffer is coupled to a data cache and is configured to store information on memory operations. The memory access buffer is configured to store addresses and data associated with the requested addresses for at least one of the most recent memory operations. The memory access buffer, upon detecting a load memory operation, outputs data associated with the load memory operation's requested address. If the requested address is not stored within the memory access buffer, the memory access buffer is configured to store the load memory operation's requested address and associated data when it becomes available from the data cache. Similarly, store memory operation requested address and associated data is also stored.

Abstract: A processor coupled to a memory for providing a pointer in order to access a corresponding memory address, the pointer being updated by adding a predetermined increment according to logic integral with the processor. A method is disclosed for updating the pointer to a value other than that dictated by the processor logic so as to access an arbitrary memory address dictated by an application program accessing the processor. The method comprises disabling the logic in respective of the pointer, processing the application program so as generate a successive memory address for accessing the memory, and setting the pointer to the successive memory address instead of incrementing the pointer by the predetermined increment dictated by the logic.

Abstract: A number of virtual areas with virtual addresses of storage locations within the virtual areas are allocated to a data storage array, having a total physical storage capacity. Physical addresses are allocated by an array controller for the disc storage array to the virtual addresses only as data are to be written to the respective virtual addresses.

Abstract: The present invention relates to a FIFO (First In First Out) memory control circuit for controlling FIFO memory which is used in various electronic devices. Specifically, the present invention relates to a FIFO memory control circuit capable of performing asynchronous read/write control hen a write clock and a read clock are different and it is known or determined which of these clocks has a higher clock frequency.

Abstract: When a decision circuit (217) incorporated in a control circuit (21) in an instruction decode unit (2) in a microprocessor (1) decides that an integer operation unit (4) can not execute a following sub instruction, the decision circuit (217) controls each of selectors (211, 214, and 215) and an exchange circuit (216) so that a memory access unit (3) that has already executed a preceding sub instruction can execute the following sub instruction.

Abstract: In a digital signal processor, a file address table (FAT) file is stored in the storage memory unit of the digital signal processor rather than in the program memory of the central processing unit. When a selected file is to be processed, a summary file is generated in the stack sector of the program memory, the summary file including the FAT file entries for the selected file. By positioning the FAT files in this manner, not only are locations in the program memory made available for the storage of other files, but the performance of the digital signal processor can be enhanced.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock since the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: An instruction cache memory (12) includes a clock gate circuit (26) for controlling the supply of a clock signal (CLK) to tag RAM (22). The clock gate circuit (22) supplies the clock signal (CLK) to tag RAM 22 only when there is a movement in cache line for storing a word to be read out or a branch instruction is detected in a processor (14). As a result, power consumption of the tag RAM (22) can be reduced.

Abstract: A data buffer apparatus stores first data objects containing a plurality of first data items and second data objects containing one or more second data items in a number of different ways depending upon a mode of operation. The apparatus includes an encoder (1290) for rearranging the order of the first data items within the first data objects in accordance with first arranging mode, prior to storing in the buffer (1293). The apparatus also includes a decoder (1291) for rearranging the order of a plurality first data items read from the buffer, in accordance with a second arranging mode.

Abstract: A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register 900 receives an instruction for execution. Decoding circuitry 913 selects a register specified by a field in an instruction to provide an index value. An immediate field from the instruction is combined with the index value by multiplexor 910 to form an address which can be used to access a data value or to form a target address for a branch instruction. Mux control 915 parses the immediate value to determine how to combine the immediate value and the index value.

Abstract: A microprocessor apparatus executes a program including an instruction which indicates an address for taking out an operand from a main memory in a predetermined addressing mode which belongs to a displacement-adding register indirect addressing mode. The microprocessor includes address generating portion for shifting by a predetermined number of bits the value of a displacement which is indicated by the instruction, adding the thus-shifted value to the value stored in a predetermined register and thus generating an effective address, when the operand of the instruction is taken out from the main memory.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a lock size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: A superscalar microprocessor implements a microcode instruction unit that patches existing microcode instructions with substitute microcode instructions. A flag bit is associated with each line of microcode in the microcode instruction unit. If the flag bit is asserted, the microcode instruction unit branches to a patch microcode routine that causes a substitute microcode instruction stored in external RAM to be loaded into patch data registers. The transfer of the substitute microcode instruction to the patch data registers is accomplished using data transfer procedures. The microcode instruction unit then dispatches the substitute instructions stored in the patch data registers and the substitute instruction is executed by a functional unit in place of the existing microcode instruction.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Abstract: A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a particular load memory operation is the sum of a stride operand of the stride instruction and the address corresponding to another load memory operation immediately preceding the particular load memory operation in the series. A base address operand specifies the address of the first load memory operation in the series, and a repetition count operand specifies the number of load memory operations in the series. The cache lines corresponding to the series of load memory operations (i.e. the cache lines storing the bytes addressed by the load memory operations) are fetched into the data cache of the microprocessor in response to the series of load memory operations.

Abstract: A bit field system is disclosed which includes a processor as well as a bit field peripheral device which is accessed via dedicated bit field addresses. Such a system efficiently executes bit field operations. Additionally, such a system advantageously provides a processor which does not include an original bit field instruction set with the ability of performing bit field operations. Such a system also advantageously avoids difficulties involved in encoding bit field instructions.

Abstract: A microcontroller is presented including additional hardware which generates multiple auxiliary address signals needed to expand the memory address space of the microcontroller. The auxiliary address signals allow access to memory locations within external memory devices which would not otherwise be accessible while advantageously maintaining software compatibility with previous microcontroller products. The auxiliary address signals form the most significant bits of augmented addresses, thereby dividing memory locations within the external memory devices into multiple memory banks of equal size. When memory banking is enabled, software instructions select the desired memory bank by writing appropriate values to address bit positions within a memory banking control (MBC) register. The auxiliary address signals are normally produced having values stored within corresponding bit positions of the MBC register.

Abstract: A method and apparatus for controlling an integrated circuit (IC) die with another IC die. The present invention uses a processor to control the operation of a cache memory die. In this manner, the cache memory is directed by the processor as to the operations to be performed, such as writing to the cache memory. A dedicated bus is coupled between the two dice. This dedicated bus is used to send control and other signals between the two dice.

Abstract: An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the corresponding reservation stations while the associated instructions are being decoded. The speculative register file stores speculative register values corresponding to previously decoded instructions. The speculative register values are generated prior to execution of the previously decoded instructions. If the register operands included in the address operands of an instruction are stored in the speculative register file, then the memory operation may be passed through the corresponding reservation station to an address generation unit. The address generation unit generates the data address from the address operands and accesses a data cache while register operands corresponding to the instruction are requested from a register file and reorder buffer.

Abstract: A method and apparatus for controlling multiple cache memories with a single cache controller. The present invention uses a processor to control the operation of its on-chip level one (L1) cache memory and a level two (L2) cache memory. In this manner, the processor is able to send operations to be performed to the L2 cache memory, such as writing state and/or cache line status to the L2 cache memory. A dedicated bus is coupled between dice. This dedicated bus is used to send control and other signals between the processor and the L2 cache memory.

Abstract: An apparatus and method are shown for decoding variable length instructions in a processor where a line of variable length instructions from an instruction cache are loaded into an instruction buffer and the start bits indicating the instruction boundaries of the instructions in the line of variable length instructions is loaded into a start bit buffer. A first shift register is loaded with the start bits and shifted in response to a lower program count value which is also used to shift the instruction buffer. A length of a current instruction is obtained by detecting the position of the next instruction boundary in the start bits in the first register. The length of the current instruction is added to the current value of the lower program count value in order to obtain a next sequential value for the lower program count which is loaded into a lower program count register.

Abstract: An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the corresponding reservation stations while the associated instructions are being decoded. The speculative register file stores speculative register values corresponding to previously decoded instructions. The speculative register values are generated prior to execution of the previously decoded instructions. If the register operands included in the address operands of an instruction are stored in the speculative register file, then the memory operation may be passed through the corresponding reservation station to an address generation unit. The address generation unit generates the data address from the address operands and accesses a data cache while register operands corresponding to the instruction are requested from a register file and reorder buffer.

Abstract: An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of processing elements (PE) constituting a parallel computer system. An adder provided within the global address generating unit sequentially adds an increment of an address, d.sub.-- Adr.sub.-- exl, and d.sub.-- Adr.sub.-- in to an address Adr.sub.-- exl and Adr.sub.-- in, respectively. A subtracter outputs a quotient obtained by dividing d.sub.-- Adr.sub.-- exl by band width bexl as a logical PE number. Additionally, a remainder obtained as an output from a subtracter is added to Adr.sub.-- in, thereby enabling a logical in-PE address to be obtained. The logical PE number and the logical in-PE address thus obtained are converted to a real PE number and a real in-PE address. Generating a global address by hardware reduces overhead incurred by parallel operation of array data.

Abstract: An apparatus is provided, including one or more early address generation units which attempt to perform data address generation upon decode of an instruction which includes a memory operand. The early address generation units may be successful at generating the data address if the logical data address is formed from a displacement only. Additionally, the early address generation unit may be successful at generating the data address if the logical data address is formed from the displacement and register operands which are available upon decode of the instruction. Data address generation latency may be shortened. If register operands are employed for forming the address and the register operands are not available, the data address may be generated in a functional unit at the execute stage.

Abstract: A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.

Abstract: An apparatus for controlling address alignment fault generation employing a recoded two bit structure. This alignment fault state circuit stores one of four states corresponding to whether the operating system permits address misalignment fault generation and whether the application program requests such address misalignment fault generation. The two latches each hold either a first state or a second state. Together the two latches have either a first combined state, a second combined state, a third combined state or a fourth combined state. The two latches have a recoded set of states such that receipt of at least one of the alignment check on instruction, the alignment check off instruction, the alignment mask permit instruction or the alignment mask prohibit instruction causes both latches to change state.