Abstract: Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A plurality of dimensions from a tensor is flattened into a single dimension. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. A direct memory access (DMA) engine coupled to the one or more processor clusters is configured. Addresses are generated based on the unique address space descriptors and the common address space descriptor. The plurality of dimensions can be summed to generate a single address. Memory is accessed using two or more of the addresses that were generated. The addresses are used to enable DMA access.

Abstract: The embodiments of the present disclosure relate to a storage device sharing system and operation method thereof. According to embodiments of the present disclosure, the storage device sharing system may include i) a plurality of storage devices, each storage device including a first memory buffer including a plurality of first type memory blocks and a second memory buffer including a plurality of second type memory blocks, and ii) a host device configured to determine, based on sharing state set for a first storage device among the plurality of storage devices, whether to set the first memory buffer of the first storage device as an area for storing data to be written to a second storage device among the plurality of storage devices.

Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) generator. Unstable bits of the plurality of key bits are identified, and a security key is generated based on the plurality of key bits, wherein the security key excludes the identified unstable bits.

Abstract: An apparatus includes a plurality of load buses and a load store unit that includes a plurality of load ports to access the plurality of load buses. The load store unit performs a gather operation to concurrently gather a plurality of subsets of data from a memory via the plurality of load buses in a first mode. The apparatus also includes a register that is partitioned into a plurality of portions to hold the plurality of subsets of data provided by the load store unit. The load store unit ignores exceptions or faults while performing the gather operation in the first mode and transitions to a second mode in response to an exception or fault. Two lanes are dispatched to concurrently perform the gather operation per clock cycle in the first mode and a single lane is dispatched to perform the gather operation per clock cycle in the second mode.

Abstract: Intelligent memory brokering for multiple process instances, such as relational databases (e.g., SQL servers), reclaims memory based on value, thereby minimizing cost across instances. An exemplary solution includes: based at least on a trigger event, determining a memory profile for each of a plurality of process instances at a computing node; determining an aggregate memory profile, the aggregate memory profile indicating a memory unit cost for each of a plurality of memory units; determining a count of memory units to be reclaimed; identifying, based at least on the aggregate memory profile and the count of memory units to be reclaimed, a count of memory units to be reclaimed within each process instance so that a total cost is minimized to reclaim the determined count; and communicating, to each process instance having identified memory units to be reclaimed, a count of memory units to be reclaimed within the process instance.

Abstract: An apparatus and method are provided for performing vector processing operations. In particular the apparatus has processing circuitry to perform the vector processing operations and an instruction decoder to decode vector instructions to control the processing circuitry to perform the vector processing operations specified by the vector instructions. The instruction decoder is responsive to a vector generating instruction identifying a scalar start value and wrapping control information, to control the processing circuitry to generate a vector comprising a plurality of elements. In particular, the processing circuitry is arranged to generate the vector such that the first element in the plurality is dependent on the scalar start value, and the values of the plurality of elements follow a regularly progressing sequence that is constrained to wrap as required to ensure that each value is within bounds determined from the wrapping control information.

Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

Abstract: A memory system may include: a nonvolatile memory device including a plurality of memory blocks, each memory block including a plurality of pages; and a controller suitable for controlling the nonvolatile memory device to store user data received from a host in a first block among the memory blocks, to store metadata in a second block among the memory blocks, and to generate the metadata corresponding to storage of the user data, the controller may map a first logical address used in the host to a physical address of the first block, and may map a second logical address not used in the host, to a physical address of the second block, the first logical address and the second logical address being successive.

Abstract: Fractional bit storage is disclosed herein which allows for storage of additional bits distributed over multiple SSD cells and maximizes data stored for SSD cells with non-binary amounts of allowable threshold voltages while minimizing required bits dedicated to error correction code (ECC). For an SSD cell with twenty-four levels of threshold voltage, set partitioning is used to create three equal subsets of levels each corresponding to eight levels of threshold voltage and each partitioned subset able to encode three bits. Each partitioned subset is designed with eight allowable threshold voltage ranges, each of which is separated from any other allowable threshold voltage range by at least two of the twenty-four levels of maximum threshold voltage. By choosing both set partitioning and assigning bit values determined via code modulation, bits stored within a partitioned subset are protected without the need for additional ECC.

Abstract: The systems and methods provided herein relate to a command interface/memory device that supports multiple modes of command acquisition. A current command acquisition mode from a set of supported command acquisition modes that each define a corresponding command execution frequency is identified. Based upon the identified mode, clock cycles that will be used to acquire portions of a command address from are identified. The portions of the command address are acquired from the identified clock cycles and a command based upon the acquired portions of the command address is executed.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

Abstract: A system for designing and executing control loops in a cloud environment includes a control platform implemented in the cloud environment having a data collection, analytics and events module, a policy module and an application controller module. The system includes a business process management application coupled to the control platform having a control loop designer module for designing a control loop template and a workflow engine for distributing the control loop template. The business process management application is coupled to the data collection analytics and events module of the control platform as well as the policy module in the application controller module to control platform. The control loop is activated by the control platform.

Abstract: A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.

Abstract: Embodiments of the present disclosure relate to a controller that includes a monitor to determine an access pattern for a range of memory of a first computer memory device, and a pre-loader to pre-load a second computer memory device with a copy of a subset of the range of memory based at least in part on the access pattern, wherein the subset includes a plurality of cache lines. In some embodiments, the controller includes a specifier and the monitor determines the access pattern based at least in part on one or more configuration elements in the specifier. Other embodiments may be described and/or claimed.

Abstract: Methods and systems regarding the rapid and efficient compression and decompression of sparse data are disclosed. One method for compressing a set of data from a sparse matrix includes, evaluating a sequence of data entries from the set of data, extracting a sequence of sparse data values from the sequence, extracting a sequence of non-sparse data value run lengths from the sequence, formulating a set of row pointers from the sequence, storing the sequence of sparse data values in a first set of memory addresses, and storing the sequence of non-sparse data value run lengths in a second set of memory addresses. The set of row pointers identify a set of rows of the sparse matrix in both the first and second sets of memory addresses. Rapid decompression can be conducted using the row pointers.

Abstract: A processor device is provided with hardware-implemented logic to receive an instruction including a pointer identifier and a pointer change value, the pointer identifier including a pointer address field encoded with an address of a line of memory corresponding to a location of a pointer of a particular one of the one or more cyclic buffers, one or more cushion bits, and a buffer identifier field encoded with a buffer identifier assigned to the particular cyclic buffer. The logic further enables the processor to identify that the instruction is to apply to the particular cyclic buffer based on the buffer identifier, determine that the pointer change value causes a wraparound of the pointer in the particular cyclic buffer, and fix location of the pointer in the particular cyclic buffer based on the wraparound.

Abstract: A library control device moves a desired record medium from a magazine, which is configured to load a plurality of record media into a plurality of slots, to a drive so as to read or write data. The library control device stores identifications of record media in correlation with slots loading recording media. Upon detecting a malfunction in reading or writing data with a record medium, an operator needs to extract the record medium from the magazine. At this time, the library control device rewrites the identification of a slot, which is stored in correlation with the record medium subjected to extraction, with the identification of a predetermined slot so as to move the record medium to the predetermined slot. Thus, it is possible for an operator to extract the record medium detecting a malfunction from the predetermined slot without making any mistake.

Abstract: Circuitry may be configured to identify a particular element position of a bit vector stored in a register, where a value of the element occupying the particular element position matches a first predetermined value, and determine an address value dependent upon the particular element position of the bit vector and a base address. The circuitry may be further configured to load data from a memory dependent upon the address value.

Abstract: Devices, systems and methods are provided for writing, by a plurality of computing resources, to contiguous memory addresses of memory that supports random access, without having to specify actual write addresses of the memory.

Abstract: Systems and methods for tracking addresses stored in non-home locations in a cache. A method includes determining if an address that is to be stored in a cache is to be stored in a non-home location, determining if a directory has a location available for storing an identifier of the non-home location and if one or more locations of the directory are available for storing an identifier of the non-home location, storing an identifier of the non-home location in one of the one or more locations of the directory. The method further includes invalidating a non-home location in the cache that corresponds to one of the one or more locations of the directory, if none of the one or more locations of the directory are available for storing an identifier of the non-home location, and storing an identifier of the non-home location in the one of the one or more locations.

Abstract: Systems and methods for invalidating a way of a directory for non-home locations (DNHL) set that stores an identifier of a home location of an address is disclosed. As a part of a method, a request to store data in a location of a special cache that is being tracked by the way of the DNHL set is accessed, it is determined if an address stored in the location of the special cache is stored in a non-home location, a DNHL set is identified that tracks the location of the special cache if the address is not stored in a non-home location, and a set and way of the location of the special cache is compared with a set and way identifier stored in each way of the DNHL set. The way of the DNHL set that stores a matching set and way identifier is invalidated.

Abstract: An apparatus and method for performing a vector bit reversal. For example, one embodiment of a processor comprises: a source vector register to store a plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; vector bit reversal logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the source vector register to generate a set of reversed bit groups; and a destination vector register to store the reversed bit groups.

Abstract: A method for operating a memory system includes detecting a size of a data requested by a host, generating a first data that represents the size of the requested data and a second data that represents a remaining empty space other than a space for the requested data in a first region having a unit size of data storage in a memory device when the size of the requested data is smaller than the first region and the request is to write the requested data into the memory device, and storing the first data and the second data in the memory device along with the requested data.

Abstract: A rupture control device may include an address control circuit configured to generate a rupture address in response to a first rupture command signal, a rupture mask signal and an external address, wherein the rupture address is generated according to whether the rupture mask signal is activated, and wherein an address and fuse data are compared, and a rupture mask signal indicating whether a fuse is ruptured is determined. Further, a fuse array configured to perform a rupture operation in response to the rupture address when a rupture enable signal is activated, and output the fuse data in response to a read enable signal.

Abstract: An apparatus and method for performing a vector bit reversal and crossing. For example, one embodiment of a processor comprises: a first source vector register to store a first plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; a second source vector to store a second plurality of source bit groups; vector bit reversal and crossing logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the first source vector register to generate a set of reversed bit groups, wherein the vector bit reversal and crossing logic is to additionally interleave the set of reversed bit groups with the second plurality of bit groups; and a destination vector register to store the reversed bit groups interleaved with the first plurality of bit groups.

Abstract: A method performed by a control unit in an array of multiple self-addressable control units arranged in at least two dimensions involves obtaining information to be used to determine a self-address, determining a self-address value based upon the information, storing the determined self-address value, based upon the self-address value, specifying first data to be provided to a next self-addressable control unit in a first group of self-addressable control units for a first dimension of the array, providing the first data to the next self-addressable control unit in the first group, based upon the self-address value, specifying second data to be provided to a different self-addressable control unit in a second group of self-addressable control units for a second dimension of the array different from the first dimension of the array, and providing the second data to the different self-addressable control unit in the second group.

Abstract: Embodiments of the present invention provide a database processing system for efficient partitioning of a database table with column-major layout for executing one or more join operations. One embodiment comprises a method for partitioning a database table with column-major layout, partitioning only the join-columns by limiting the partitions by size and number, executing one or more join operations for joining the partitioned columns, and optionally de-partitioning the join result to the original order by sequentially writing and randomly reading table values using P cursors.

Abstract: One example method includes identifying synchronous code including instructions specifying a computing operation to be performed on a set of data; transforming the synchronous code into a pipeline application including one or more pipeline objects; identifying a first input data set on which to execute the pipeline application; executing the pipeline application on a first input data set to produce a first output data set; after executing the pipeline application on the first input data set, identifying a second input data set on which to execute the pipeline application; determining a set of differences between the first input data set and second input data set; and executing the pipeline application on the set of differences to produce a second output data set.

Abstract: A register file is provided. The register file includes a plurality of registers configured to form at least one register cluster, each of the registers being configured to have a virtual index defined for each cluster and a physical index defined for each register, and an index converting unit configured to convert the virtual index to the physical index.

Abstract: A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first and second storage locations and sense amplifier circuitry according to states of the first and second enable values. This includes transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state.

Abstract: A network device includes multiple packet processing engines implemented in parallel with one another. A spraying component distributes incoming packets to the packet processing engines using a spraying technique that load balances the packet processing engines. In particular, the spraying component distributes the incoming packets based on queue lengths associated with the packet processing engines and based on a random component. In one implementation, the random component is a random selection from all the candidate processing engines. In another implementation, the random component is a weighted random selection in which the weights are inversely proportional to the queue lengths.

Abstract: A video-rendering chip performs gain correction on received display input, based on a display temperature, to produce output values that are shown on the display. The video-rendering chip includes multipliers, a microprocessor, and a memory. The microprocessor receives a display temperature from a sensor, determines gain correction coefficients that correspond to the display temperature, and provides the correction coefficients to the multipliers. The multipliers then multiply the display input by the correction coefficients to produce the output values. The microprocessor may determine the correction coefficients utilizing a lookup table or a correction coefficient formula stored in the memory. The microprocessor may receive an updated display temperature periodically and may determine new correction coefficients that correspond to the updated display temperature. The microprocessor may receive updated display temperatures at fixed periods or at varying periods based on the previous display temperature.

Abstract: A system and method for limiting fixed pattern noise (FPN) in a time delay and integration (TDI) mode of operation of a complementary metal oxide semiconductor (CMOS) imaging device is disclosed. The system and method provide for each line time, selecting a pixel for each column of photosensitive elements in the along track direction to capture dark information such that the selected pixel does not correspond to a portion of a scene that was previously selected to capture dark information in a current TDI period. The dark information for the selected pixels is captured and summed for each column of photosensitive elements. This sum is then used during a next TDI time period to subtract FPN effects from the output of the corresponding column. This allows the dark sum information to be constantly updated while the image sensor is in use while only decreasing the responsitivity by (N?1)/N relative to an N pixel column of a traditional TDI operation.

Abstract: A terminal and a method extend a storage space. The terminal includes a contents receiver, an interface, an external memory measure unit, a store determining unit, and a transmission controller. The contents receiver receives contents via a network. The interface accesses at least one external memory. The external memory measure unit measures at least one of a speed of the interface, an available capacity and a use history of the external memory accessed via the interface. The store determining unit determines whether to store the contents in the external memory based on a value measured by the external memory measure unit. The transmission controller controls to transmit the contents to the external memory via the interface when it is determined that the contents are stored in the external memory.

Abstract: A method, apparatus and a data storage device are provided for implementing drive list mode for read and write transfers on a recordable surface of a storage device. Drive List mode provides a queue in a linked list to chain together multiple independent transfers on a single track. The multiple drive independent transfers include at least one of sequential transfers, near-sequential transfers, and random transfers on the single track. A drive list mode transfer of multiple independent transfers on the single track is enabled in one disk revolution, and requiring a single hardware setup for the drive list mode transfer.

Abstract: A system in accordance with the invention may include a data memory storing a multi-dimensional (e.g., a two-dimensional) data structure. An address generation unit is provided to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate real addresses by moving across the multi-dimensional data structure between pairs of end points. The pairs of end points (as well as parameters such as the step size between the end points) may be pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. A processor, such as a vector processor, may be configured to access (e.g., read or write data to) the data structure at the real addresses calculated by the address generation unit.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: Techniques for achieving storage and network isolation in a cloud environment are presented. A single Internet Protocol (IP) address is presented to multiple storage tenants that use storage in a cloud environment. When each tenant accesses the IP address, a specific identity of the tenant is resolved and the storage stack for that tenant is sent to the tenant's storage machine having the tenant's storage. The tenant is directly connected to its tenant storage machine thereafter.

Abstract: A data movement controller (20) for controlling the movement between a shared data store (18) and a local data store (16) such that the data can be used by a plurality of parallel data processing elements is described. The data movement controller (20) comprises a set of data registers (56, 58, 60) which, in use, are loaded with different data parameters (57, 61, 62) to define a plurality of different ways in which data is transferred between the shared data store (18) and a set of processing elements (12). The data parameters (57, 61, 62) define a set of time delays for transferring portions of the data to predefined ones of the plurality of processing elements (12) and the type of overall data transfer that is to be carried out.

Abstract: Incoming files are examined to detect abnormal files. The incoming files may be examined for a weak file structure, such as a weak file format structure or a weak file data structure, to detect abnormal files. A weak file structure includes file structures that do not conform to the file format of the file yet still loadable by a file loader of the file format. The incoming files may also be examined for suspicious loading in memory to detect abnormal files.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a first block of data is written to a group of memory cells at a first memory location in single-level cell (SLC) mode. The first block of data is copied from the first memory location to a group of memory cells at a second memory location to provide a backup copy of the first block of data during a protected mode of operation. A second block of data is subsequently overwritten to the group of memory cells at the first memory location so that the first memory location stores both the first and second blocks of data in multi-level cell (MLC) mode.

Abstract: The subject disclosure relates to analyzing memory allocations for one or more computer-implemented processes. In particular, in conjunction with employing tags for tracking memory allocation commands, currently allocated memory can be examined for various characteristics of inefficient memory use. For example, as memory is initially allocated, a predetermined bit pattern can be written to the newly allocated memory. Thus, detection of the predetermined bit pattern can be indicative of wasted memory use. Moreover, additional features can be provided to both analyze data and present views associated with that analysis relating to identification of memory fragmentation, over-allocation, sparse memory use, duplication of allocations, multiple module loads, and so forth.

Abstract: Memory leak detection can be automated by assigning and recording an increasing sequence number to each memory allocation requested by an action. Call stacks associated with the action are also recorded. Several repetitions of the action can be executed. Allocations that occur in each action and that have similar or matching callstacks are defined as leaks. Allocations that do not have matches can be ignored.

Abstract: A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.

Abstract: A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.

Abstract: In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.

Abstract: A key transport method for transporting a key from a buffer memory to an encryption/decryption unit is provided. The method includes logically dividing bits of the key into key segments, wherein each of the key segments has a start position and a segment length. The method also includes setting a transmission length belonging to each of key segments based on the start positions and the segment lengths of the key segments; assigning a transmission bit stream belonging to each of the key segments from the bits of the key according to the start positions and the transmission lengths of the key segments; determining a transmission sequence; and sending the start position, the segment length and the transmission bit stream belonging to each of the key segments to the encryption/decryption unit from the buffer memory based on the transmission sequence. Accordingly, the method can transport the key safely.

Abstract: Read messages are grouped by a plurality of unique sequence identifications (IDs), where each of the sequence IDs corresponds to a specific read sequence, consisting of all read and read-ahead requests related to a specific storage segment that is being read sequentially by a thread of execution in a client application. The storage system uses the sequence id value in order to identify and filter read-ahead messages that are obsolete when received by the storage system, as the client application has already moved to read a different storage segment. Basically, a message is discarded when its sequence id value is less recent than the most recent value already seen by the storage system. The sequence IDs are used by the storage system to determine corresponding read-ahead data to be loaded into a read-ahead cache.

Abstract: Various methods and systems for securing access to hash-based storage systems are disclosed. One method involves receiving information to be stored in a storage system from a storage system client and then generating a key. The key identifies the information to be stored. The value of the key is dependent upon a secret value, which is associated with the storage system. The key is generated, at least in part, by applying a hash algorithm to the information to be stored. The key can then be returned the key to the storage system client. The storage system client can then use the key to retrieve the stored information.