With Shared Cache (epo) Patents (Class 711/E12.038)
  • Software Transactional Memory for Dynamically Sizable Shared Data Structures
    Publication number: 20080098181
    Abstract: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of our obstruction-free STM implementation is its ability to use of modular contention managers to ensure progress in practice.
    Type: Application
    Filed: December 20, 2007
    Publication date: April 24, 2008
    Inventors: Mark Moir, Victor Luchangco, Maurice Herlihy
  • PROCESSING DEVICE, COMPUTER SYSTEM, AND MOBILE APPARATUS
    Publication number: 20080065833
    Abstract: A processing device included on a single chip includes processors capable of executing tasks in parallel and a cache memory shared by the processors, wherein the cache memory includes single-port memories and read data selection units, each of the single-port memories have one data output port, and each of the read data selection units is in a one-to-one association with each of the processors and selects a single-port memory which stores data to be read to a associated processor, from among the single-port memories.
    Type: Application
    Filed: September 6, 2007
    Publication date: March 13, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tetsu Hosoki, Masaitsu Nakajima