Abstract: A coprocessor performs operations on behalf of processes executing in processors coupled thereto, and accesses data operands in memory using real addresses. A process executing in a processor generates an effective address for a coprocessor request, invokes the processor's address translation mechanisms to generate a corresponding real address, and passes this real address is the coprocessor. Preferably, the real address references a block of additional real addresses, each for a respective data operand. The coprocessor uses the real address to access the data operands to perform the operation. An address context detection mechanism detects the occurrence of certain events which could alter the context of real addresses used by the coprocessor or the real addresses themselves.

Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.

Abstract: A component of a computing device, such as the kernel of an operating system, is arranged to identify real time processes running on the device and transparently lock the memory owned by such processes to avoid them being paged out. The kernel is also able to inspect all inter-process communications originated by the real time threads running in such processes, in order to ascertain what other processes they invoke, and, if they have the potential to block a real time operation, the kernel is arranged to lock the areas of memory these processes reference. This procedure operates recursively, and ensures that page faults which might affect the operation of any real time process do not occur.

Abstract: Some embodiments of the present invention include a memory management unit (MMU) configured to, in response to a write access targeting a guest page mapping of a guest virtual page number (GVPN) to a guest physical page number (GPPN) within a guest page table, identify a shadow page mapping that associates the GVPN with a physical page number (PPN). The MMU is also configured to determine whether a traced write indication is associated with the shadow page mapping and, if so, record update information identifying the targeted guest page mapping. The update information is used to reestablish coherence between the guest page mapping and the shadow page mapping. The MMU is further configured to perform the write access.

Abstract: A computer implemented method optimizes memory page sizes during runtime. A process is identified from a policy file. The policy file contains at least one policy based threshold. A resource usage profiler monitors the process during runtime. The resource usage profiler determines whether the process exceeds the set of stated desired policies from the at least one policy based threshold. If the process exceeds the set of stated desired policies from the set of policy based thresholds, a performance projection for the process is executed to determine whether the process would experience a performance benefit from a different page size. Responsive to determining that the process would experience the performance benefit from the different page size, the page size for the process is changed.

Abstract: In one embodiment, a processor includes an address generation unit having a memory context logic to determine whether a memory context identifier associated with an address of a memory access request corresponds to an agent memory context identifier for the processor, and to handle the memory address request based on the determination. Other embodiments are described and claimed.

Abstract: One or more embodiments provides a shadow page table used by a virtualization software wherein at least a portion of the shadow page table shares computer memory with a guest page table used by a guest operating system (OS) and wherein the virtualization software provides a mapping of guest OS physical pages to machine pages.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: Methods and systems are described for excluding an addressable entity from a translation of source code. A first translation is received that is translated from source code including a first addressable entity specified in a programming language and that includes a first translation of the first addressable entity. Excluding information is received that identifies the first translation of the first addressable entity as excludable from a second translation, of the source code, translated from the first translation. Translation configuration information is received for translating the first translation. In response to the translation configuration information being received, the first translation is translated into the second translation excluding, based on the excluding information, the first addressable entity.

Abstract: A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a virtual machine context. A plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context are stored within a TLB. Memory protection bits for the plurality of TLB entries are logically combined to enforce memory protection on the virtual machine application.

Abstract: Activity level of memory pages is classified in virtual machine environment, so that processes such as live VM migration and checkpointing, among others, can be carried out more efficiently. The method includes the steps of scanning page table entries of hypervisor-managed page tables continuously over repeating scan periods to determine whether memory pages have been accessed or not, and for each memory page, determining an activity level of the memory page based on whether the memory page has been accessed or not since a prior scan and storing the activity level of the memory page. The activity level of the memory page may be represented by one or more bits of its page table entry and may be classified as having at least two states ranging from hot to cold.

Abstract: A multithread processor including: an execution unit including a physical processor; and a translation lookaside buffer (TLB) which converts, to a physical address, a logical address output from the execution unit, and logical processors are implemented on the physical processor, a first logical processor that is a part of the logical processors constitutes a first subsystem having a first virtual space, a second logical processor that is a part of the logical processors and different from the first logical processor constitutes a second subsystem having a second virtual space, each of the first and the second subsystems has processes to be assigned to the logical processors, and the logical address includes: a first TLB access virtual identifier for identifying one of the first and the second subsystems; and a process identifier for identifying a corresponding one of the processes in each of the first and the second subsystems.

Abstract: A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

Abstract: Memory address translation buffering circuitry is provided comprising a primary storage bank and a secondary storage bank. Storage bank accessing circuitry is provided to perform a parallel lookup of the primary storage bank and the secondary storage bank for virtual to physical address translation entries. Buffering management circuitry is configured to transfer an address translation entry between the primary storage bank and the secondary storage bank dependent upon an occupancy level of at least one of the primary storage bank and secondary storage bank.

Abstract: A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.

Abstract: A plurality of address spaces are assigned to an adapter. To select a particular address space for the adapter, a requestor identifier and address space identifier provided in a request by the adapter are used. Each address space may have a different address translation mechanism associated therewith.

Abstract: A storage system is provided. The storage system comprises a storage media, a storage controller and a host. The storage controller is connected to the storage media. The host is connected to the storage controller, and performs a physical resource management algorithm for managing a physical resource of the storage media, so as to output at least a media operation command to the storage controller. The storage controller performs the media operation command to manage the storage media. A storage management method is also provided.

Abstract: A lookup operation is performed in a translation look aside buffer based on a first translation request as current translation request, wherein a respective absolute address is returned to a corresponding requestor for the first translation request as translation result in case of a hit. A translation engine is activated to perform at least one translation table fetch in case the current translation request does not hit an entry in the translation look aside buffer, wherein the translation engine is idle waiting for the at least one translation table fetch to return data, reporting the idle state of the translation engine as lookup under miss condition and accepting a currently pending translation request as second translation request, wherein a lookup under miss sequence is performed in the translation look aside buffer based on said second translation request.

Abstract: In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.

Abstract: Methods and apparatus related to techniques for translating requests between a full speed bus and a slower speed device are described. In one embodiment, a translation logic translates requests between a full speed bus (such as a front side bus, e.g., running relatively higher frequencies, for example at MHz levels) and a much slower speed device (such as a System On Chip (SOC) device (or SOC Device Under Test (DUT)), e.g., logic provided through emulation, which may be running at much lower frequency, for example kHz levels). Other embodiments are also disclosed.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: Lookup techniques are described, which can achieve improvements in energy efficiency, speed, and cost, of IP address lookup, for example, in devices and systems employing ternary content addressable memory (TCAM). The disclosed subject matter describes dividing a route table into several sub-tries with disjoint range boundaries. In addition, the disclosed subject matter describes storing sub-tries of a route table between a TCAM and a faster and less costly memory. The disclosed details enable various refinements and modifications according to system design and tradeoff considerations.

Abstract: Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.

Abstract: In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

Abstract: The disclosed embodiments provide a system that filters duplicate requests from an L1 cache for a cache line. During operation, the system receives at an L2 cache a first request and a second request for the same cache line, and stores identifying information for these requests. The system then performs a cache array look-up for the first request that, in the process of creating a load fill packet for the first request, loads the cache line into a fill buffer. After sending the load fill packet for the first request to the L1 cache, the system uses the cache line data still stored in the fill buffer and stored identifying information for the second fill request to send a subsequent load fill packet for the second request to the L1 cache without performing an additional cache array look-up.

Abstract: A processor 4 is provided with an instruction decoder 32 responsive to preload instructions PLD [r0] which trigger preload operations, such as page table walks and cache line fetches. An instruction decoder identifies if the memory address associated with the preload instruction matches a null value and suppresses the preload operation if the memory address does match the null value. The null value may be set under program control, it may be predetermined as a fixed value (e.g. zero) or may be set under hardware control, such as corresponding to memory addresses of a page identified by a memory management unit as non-accessible.

Abstract: A hypervisor prepares a guest region identifier (RID)-physical region identifier (RID) mapping table for dynamically registering and managing items and performs RID conversion using the guest RID-physical RID mapping table. When the mapping table is used, since it is unnecessary to provide a specific information area representing logical partitions (LPARs) corresponding to respective guests in an RID to be converted, there is no limitation concerning the number of LPARs and a problem in operation can be eliminated.

Abstract: A computing system supports a virtualization platform with dedicated cache access. The computing system is configured for usage with a memory and a cache and comprises an instruction decoder configured to decode a cache-line allocation instruction and control logic. The control logic is coupled to the instruction decoder and controls the computing system to execute a cache-line allocation instruction that loads portions of data and code regions of the memory into dedicated cache-lines of the cache which are exempted from eviction according to a cache controller replacement policy.

Abstract: Described herein are systems and methods that reduce the latency which may occur when a level one (L1) cache issues a request to a level two (L2) cache, and that ensure that a translation requests sent to an L2 cache are flushed during a context switch. Such a system may include a work queue and a cache (such as an L2 cache). The work queue comprises a plurality of state machines, each configured to store a request for access to memory. The state machines can monitor requests that are stored in the other state machines and requests that the other state machines issue to the cache. A state machine only sends its request to the cache if another state machine is not already awaiting translation data relating to the that request. In this way, the request/translation traffic between the work queue and the cache can be significantly reduced.

Abstract: A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions.

Abstract: A memory management apparatus has an ASID conversion table, an actual ASID use table, and a TLB flush control section. The ASID conversion table and the actual ASID use table manage virtual ASID, actual ASID and an overlap flag so that they are related for each VM. The TLB flush control section reads actual ASIDs allocated to VM as a switching target at the time of switching VM as a switching source into the VM as the switching target, determines whether the read actual ASID is allocated to the plurality of VMs in an overlapped manner with reference to the overlap flag, and sets the actual ASID in the read actual ASIDs determined being allocated in the overlapped manner as a target for the TLB flush.

Abstract: A data processing apparatus includes: a slide storage unit sequentially storing input data; a search unit searching for a data string, stored in the slide storage unit, matched with an input data string including the input data that is continuously input; a length generation unit selecting one from the data string, obtaining a length, and generating a length value; an address value generation unit obtaining a position, in the slide storage unit, of start data in the data string and generating an address value; a translation unit translating a predetermined number of address values among address values having a high appearance frequency among address values generated by the address value generation unit into a translation address value having a value equal to or smaller than a predetermined value according to the appearance frequency of the address value; and an encoding unit encoding the length value and the translation address value.

Abstract: Memory management methods and computing apparatus with memory management capabilities are disclosed. One exemplary method includes mapping an address from an address space of a physically-mapped device to a first address of a common address space so as to create a first common mapping instance, and encapsulating an existing processor mapping that maps an address from an address space of a processor to a second address of the common address space to create a second common mapping instance. In addition, a third common mapping instance between an address from an address space of a memory-management-unit (MMU) device and a third address of the common address space is created, wherein the first, second, and third addresses of the common address space may be the same address or different addresses, and the first, second, and third common mapping instances may be manipulated using the same function calls.

Abstract: An access request including a client address for data is received. A metadata server determines a mapping between the client address and storage unit identifiers for the data. Each of the one or more storage unit identifiers uniquely identifies content of a storage unit and the metadata server stores mappings on storage unit identifiers that are referenced by client addresses. The one or more storage unit identifiers are sent to one or more block servers. The one or more block servers service the request using the one or more storage unit identifiers where the one or more block servers store information on where a storage unit is stored on a block server for a storage unit identifier. Also, multiple client addresses associated with a storage unit with a same storage unit identifier are mapped to a single storage unit stored in a storage medium for a block server.

Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.

Abstract: A disjoint instruction for accessing operands in memory while executing in a processor of a plurality of processes interrogates a state indicator settable by other processors to determine if the disjoint instruction accessed the operands without an intervening store operation from another processor to the operand. A condition code is set based on the state indicator.

Abstract: Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs).

Abstract: Apparatus for data processing 2 is provided with processing circuitry 8 which operates in one or more secure modes 40 and one or more non-secure modes 42. When operating in a non-secure mode, one or more regions of the memory are inaccessible. A memory management unit 24 is responsive to page table data to manage accesses to the memory which includes a secure memory 22 and a non-secure memory 6. Secure page table data 36, 38 is used when operating in one of the secure modes. A page table entry within the hierarchy of page tables of the secure page table data includes a table security field 68, 72 indicating whether or not a further page table pointed to by that page table entry is stored within the secure memory 22 or the non-secure memory 6. If any of the page tables associated with a memory access are stored within the non-secure memory 6, then the memory access is marked with a table attribute bit NST indicating that the memory access should be treated as non-secure.

Abstract: According to one embodiment, a memory controller comprises a counter and a setting module. The counter is configured to count the number of valid pages in a block includes a page to be invalidated, when data is written in a nonvolatile memory. The setting module is configured to set the block as an object of compaction when the number of valid pages counted by the counter is smaller than a predetermined number.

Abstract: Data deduplication compression in a streaming storage application, is provided. The disclosed deduplication process provides a deduplication archive that enables storage of the archive to, and extraction from, a streaming storage medium. One implementation involves compressing fully sequential data stored in a data repository to a sequential streaming storage, by: splitting fully sequential data into data blocks; hashing content of each data block and comparing each hash to an in-memory lookup table for a match, the in-memory lookup table storing all hashes that have been encountered during the compression of the fully sequential data; for each data block without a hash match, adding the data block as a new data block for compression of fully sequential data; and encoding duplicate data blocks using the in-memory lookup table into data segments.

Abstract: There is provided a method and apparatus for implementing a virtual mirror of a primary storage device (106) on a secondary storage device (108). The method comprises providing a map (124a) for translating primary data storage locations on said primary storage device (106) to secondary data storage locations on said secondary storage device (106) and utilising said map (124a) to enable data stored on said secondary storage device (108) to mirror data stored on said primary storage device (106). By providing such a method, the requirements of the primary and secondary disks (106, 108) can be decoupled such that a smaller secondary disk (108) could be used with a larger primary (106) which will not be filled to capacity. This reduces the unused capacity on the secondary disk (108) which would otherwise be wasted.

Abstract: A code injection attack detecting apparatus and method are provided. The code injection attack may be detected based on characteristics occurring when a malicious code injected by the code injection attack is executed. For example, the code injection attack detecting apparatus and method may detect that a code injection attack occurs when a buffer miss is detected, a page corresponding to an address is updated, a mode of the page corresponding to the address is in user mode, and/or the page corresponding to the page is inserted by an external input.

Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).

Abstract: A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

Abstract: Embodiments of the present invention provide a system that handles way mispredictions in a multi-way cache. The system starts by receiving requests to access cache lines in the multi-way cache. For each request, the system makes a prediction of a way in which the cache line resides based on a corresponding entry in the way prediction table. The system then checks for the presence of the cache line in the predicted way. Upon determining that the cache line is not present in the predicted way, but is present in a different way, and hence the way was mispredicted, the system increments a corresponding record in a conflict detection table. Upon detecting that a record in the conflict detection table indicates that a number of mispredictions equals a predetermined value, the system copies the corresponding cache line from the way where the cache line actually resides into the predicted way.

Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.

Abstract: A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of a subset of the pages, the virtual page number and the physical page number in correspondence, and a conversion processing unit operable to convert a virtual address into a physical address in accordance with content stored in the buffer.

Abstract: Systems and methods are provided that utilize shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.

Abstract: A computer implemented method searches a unified translation lookaside buffer. Responsive to a request to access the unified translation lookaside buffer, a first order code within a first entry of a search priority configuration register is identified. A unified translation lookaside buffer is then searched according to the first order code for a hashed page entry. If the hashed page entry is not found when searching a unified translation lookaside buffer according to the first order code, a second order code is identified within a second entry of the search priority configuration register. The unified translation lookaside buffer is then searched according to the second order code for the hashed page entry.