Decentralized Address Translation, E.g., In Distributed Shared Memory Systems, Etc. (epo) Patents (Class 711/E12.066)
  • Publication number: 20090282198
    Abstract: According to at least some embodiments, systems and methods are provided for mapping, by a first processor, of a memory portion that is inaccessible to a second processor to at least a segment of a pre-reserved region of memory addresses used by the second processor to enable the second processor to access the contents of the memory portion. The mapped memory portion comprising two temporary pages and all pages of data in a buffer to be shared excepting a first block of data and a last block of data, and copying the contents of the first block of data and the last block of data into its respective temporary page, at least one of the first and last blocks of data are unaligned prior to being copied into its respective temporary page. In some embodiments, at least one of the first and last blocks of data, prior to being copied into its respective temporary page, comprises a portion of data to be shared on a same cache line as a portion of data not to be shared.
    Type: Application
    Filed: June 30, 2008
    Publication date: November 12, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nourredine HAMOUDI, Sripal A. BAGADIA
  • Publication number: 20090228663
    Abstract: A shared memory control method parallel processes ordered access requests (AccReq) for a shared memory received from processors or threads. The method includes dividing the shared memory into memory areas, receiving the ordered AccReq for each memory area, executing the AccReq when a described order number (OrdNum) described in the AccReq matches an OrdNum expected for access, increasing or decreasing the expected OrdNum expected by the memory area to be accessed by a predetermined number when the type of the AccReq is “READ ONLY” or “WRITE” or “NO OPERATION”, saving the AccReq into a queue independently assigned to each memory area when the described OrdNum in the AccReq does not match the expected OrdNum, and sequentially fetching the AccReq from the queue and executing the AccReq as long as a described OrdNum described in the AccReq preserved in the queue matches an expected OrdNum corresponding to the queue.
    Type: Application
    Filed: February 27, 2009
    Publication date: September 10, 2009
    Applicant: NEC CORPORATION
    Inventor: Kiyohisa ICHINO
  • Publication number: 20090228662
    Abstract: The present invention discloses a multi-channel memory storage device and control method thereof. The method arranges physical locations for a file's data stored in the storage device. The storage device includes a plurality of memories. The major feature of the method is to decide whether the data is written to a single memory or parallel memories according to the size of the data.
    Type: Application
    Filed: September 3, 2008
    Publication date: September 10, 2009
    Applicant: A-DATA TECHNOLOGY CO., LTD.
    Inventors: Hui-Neng Chang, Chuan-Sheng Lin
  • Publication number: 20090216958
    Abstract: A data processing system in the form of an integrated circuit 2 includes a general purpose programmable processor 4 and a hardware accelerator 6. A shared memory management unit 10 provides memory management operations on behalf of both of the processor core 4 and the hardware accelerator 6. The processor 4 and the hardware accelerator 6 share a memory system 8. A first communication channel 12 between the processor 4 and the hardware accelerator 6 communicates at least control signals therebetween. A second communication channel 14 coupling the hardware accelerator 6 and the memory system 8 allows the hardware accelerator 6 to perform its own data access operations upon the memory system 8.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 27, 2009
    Applicant: ARM Limited
    Inventors: Stuart David Biles, Nigel Charles Paver, Chander Sudanthi
  • Publication number: 20080215825
    Abstract: A method and an apparatus for having a memory shared by a plurality of processors are disclosed. The digital processing apparatus in accordance with an embodiment of the present invention comprises a memory, a main processor connected to one side of the memory through a first memory bus, and application processors in a quantity of n connected parallel to the other side of the memory through a second memory bus. Each application processor performs at least one predetermined function. The main processor is connected parallel to the n application processors through a control bus, and delivers a control signal to at least one application processor through the control bus. With the present invention, the structure of a digital processing apparatus can be simplified, and the cost and size of a digital processing apparatus can be minimized.
    Type: Application
    Filed: June 13, 2006
    Publication date: September 4, 2008
    Applicant: MTEKVISION CO., LTD.
    Inventor: Kyung-chul Min
  • Publication number: 20080183973
    Abstract: Embodiments include methods, apparatus, and systems for snapshots in distributed storage systems. One method of software execution includes using a version tree to determine what data blocks are shared between various storage nodes in the version tree in order to create a clone or a snapshot of a storage volume in a distributed storage system that uses quorum-based replication.
    Type: Application
    Filed: January 31, 2007
    Publication date: July 31, 2008
    Inventors: Marcos K. Aguilera, Alistair Veitch, Susan Spence
  • Publication number: 20080126740
    Abstract: Sensitive data structures, such as type data structures, can be used by untrusted application programs without necessarily exposing the sensitive data structures directly. For example, untrusted components, such as application programs that may or may not be type safe, can be allowed to operate in a lower-privilege mode. In addition, the application programs can be associated with an address space with limited permissions (e.g., read-only) to a shared memory heap. Requests by the untrusted components for sensitive data structures can then be handled by trusted components operating in a higher-privilege mode, which may have broader permissions to the shared memory heap. If the requests by the untrusted components are deemed to be valid, the results of the requests can be shared with the lower-privilege mode components through the shared memory heap.
    Type: Application
    Filed: December 7, 2006
    Publication date: May 29, 2008
    Applicant: MICROSOFT CORPORATION
    Inventors: David Charles Wrighton, Robert Sadao Unoki