Abstract: A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

Abstract: Operation control circuits start a first operation of any of memory cores in response to a first operation command, start a second operation of any of the memory cores in response to a second operation command, and terminate the first operation and continue the second operation in response to a termination command to terminate operations of the plurality of memory cores. For example, the semiconductor memory is mounted on a system together with a controller accessing the semiconductor memory. The termination of the operation in response to the termination command is judged in accordance with an operation state of the memory core. Accordingly, it is possible to terminate the operation of the memory core requiring the termination of operation without specifying the memory core from outside.

Abstract: A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation.

Abstract: The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.

Abstract: A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

Abstract: A method for re-allocating memory partition space is provided. The method comprises determining when a first memory partition is full or has reached a threshold value, determining that a second memory partition has unused storage space that can be allocated to the first memory partition, and assigning the unused storage space from the second memory partition to the first memory partition. A memory controller embedded within the mass storage device and having an interface to an external host assigns the unused storage space from the second memory partition to the first memory partition.

Abstract: This information recording/playback apparatus has a memory for storing data and which includes a plurality of storage cells configured from a capacitor for accumulating charge. When an issue interval time for issuing a read/write command to an arbitrary storage cell is shorter than a threshold time for retaining a charge amount for the arbitrary storage cell to read correct data, a dummy read command for simulatively reading data stored in storage cells other than the arbitrary storage cell is issued to storage cells other than the arbitrary storage cell, and dummy read processing is executed for replenishing charge in the capacitor configuring storage cells other than the arbitrary storage cell.

Abstract: A memory expansion blade for a multi-protocol architecture, includes dual inline memory modules (DIMMs) and a multi-protocol memory controller coupled to the DIMMs and operable to control operations of the DIMMs. The multi-protocol memory controller includes one or more memory channel controllers, with each of the memory channel controllers coupled to a single channel of DIMM, and where the DIMM in each single channel operate according to a specific protocol. The controller further includes a protocol engine coupled to the memory channel controllers, where the protocol engine is configurable to accommodate one or more of the specific protocols, and a system interface coupled to the protocol engine and configurable to provide electrical power and signaling appropriate for the specific protocols.

Abstract: A semiconductor memory device includes a first nonvolatile memory which has a first external interface and is capable of recording 1-bit data in one memory cell, a second nonvolatile memory which has a test terminal interface and is capable of recording a plurality of data in one memory cell, and a control unit which has a second external interface and is configured to control a physical state of an inside of the second nonvolatile memory.

Abstract: A system, and a corresponding method, are used to implement rank sparing. The system includes a memory controller and one or more DIMM channels coupled to the memory controller, where each DIMM channel includes one or more DIMMS, and where each of the one or more DIMMs includes at least one rank of DRAM devices. The memory controller is loaded with programming to test the DIMMs to designate at least one specific rank of DRAM devices as a spare rank.

Abstract: An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal.

Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.

Abstract: The illustrative embodiments described herein provide an apparatus and method for managing data in a hybrid drive system. In one embodiment, a process determines whether the detachable memory contains clean data in response to identifying that a cache portion of a detachable memory is unavailable. The clean data does not require a disk to be in a spin state to be removed from the detachable memory. The process removes the clean data from the detachable memory in response to determining that the detachable memory contains the clean data. The process stores the data on the detachable memory.

Abstract: Saving state of Random Access Memory (RAM) in use by guest operating system software is accomplished using state saving software that starts a plurality of compression threads for compressing RAM data blocks used by the guest. Each compression thread determines a compression level for a RAM data block based on a size of a queue of data to be written to disk, then compresses the RAM data block, and places the compressed block in the queue.

Abstract: According to one embodiment, the present disclosure generally provides a method for improving the performance of a cache of a processor. The method may include storing a plurality of data in a data Random Access Memory (RAM). The method may further include holding information for all outstanding requests forwarded to a next-level memory subsystem. The method may also include clearing information associated with a serviced request after the request has been fulfilled. The method may additionally include determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem. The method may further include matching fulfilled requests serviced by the next-level memory subsystem to at least one requester who issued requests while an original request was in-flight to the next level memory subsystem.

Abstract: In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.

Abstract: A data management system includes a data processor configured to provide a file system module configured to store first data in a flash memory in block units and a filter layer module configured to receive second data from the file system module and to store the second data in a phase-change random access memory (PRAM) in sub-block units. The filter layer module may be configured to identify difference data in the second data received from the file system module by comparing the received second data and third data stored in the PRAM, and to write the identified difference data to the PRAM. The second data may include file metadata and the first data may include data other than file metadata. The sub-block units may be byte units.

Abstract: A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

Abstract: A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.

Abstract: An optical storage device that includes a memory and a controller. The memory includes a command queue to store advanced technology attachment (ATA) commands sent by a host device. The controller executes the commands, in which at least a subset of the commands are executed in a sequence that is different from a sequence in which the commands are sent by the host device.

Abstract: An optical storage device that includes a memory and a controller. The memory includes a command queue to store advanced technology attachment (ATA) commands sent by a host device. The controller executes the commands, in which at least a subset of the commands are executed in a sequence that is different from a sequence in which the commands are sent by the host device.

Abstract: A physical area management table (105) and a pointer table (106) are stored in a nonvolatile auxiliary storage memory (107). When a logical-physical conversion table (108) is updated (restored) in a main storage memory (140), the restored area is determined in a re-arrangement way by the pointer table to avoid rewrite concentration on the main storage memory (140). Immediately after data is written in the main storage memory (140), the state of the physical block on the physical area management table (105) is updated. Consequently, even if power interruption occurs, it is possible to reliably judge if the data is valid or not.

Abstract: To provide a sample-and-hold method which can limit the storage capacity of storage media needed to a bare minimum and can independently manage a series of data contained in a predetermined interval before the arrival time of a trigger signal and a series of data contained in a predetermined interval after the arrival time of the trigger signal by separating them clearly.

Abstract: A peripheral for a computer and a method of using the peripheral is for installing software onto the computer using Direct Memory Access. The peripheral comprises a computer accessible medium and a program product. The program product has codes to read and write to the Random Access Memory of the computer; and to bypass restrictions of the host computer Operating System that prevent the peripheral from gaining full access to all portions of the host computer's Random Access Memory. The preferred methods of using the peripheral automatically install software on a computer or copies forensic data from the computer's Random Access Memory once the peripheral is connected to the computer.

Abstract: A method of converting a hybrid hard disk drive (HDD) to a normal HDD when a system is powered on depending on whether the total number of defective blocks in a non-volatile cache (NVC) exceeds a predetermined threshold. The method of converting a hard disk drive (HDD) from a hybrid HDD to a normal HDD where the HDD has a normal hard disk and a non-volatile cache includes the steps of determining whether a mode conversion flag is enabled during a power-on period. When the mode conversion flag is enabled, operating the HDD as a normal HDD. When the mode conversion flag is disabled, determining whether an operating mode of the HDD is a normal mode or a hybrid mode. When the operating mode of the HDD is in the normal mode, the HDD operates as a normal HDD. A determination is made when the HDD is in the hybrid mode as to whether the total number of defective blocks in the non-volatile cache is greater than a predetermined threshold.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: A microcode patching system, including a memory unit comprising a first memory storing at least one microcode main instruction and a second memory providing at least one microcode patch instruction, accessed according to a selected output address, an address selecting unit providing a first output address, and a trap and patch logic unit coupled between the address selecting unit and the memory unit, determining if the first output address matches any of at least one bug address, and selecting a selected patch address for accessing the second memory or the first output address as a second output address if the first output address matches one or none of the bug addresses, respectively, wherein the second output address is coupled to the memory unit.

Abstract: According to one embodiment, an information processing apparatus includes a main body, a display panel, a position sensor, a disk drive and a controller. The display panel is rotatably attached to the main body between a close position and an open position. The position sensor detects a position of the display panel. The disk drive includes a nonvolatile memory and a disc medium. The controller sets the disk drive to a first mode when the display panel is in the open position and a second mode when the display panel is in the close position. In the first mode, an access to the disc medium is permitted. In the second mode, the access to the disc medium is inhibited and the nonvolatile memory temporary stores the data input to the disk drive.

Abstract: A data storage system includes a non-volatile memory, a disc recording medium, a non-volatile memory buffer, operatively disposed between a host interface and the non-volatile memory, which stores a portion of data stored in the non-volatile memory, and a disc buffer, operatively disposed between the host interface and the disc recording medium, which stores a portion of data stored in the disc recording medium. The data storage system may be configured to receive an access address from a host operatively connected to the host interface, and sequentially determine whether the access address exists in one of the non-volatile memory buffer, the non-volatile memory, the disc buffer, and the disc recording medium, in that order.

Abstract: An apparatus and method for managing data, the data-managing apparatus including: a command receiver that receives a move command for data, a memory interface unit that accesses a first storage device currently storing the data and second storage device to store the data according to the move command, and a memory-managing unit that moves the data from the first storage device to the second storage device without transferring the data through a system memory.

Abstract: Embodiments of the present invention provides a system controller interfacing point-to-point subsystems consisting of solid state memory. The point-to-point linked subsystems enable high bandwidth data transfer to a system controller. The memory subsystems locally control the normal solid state disk functions. The independent subsystems thus configured and scaled according to various applications enables the memory storage system to operate with optimal data bandwidths, optimal overall power consumption, improved data integrity and increased disk capacity than previous solid state disk implementations.

Abstract: The present invention is a method and apparatus to buffer data. A buffer memory of a first type stores data associated with a connection identifier corresponding to a channel in a network. The data is organized into at least one chunk based on a linked list. The connection identifier identifies a connection in the channel. The data is part of a data stream associated with the connection. A packet memory of a second type provides access to the stored data when a transfer condition occurs.

Abstract: The present invention achieves data relocation in accordance with a user's policies, in an environment where a plurality of storage devices coexist. The volumes belonging to storage devices A-D are managed virtually integrally. A host recognizes a plurality of storage devices A-D as a single virtual storage device. The user is able to group arbitrarily each volume belonging to the storage system, as a plurality of storage layers 1-3. For example, storage layer 1 can be defined as a high-reliability layer, storage layer 2, as a low-cost layer, and storage layer 3, as an archive layer. Each storage layer is constituted by a group of volumes corresponding to respective policies (high reliability, low cost, archiving). The user designates volumes V1 and V2 to be moved, in group units, and indicates a storage layer forming a movement destination, whereby the data is relocated.

Abstract: A memory module system, a memory module, a buffer device, a memory module printed circuit board, and to a method for operating a memory module is disclosed. In one embodiment, the memory module system includes at least a first, a second, and a third memory module. The first memory module is connected with the second memory module via a first connection and with the third memory module via a second connection, and is designed and equipped such that data, address, and/or control signals received by the first memory module are transmitted to the second memory module via the first connection and to the third memory module via the second connection.

Abstract: A block based storage system and method uses RAM memory to implement the buffers and is made redundant by replicating the buffer cache to an in-memory buffer cache on a separate caching unit. Replication can be done using one or more parity schemes (e.g. RAID 1, RAID 5, RAID 6) and/or other replication processes.