Abstract: A system or a device can include a processor core comprising one or more hardware processors; a processor memory to cache data; a memory link interface to couple the processor core with one or more attached memory units; and a platform firmware to determine that a device is connected to the processor core across the memory link interface; determine that the device comprises an attached memory; determine a range of at least a portion of the attached memory available for the processor core; map the range of the portion of the attached memory to the processor memory; and wherein the processor core is to use the range of the portion of the attached memory and the processor memory to cache data.

Abstract: The disclosure relates to a 5th Generation (5G) or pre-5G communication system for supporting a higher data rate than a 4th Generation (4G) communication system such as Long Term Evolution (LTE). According to various embodiments of the disclosure, an apparatus of a base station in a wireless communication system is provided. The apparatus includes: a master Field Programmable Gate Array (FPGA); a plurality of slave FPGAs controlled by the master FPGA; and an address masker coupled to the master FPGA and the plurality of slave FPGAs, wherein the address masker is configured to: receive different address bits assigned respectively to the plurality of slave FPGAs by the master FPGA; for the different address bits, mask bit values at a specific position with the same value; and transmit masked address bits corresponding respectively to the plurality of slave FPGAs.

Abstract: A memory system and a memory controller are disclosed. By determining whether an error has occurred in target data stored in a predetermined target memory area of the memory device and determining, in response to whether an error has occurred in the target data, the magnitude of the supplied power based on a first operation parameter selected among predetermined candidate operation parameters in connection with the magnitude of the supplied power, the memory controller may stably drive a firmware, and may handle an operation error of the firmware due to a change in external environment.

Abstract: Various implementations described herein refer to a device having an address bus that provides multi-port addresses from multiple ports including a first address from a first port and a second address from a second port. The device may have column contention-detection circuitry that receives the multi-port addresses from the address bus, compares the first address from the first port with the second address from the second port and provides a contention adjustment signal based on the comparison between the first address and the second address. The device may have bitline collision circuitry that receives the contention adjustment signal, senses wire-to-wire variation related to bitline coupling effects and provides a bitline collision signal based on sensing the bitline coupling effects.

Abstract: A dynamic random access memory (DRAM) and a production method, a semiconductor packaging component and a packaging method. The production method comprises: providing a memory wafer, the memory wafer being provided with a memory bare chip which is provided with a top metal layer which is provided with a power source bonding pad, a signal bonding pad, and a micro bonding pad, and an internal bus led out of the memory bare chip being electrically connected to the micro bonding pad; repairing the memory wafer; if a yield of the memory wafer is greater than or equal to a preset threshold, rearranging the micro bonding pad to form a butt-joint bonding pad which is electrically connected to the micro bonding pad and the power source bonding pad. A structure of the DRAM is not significantly changed, a data bandwidth of the DRAM is increased, and a high yield is ensured.

Abstract: A memory mapping system for compactly mapping dissimilar memory systems and methods for manufacturing and using same. The mapping system maps a source memory system into a destination memory system by partitioning the source memory system and disposing memory contents within the partitioned source memory system into the destination memory system. In one embodiment, the mapping system factorizes a source data width of the source memory system in terms of a destination data width of the destination memory system to form at least one data sub-width. A source memory sub-region is defined for each data sub-width. The memory contents associated with each source memory sub-region are disposed within the destination memory system in a side-by-side manner across selected destination memory registers of the destination memory system. The mapping system thereby can compactly map the memory contents into the destination memory system without a loss of valuable memory space.