Abstract: Described and claimed is a system for securely storing and processing raw data from a plurality of different data sources. The system comprises a server with a processing unit and volatile memory, an external non-volatile memory connected to the server and a plurality of data sources. The server is adapted for encrypting raw data received from each data source of the plurality of data sources and storing the encrypted raw data on the external non-volatile memory, retrieving and decrypting encrypted raw data stored on the at least one external non-volatile memory and processing raw data retrieved from the at least one external non-volatile memory. Further, a corresponding server and a method for securely storing and processing raw data from a plurality of different data sources are described and claimed.

Abstract: A memory device is described, including a command decoder configured to receive a copy command to copy data stored in a first memory location to a second memory location without transmitting the data to an external controller, a memory array electrically connected to the command decoder and including a plurality of memory locations including the first memory location and the second memory location, a data line electrically connected to the memory array and configured to receive, from the first memory location, the data to be transmitted to the second memory location through the same data line, and an output buffer configured to store the data received from the first memory location through the data line to be written into the second memory location without transmitting the data to the external controller.

Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).

Abstract: Memory access control, as described herein, can leverage persistent memory to store data that is generally stored in a non-persistent memory. An example method for memory access control can include receiving, by control circuitry resident on a memory device, a memory access request targeting an address of a volatile (e.g., non-persistent) memory component of the memory device and determining characteristics of data associated with the targeted address. The method can further include accessing data at the targeted address of the volatile memory component in response to determining that the characteristics of the data meet a first criterion and accessing data at another address of a non-volatile memory component in response to determining that the characteristics of the data meet a second criterion.

Abstract: Various embodiments described herein provide for secure data communication between a host system and a memory sub-system. For example, some embodiments use a salt value, symmetric encryption, and asymmetric encryption to facilitate secure data communication between the host system and the memory sub-system.

Abstract: A system and method stores a database file into Flash memory or other write-constrained storage.

Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

Abstract: An information processing apparatus that is capable of improving access to a nonvolatile semiconductor memory. The information processing apparatus includes a nonvolatile semiconductor memory that includes memory areas, a user interface that can accept a user operation, a memory device that stores a set of instructions, and one or more processor that executes the set of instructions to generate an erase command that instructs the semiconductor memory to execute an erasing process to each of the memory areas in a state where a user operation to the user interface is unacceptable.

Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

Abstract: A memory device includes an error code generator, one or more first pins coupled to an external data bus, and one or more second pins coupled to an external system interface. The one or more first pins output data chunks to the data bus during a period of memory operation; and the error code generator is configured to transmit a status code via the one or more second pins during the period of memory operation. The status code indicates at least one of an error was detected, an error was detected and corrected, or an error was detected and not corrected.

Abstract: Technologies are described herein for a representational state transfer (“REST” or “RESTful”) over Intelligent Platform Management Interface (“IPMI”) interface for firmware to BMC communication and applications thereof. These applications include, but are not limited to, remote firmware configuration, firmware updates, peripheral device firmware updates, provision of management information such as system inventory data, cloning and batch migration of firmware configuration settings, and firmware integrity monitoring. This functionality can be provided in a way that enables communication between BMCs and firmware to utilize modern manageability interfaces while maintaining backward compatibility with previous IPMI implementations.

Abstract: Technologies are described herein for a representational state transfer (“REST” or “RESTful”) over Intelligent Platform Management Interface (“IPMI”) interface for firmware to BMC communication and applications thereof. These applications include, but are not limited to, remote firmware configuration, firmware updates, peripheral device firmware updates, provision of management information such as system inventory data, cloning and batch migration of firmware configuration settings, and firmware integrity monitoring. This functionality can be provided in a way that enables communication between BMCs and firmware to utilize modern manageability interfaces while maintaining backward compatibility with previous IPMI implementations.

Abstract: Disclosed embodiments relate to a system having a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing security rules pertaining to the multiple security levels. The monitoring device restricts usage of the system if the processor activates the security levels in a sequence contrary to the security rules.

Abstract: A method for protecting an integrated circuit against unauthorized access to key registers, wherein functions and/or applications of the integrated circuit are unlocked and/or activated via data stored in key registers, such as during the start-up of the integrated circuit and/or during ongoing operation, where if such a key register is accessed, the data word used to perform the access is compared with specified key data, and if access via a data word deviating from the specified key data is detected, the access is marked as unauthorized, the access marked as unauthorized is then recorded and evaluated, and after the analysis, appropriate protective measures are triggered to prevent further unauthorized access such that a key register method for protecting sensitive data is expanded in a simple manner and hacker attacks are quickly detected and thwarted.

Abstract: A computer system includes a memory unit and a processing unit. The memory unit is configured to store a default setting value with an image file form. The processing unit is electrically connected to the memory unit, and configured to read the default setting value with the image file form from the memory unit. When the computer system is unable to be activated, the processing unit is configured to trigger the computer system to activate a safe mode of a basic input/output system, and to compare the default setting value with a system setting value of the computer system to generate a comparison result, so as to adjust and reactivate the computer system according to the comparison result.

Abstract: Technologies for memory encryption include a computing device to generate a keyed hash of a data line based on a statistical counter value and a memory address to which to write the data line and to store the keyed hash to a cache line. The statistical counter value has a reference probability of incrementing at each write operation. The cache line includes a plurality of keyed hashes and each of the keyed hashes corresponds with a different data line. The computing device further encrypts the data line based on the keyed hash, the memory address, and the statistical counter value.

Abstract: A method, system, and computer program product for protecting a computer system provides bootstrap operating system detection and recovery and provides the capability to detect malware, such as rootkits, before the operating system has been loaded and provides the capability to patch malfunctions that block the ability of the computer system to access the Internet. A method for protecting a computer system includes reading stored status information indicating whether network connectivity was available the last time an operating system of the computer system was operational, when the stored status information indicates that network connectivity was not available, obtaining a software patch, and executing and applying the software patch.

Abstract: A method, a system and a computer program product for handling speculative stores. The system determines when a speculative store buffer is not full. An indicator is generated when the speculative store buffer is not full, and the speculative stores are input into the speculative store buffer. When the speculative store buffer is full, a full buffer indicator is generated. Speculative stores prevented from entering the speculative store buffer are overflow stores. The overflow list is searched to determine whether one or more addresses of the overflow stores are present in the overflow list. When one or more addresses of the overflow stores are not present in the overflow list, the overflow stores are stored in the overflow list.

Abstract: A method of operating a disk drive is disclosed, the disk drive comprising a head actuated over a disk surface, and a first non-volatile semiconductor memory (NVSM). Calibrated parameters are stored in the first NVSM, wherein the calibrated parameters for accessing the disk surface. Prior to altering the disk drive, the calibrated parameters are uploaded from the disk drive to a host. After altering the disk drive, the calibrated parameters are downloaded from the host to the disk drive and the calibrated parameters are stored in a second NVSM.

Abstract: A hard disk control method, a hard disk control device and a computer are provided The method includes detecting the current mode in which the system runs; determining the access frequency of the hard disk in the system when detecting the system runs in an idle mode currently; intercepting the hard disk access commands to be sent to the hard disk when the access frequency of the hard disk is lower than a predetermined access frequency threshold to make the hard disk enter into a preset power saving mode, and saving the hard disk access commands into a preset memory.

Abstract: An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.

Abstract: A system and method for monitoring a group of storage devices for indications of a detected error. After receiving an indication that a first storage device in the group has experienced a detected error, a consecutive number of detected errors experienced by the first storage device is determined. If it is determined the consecutive number of detected errors experienced by the first storage device exceeds a threshold of more than one detected error before a second storage device in the group experiences one detected error, then in response, the consecutive number of detected errors experienced by the first storage device is reset. If the consecutive number of detected errors does exceed the threshold before the second storage device experiences the one detected error, then the first storage device is identified as a suspect storage device.