Abstract: Systems, apparatuses, and methods for efficiently processing arithmetic operations are disclosed. A computing system includes a processor capable of executing single precision mathematical instructions on data sizes of M bits and half precision mathematical instructions on data sizes of N bits, which is less than M bits. At least two source operands with M bits indicated by a received instruction are read from a register file. If the instruction is a packed math instruction, at least a first source operand with a size of N bits less than M bits is selected from either a high portion or a low portion of one of the at least two source operands read from the register file. The instruction includes fields storing bits, each bit indicating the high portion or the low portion of a given source operand associated with a register identifier specified elsewhere in the instruction.

Abstract: A reconfigurable hardware accelerator for computers combines a high-speed dataflow processor, having programmable functional units rapidly reconfigured in a network of programmable switches, with a stream processor that may autonomously access memory in predefined access patterns after receiving simple stream instructions. The result is a compact, high-speed processor that may exploit parallelism associated with many application-specific programs susceptible to acceleration.

Abstract: Systems, methods, devices and non-transitory, computer-readable storage mediums are disclosed for single sign-on (SSO) for mobile applications using direct brokering for identity authentication. In an embodiment, a method comprises: sending, by a mobile application operating on a mobile device, a request to an online service provider for access to a resource; receiving, by the mobile application, a redirect from the service provider to an identity service provider for authentication; and establishing, by a portion of binary code of the mobile application and using the redirect, a brokered authentication session with the identity service provider, the portion of binary code configured to operate as a broker for the mobile application for the authentication session, and to provide single sign-on (SSO) services to the mobile application and other mobile applications operating on the mobile device, the SSO services including services to access the resources and authorization to use the accessed resources.

Abstract: In accordance with an embodiment, described herein is a system and method for providing a reactive flattening map for use with a microservices or other computing environment. In a cloud computing environment, reactive programming can be used with publishers and subscribers, to abstract execution away from the thread of execution while providing rigorous coordination of various state transitions. The described approach provides support for processing streams of data involving one or more publishers and subscribers, by use of a multi-flat-map publisher component, to flatten or otherwise combine events emitted by multiple publishers concurrently, into a single stream of events for use by a downstream subscriber.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive an indication of at least one of a first interleaving mode for mapping codeblocks to a data channel or a second interleaving mode for reporting channel state information (CSI). The UE may map codeblocks to the data channel based at least in part on the first interleaving mode. The UE may report CSI based at least in part on the second interleaving mode. Numerous other aspects are provided.

Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication of critical branches. In one embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to disable use of the predicted future outcome for a conditional critical branch comprising the branch instruction.

Abstract: Technologies for protecting systems and data of an organization from malware include a data integrity server configured to receive a data file from an external source. The data integrity server analyzes the received data file with an anti-malware engine to determine whether the data file includes malware. The data integrity server discards the data file in response to a determination that the data file includes malware. Additionally, the data integrity server verifies the file type of the received data file. The data integrity server sanitizes the received data file in response to verification of the file type. Other embodiments are described and claimed.

Abstract: An exemplary method for using a virtual assistant may include, at an electronic device configured to transmit and receive data, receiving a user request for a service from a virtual assistant; determining at least one task to perform in response to the user request; estimating at least one performance characteristic for completion of the at least one task with the electronic device, based on at least one heuristic; based on the estimating, determining whether to execute the at least one task at the electronic device; in accordance with a determination to execute the at least one task at the electronic device, causing the execution of the at least one task at the electronic device; in accordance with a determination to execute the at least one task outside the electronic device: generating executable code for carrying out the least one task; and transmitting the executable code from the electronic device.

Abstract: The present invention relates to a method for encrypting a data pipeline in a computer system. A device receives a request to encrypt a data pipeline. The device can also receive encrypted stages of a data pipeline that are encrypted by an encryption key. The device can generate random locations in storage where the data pipeline stages will be stored. The random locations can be generated in response to the data pipeline stages being encrypted. The random storage locations can be stored in a mapping file. The mapping file can be selected to store the random locations based on the random storage locations being generated. The device can encrypt the mapping file based on the mapping file storing the random storage locations. The device can place the encrypted mapping file in memory.

Abstract: Systems, apparatuses, and methods for implementing as part of a processor pipeline a reprogrammable execution unit capable of executing specialized instructions are disclosed. A processor includes one or more reprogrammable execution units which can be programmed to execute different types of customized instructions. When the processor loads a program for execution, the processor loads a bitfile associated with the program. The processor programs a reprogrammable execution unit with the bitfile so that the reprogrammable execution unit is capable of executing specialized instructions associated with the program. During execution, a dispatch unit dispatches the specialized instructions to the reprogrammable execution unit for execution.

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

Abstract: An example system implementing a processing-in-memory pipeline includes: a memory array to store a plurality of look-up tables (LUTs) and data; a control block coupled to the memory array, the control block to control a computational pipeline by activating one or more LUTs of the plurality of LUTs; and a logic array coupled to the memory array and the control block, the logic array to perform, based on control inputs received from the control block, logic operations on the activated LUTs and the data.

Abstract: A first logic circuit included in a processor receives a first digital signal, where the first logic circuit includes a special purpose register, a comparator, and an adder, where the special purpose register stores a first resource balance for executing a smart contract, where the first digital signal includes a resource deduction quota corresponding to a code set in the smart contract. The first logic circuit reads the first resource balance from the special purpose register. The first logic circuit compares, using the comparator, the first resource balance with the resource deduction quota. In response to the first resource balance being greater than or equal to the resource deduction quota, the first logic circuit subtracts, using the adder, the resource deduction quota from the first resource balance to obtain a second resource balance. The first logic circuit stores the second resource balance in the special purpose register.

Abstract: Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

Abstract: A system and corresponding method enforce strong load ordering in a processor. The system comprises an ordering ring that stores entries corresponding to in-flight memory instructions associated with a program order, scanning logic, and recovery logic. The scanning logic scans the ordering ring in response to execution or completion of a given load instruction of the in-flight memory instructions and detects an ordering violation in an event at least one entry of the entries indicates that a younger load instruction has completed and is associated with an invalidated cache line. In response to the ordering violation, the recovery logic allows the given load instruction to complete, flushes the younger load instruction, and restarts execution of the processor after the given load instruction in the program order, causing data returned by the given and younger load instructions to be returned consistent with execution according to the program order to satisfy strong load ordering.

Abstract: Various examples are directed to systems and methods for managing resources in a multi-core computing system. A first thread executing at a first core of a multi-core processor unit may allocate a first element of a resource. The first thread may increment a first thread counter for a first metric describing the resource. The first thread may determine that the first thread counter is greater than a first thread counter threshold and update a first metric global value based at least in part on the first thread counter. The first thread may also reset the first thread counter.

Abstract: Techniques pertaining to the transmission of digital data via a conventional transmission medium (e.g., a coaxial cable for TV) specifically for analog composite video signals are disclosed. To retrofit in an existing system not designed for transmitting digital signals or data, the techniques are provided to convert the data into an analog signal that is transmitted over a coaxial cable, where the analog signal, when received, is decomposed to recover the data. According to one aspect of the present invention, videos in high quality (e.g. high definition or HD format) from HD cameras are used in the conventional surveillance system, where the transmission medium for the analogy videos is already installed.

Abstract: Techniques related to executing instructions by a processor comprising receiving a first instruction for execution, determining a first latency value based on an expected amount of time needed for the first instruction to be executed, storing the first latency value in a writeback queue, beginning execution of the first instruction on the instruction execution pipeline, adjusting the latency value based on an amount of time passed since beginning execution of the first instruction, outputting a first result of the first instruction based on the latency value, receiving a second instruction, determining that the second instruction is a variable latency instruction, storing a ready value indicating that a second result of the second instruction is not ready in the writeback queue, beginning execution of the second instruction on the instruction execution pipeline, updating the ready value to indicate that the second result is ready, and outputting the second result.

Abstract: A microprocessor using a counter in a scoreboard is introduced to handle data dependency. The microprocessor includes a register file having a plurality of registers mapped to entries of the scoreboard. Each entry of the scoreboard has a counter that tracks the data dependency of each of the registers. The counter decrements for every clock cycle until the counter resets itself when it counts down to 0. With the implementation of the counter in the scoreboard, the instruction pipeline may be managed according to the number of clock cycles of a previous issued instruction takes to access the register which is recorded in the counter of the scoreboard.

Abstract: Disclosed are systems and methods to provide a platform for standardizing application programming interfaces (APIs) for a plurality of different dealership management software (DMS) systems. A computer server includes one or more processors of an automotive commerce exchange platform. The one or more processors are configured to execute a plurality of different software interfaces with a plurality of different DMS systems and provide a standardized software interface. The standardized software interface is configured to enable communication between the one or more processors of the automotive commerce exchange platform and a plurality of different devices of entities involved with an automotive market. The standardized software interface is also configured to enable the plurality of different devices access to each of the plurality of different DMS systems independent of local software interfaces of the plurality of different devices with each of the different DMS systems.

Abstract: A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction. A processor system with a random instruction encoding and randomized execution, providing effective defense against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis.

Abstract: A system may include determination of a spatial power map associated with an integrated circuit based on an architecture of the circuit, generation of a spatial thermal map associated with the integrated circuit based on the spatial power map, and determination of a spatial leakage power map based on the spatial thermal map. In some aspects, a system includes determination of a temperature of an integrated circuit, comparison of the temperature with a thermal divergence temperature, determination that the temperature of the integrated circuit is primarily due to leakage power, and disabling of power to the integrated circuit.

Abstract: In the disclosure, the microprocessor resolves the conflicts in decode stage and schedules the instruction to be executed at a future time. The instruction is issued to an execution queue until the scheduled time in the future when it is dispatched to a functional unit for execution. The disclosure uses a counter for the functional unit to track when the resource is available in the future to accept the next instruction. The disclosure also tracks the future N cycles when the register file read and write ports are scheduled to read and write operand data.

Abstract: A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction qualifies for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.

Abstract: Method and system embodying the method for programmable scheduling encompassing: enqueueing at least one command into one of a plurality of queues having a plurality of entries; determining a category of the command at the head entry of each of the plurality of queues; processing each determined non-job category command by a non-job command arbitrator; and processing each determined job category command by a job arbitrator and assignor, is disclosed.

Abstract: Technologies for protecting systems and data of an organization from malware include a data integrity server configured to receive a data file from an external source. The data integrity server analyzes the received data file with an anti-malware engine to determine whether the data file includes malware. The data integrity server discards the data file in response to a determination that the data file includes malware. Additionally, the data integrity server verifies the file type of the received data file. The data integrity server sanitizes the received data file in response to verification of the file type. Other embodiments are described and claimed.

Abstract: Efficient register breakpoint checks rely on initiating an event based on an access to a register. Initiating the event can include, based on decoding a machine code instruction, identifying one or more registers that a machine code instruction could touch, and inserting an identification of the touched registers into a stream of executable operations for the machine code instruction. Then, while executing the executable operations, these registers can be compared with a register breakpoint collection. An event can be generated when one of these registers is in the register breakpoint collection. The event might trigger a conditional analysis, an execution break, and/or logging. In some implementations, the event might enable lifetime and/or taint analysis by removing a register from a monitoring collection if the executable operations write to the register, or by adding a destination of a read to the monitoring collection if the executable operations read from the register.

Abstract: Embodiments of the present disclosure relate to a method and apparatus for processing information. The method may include: determining an instruction category of an instruction based on an instruction operation code of the acquired instruction, where the instruction category includes a dedicated instruction including register selection information, base address information, and a length of to-be-read data; sending, in response to determining that the instruction is the dedicated instruction, the dedicated instruction to a preset operator for the operator to perform following operation steps: selecting a configuration register group from preset configuration register groups as a target configuration register group according to the register selection information; reading configuration information from the target configuration register group based on the base address information and the length of the to-be-read data; performing a preset operation for the configuration information.

Abstract: Improved data pipelines are provided. A request to activate a first pipeline based on a first pipeline definition is received. The first pipeline is generated based on the first pipeline definition, wherein generating the first pipeline includes generating a reusable processing module at a first position within the first pipeline, and generating a downstream processing module at a second position within the first pipeline, where the downstream processing module selectively sends output data to the reusable processing module, such that data processed by the first data pipeline will be processed by the identified reusable processing module at least twice. The first pipeline is activated.

Abstract: A method for controlling a system using natural language comprises a step of providing a plurality of string programme code components within the system. A string programme code component each comprises a definition string comprising an expression in natural language, and a programme code segment unambiguously assigned to the definition string which implements a functionality assigned to the expression in natural language. At least one of the string programme code components from the plurality of string programme code components further comprises a process for parameter input, wherein this string programme code component is configured to support a parameter input by means of which the functionality provided by the programme code segment of this string programme code component may be specified.

Abstract: A distributed computing system is configured to compute operational data for a video advertisement delivery system. Cloud-based resource are used to calculate operational parameters such as geographical data, unique advertisement delivery instances and segments of consumers that received the video advertisements.

Abstract: A method for controlling a compile a software application. The method includes at least one computer processor generating, from source code corresponding to a software application, a plurality of pre-optimization intermediate representations (IRs) of functions associated with the software application. The method further includes generating a plurality of post-optimization IRs of the functions associated with the software application by executing one or more optimization routines on the plurality of pre-optimization IRs of functions. The method further includes determining a set of IRs of functions, from the plurality of generated pre-optimization IRs of the functions associated with the software application and the generated plurality of post-optimization IRs of the functions associated with the software application. The method further includes converting a determined set of IRs of functions to an executable version of the software application.

Abstract: An apparatus includes a memory, a memory controller, arithmetic processors, and access circuits corresponding to the arithmetic processors. The memory controller controls a load instruction that reads, from the memory, data to be obtained by the arithmetic processors. The access circuit generates divided instructions by dividing a multicast load instruction, and selects, for each divided instruction, a first access circuit that issues, to the memory controller, a read request for causing the target access circuits to perform responses to the target access arithmetic processors. The first access circuit determines first identification information common to all the target access circuits, and issues, to the memory controller, a single read request to which the first identification information is added, and obtains, from the memory controller, responses to which the first identification information is added, and outputs first data based on the obtained responses to the target arithmetic processors.

Abstract: Systems and methods for predicting the next host source of a command directed to a storage device, and configuring the storage device with the host memory configuration parameters of that predicted host, are disclosed. A predictive model may be used to identify which of a plurality of different actual or virtual hosts will be sending a next command based on a pattern of prior host origins of commands. The storage device may include a plurality of different memory configuration parameters associated with each different host source and may update the current memory configuration based on the predicted next host origin prior to actual receipt of a next command.

Abstract: A method includes invoking a first instruction that, when executed by a first processor, causes the first processor to perform a first operation, and that, when executed by the first processor, causes a second processor to perform a second operation. The method further includes a second instruction that, when executed by the first processor, causes the first processor to perform the first operation while causing the second processor to perform a third operation or while leaving the second processor unaffected. A control system includes a first processor and a second processor, wherein the first processor is configured to execute a first instruction to perform a first operation, wherein the second processor is configured to perform a second operation when the first processor executes the first instruction.

Abstract: Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.

Abstract: Exploiting FPGAs for acceleration may be performed by transforming concurrent programs. One example mode of operation may provide one or more of creating synchronous hardware accelerators from concurrent asynchronous programs at software level, by obtaining input as software instructions describing concurrent behavior via a model of communicating sequential processes (CSP) of message exchange between concurrent processes performed via channels, mapping, on a computing device, each of the concurrent processes to synchronous dataflow primitives, comprising at least one of join, fork, merge, steer, variable, and arbiter, producing a clocked digital logic description for upload to one or more field programmable gate array (FPGA) devices, performing primitive remapping of the output design for throughput, clock rate and resource usage via retiming, and creating an annotated graph of the input software description for debugging of concurrent code for the field FPGA devices.

Abstract: A system, method, and computer program product are provided for metadata driven interface orchestration and mapping. In operation, a system defines a plurality of job items in a master enterprise catalogue by mapping all possible business requests to one or more pre-defined job items. The system defines job specifications in the master enterprise catalogue by mapping the plurality of job items to one or more pre-defined job specifications. Further, the system defines a job list in the master enterprise catalogue by building a sequence of outgoing requests based on possible use cases and the job specifications. The system defines an order context associated with one or more orders. Additionally, the system automatically generates a job plan including a plurality of activities utilizing the job list from the master enterprise catalogue and the order context. Moreover, the system automatically generates interfaces with a plurality of external systems based on the job plan including the plurality of activities.

Abstract: An architectural software model in which browser-executable code and non-browser executable code of an application are distributed. The browser-executable code (such as markup language and script) is executed by a browser on perhaps a client machine, whilst the non-browser executable code (such as C# code as an example) is executed on a server or by a service. Such code typically is included within a single desktop application with an interoperability component operating between. The browser-executable code is able to communicate with the non-browser executable code using a request-response protocol. In order to facilitate communication with the non-browser-executable code, the non-browser executable code is provided in an environment that includes a request translator and a response translator. The environment includes an interface which honors the request/response protocol followed by the browser-executable code.

Abstract: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, tracking a specific dependency on each of a threshold number of instructions most recently added to the issue queue prior to the instruction, tracking as a single group a dependency of the instruction on any instructions in the issue queue that are not in the threshold number of instructions, and tracking for each source register used by the instruction an indicator of whether its content is dependent on results from an instruction in the single group that has not finished execution. Based at least in part on detecting removal from the issue queue of an instruction in the single group that has issued and not finished execution, the method includes indicating that the instruction is ready for issuance or waiting for a notification that the removed instruction has finished execution.

Abstract: A database engine receives a database query from a client. The database engine parses the database query to build a query operator tree that includes a plurality of query operators. The database engine performs one or more optimization passes on the query operator tree, including a deduplication optimization pass, to form an optimized execution plan. The deduplication optimization pass includes: creating a list of query operators via a first traversal of the query operator tree, determining a first query operator that is equivalent to a second query operator, based on a hash map, via a second traversal of the query operator tree, and substituting, via a third traversal of the query operator tree, the second query operator with a tree node that links to the first query operator. The database engine executes the optimized execution plan to retrieve a result set from the database, and returns the result set.

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

Abstract: Methods, systems, and computer-readable media for event-driven scheduling using directed acyclic graphs are disclosed. A directed acyclic graph is generated that comprises a plurality of nodes and a plurality of edges. The nodes represent jobs, and the edges represent dependency relationships between individual jobs. Based (at least in part) on one or more events, a job scheduler determines that one of the nodes represents a runnable job. One or more of the dependency relationships for the runnable job are satisfied by the one or more events. An execution schedule is determined for the runnable job. Based (at least in part) on the execution schedule, execution of the runnable job is initiated using one or more computing resources.

Abstract: A data encoding method, a data decoding method, and a storage controller are provided. The encoding method includes: obtaining a verification data corresponding to a raw data according to a write command; adding the verification data to the raw data, and obtaining a scrambled data accordingly; and performing an encoding operation on the scrambled data to obtain a codeword data. The decoding method includes: performing a decoding operation on a codeword data to obtain a decoded codeword data, and obtaining a pre-scrambling data accordingly; identifying a verification data and a raw data in the pre-scrambling data; identifying one or more first system data corresponding to the raw data according to a read command; and determining whether the raw data is correct by comparing the one or more first system data and the verification data.

Abstract: A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.

Abstract: A processor comprising a processor pipeline comprising one or more execution units configured to execute branch instructions, a branch predictor associated with the processor pipeline and configured to predict a branch instruction outcome, a branch classification unit associated with the processor pipeline and the branch prediction unit. The branch classification unit is configured to, in response to detecting a branch instruction, classify the branch instruction as at least one of the following: a simple branch or a hard-to-predict (HTP) branch, wherein a threshold used for the classification is dynamically adjusted based on a workload of the processor.

Abstract: In one approach, an import mechanism allows new hardware intrinsics to be utilized by writing or updating a library of source code, rather than specifically modifying the virtual machine for each new intrinsic. Thus, once the architecture is in place to allow the import mechanism to function, the virtual machine itself (e.g. the code which implements the virtual machine) no longer needs to be modified in order to allow new intrinsics to be utilized by end user programmers. Since source code is typically more convenient to write than the language used to implement the virtual machine and the risk of miscoding the virtual machine is minimized when introducing new intrinsics, the import mechanism described herein increases the efficiency at which new hardware intrinsics can be introduced.

Abstract: A specialized memory access processor is placed between a main processor and accelerator hardware to handle memory access for the accelerator hardware. The architecture of the memory access processor is designed to allow lower energy memory accesses than can be obtained by the main processor in providing data to the hardware accelerator while providing the hardware accelerator with a sufficiently high bandwidth memory channel. In some embodiments, the main processor may enter a sleep state during accelerator calculations to substantially lower energy consumption.

Abstract: An integrated circuit includes a memory interface, coupled to a memory to store data corresponding to instructions, and an operations queue to buffer memory operations corresponding to the instructions. The integrated circuit may include acceleration hardware to execute a sub-program corresponding to the instructions. A set of input queues may include an address queue to receive, from the acceleration hardware, an address of the memory associated with a second memory operation of the memory operations, and a dependency queue to receive, from the acceleration hardware, a dependency token associated with the address. The dependency token indicates a dependency on data generated by a first memory operation of the memory operations. A scheduler circuit may schedule issuance of the second memory operation to the memory in response to the dependency queue receiving the dependency token and the address queue receiving the address.