Abstract: An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of time-multiplexed data signals between the clock domains during hardware-based emulation. The buffer is effectively used to latch each data signal communicated across the common signal path so that the clock domain that receives the signals can retrieve each such signal at appropriate points in the receiver clock domain's evaluation cycle. Independently-controlled write/read pointers are maintained in a buffer control circuit to independently address the buffer for the transmitter and receiver sides of an asynchronous communication path.

Abstract: An architecture of method for fetching microprocessor's instructions is provided to pre-fetch and pre-decode a next instruction. If the instruction pre-decoded is found a conditional branch instruction, an instruction reading-amount register is set for reading two instructions next to the current instruction in the program memory, or one is read instead if the next instruction is found an instruction other than the conditional branch one so as to waive reading of unnecessary program memory and thereby reduce power consumption.

Abstract: The present invention provides an instruction cache apparatus and method using the instruction read buffer. The apparatus comprises an instruction hit analysis unit, an instruction read buffer, a first cache instruction word memory, a second cache instruction word memory, a first multiplexer and a second multiplexer. The instruction hit analysis unit receives a programmable counter output signal, compares this with a plurality of tags, and after the analysis, outputs the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory. The second multiplexer reads the expected instruction word from one of either the first cache instruction word memory, the second cache instruction word memory or the first multiplexer according to the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory.

Abstract: A circuit is provided to provide instruction streams to a processing device: embodiments of the circuit are appropriate for use with RISC CPUs, whereas other embodiments are useable with other processing devices, such as small processing devices used in a field programmable array. The circuit receives an external instruction stream which provides a first set of instruction values, and has a memory which contains a second set of instruction values. Two or more outputs provide instruction streams to the processing device. The circuit has a control input in the form of a mask which causes a selection means to allocate bits from the first and second sets of instruction values to different instruction streams to the processing device.

Abstract: The branch prediction characteristics of a computer for executing a program are recognized, a binary program matched to the characteristics is constituted.

Abstract: In a computer processor, a low-order portion of a virtual address for a pipelined operation is compared directly with the corresponding low-order portions of addresses of operations below it in the pipeline to detect an address conflict, without first translating the address. Preferably, if a match is found, it is assumed that an address conflict exists, and the pipeline is stalled one or more cycles to maintain data integrity in the event of an actual address conflict. Preferably, the CPU has caches which are addressed using real addresses, and a translation lookaside buffer (TLB) for determining the high-order portion of a real address. The comparison of low-order address portions provides conflict detection before the TLB can translate a real address of an instruction.

Abstract: A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into ‘stripes’, or ‘cyclically sequential’ partitions, and the memory accelerator module includes a latch that is associated with each partition. When a particular partition is accessed, it is loaded into its corresponding latch, and the instructions in the next sequential partition are automatically pre-fetched into their corresponding latch. In this manner, the performance of a sequential-access process will have a known response, because the pre-fetched instructions from the next partition will be in the latch when the program sequences to these instructions. Previously accessed blocks remain in their corresponding latches until the pre-fetch process ‘cycles around’ and overwrites the contents of each sequentially-accessed latch.

Abstract: A method and apparatus for processing instructions involves an instruction fetch unit arranged to receive a plurality of instructions. The instruction fetch unit includes a bypass buffer arranged to receive at least a portion of a plurality of instructions, and an output multiplexer arranged to receive the at least a portion of the plurality of instructions where the output multiplexer is arranged to output an instruction selected from one of an output of the bypass buffer and the at least a portion of the plurality of instructions.

Abstract: A dedicated register is provided in an external access controller such that read ahead of operand data is performed. Using a store instruction, a program initiates read ahead by writing the read ahead address to the dedicated register. The read ahead controller stores read ahead data in the dedicated register. When the program issues a load instruction, the read ahead data is transmitted.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load requests out-of-order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out-of-order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: A microprocessor and method of processing instructions for addressing timing assymetries are disclosed. A sequence of instructions including a first instruction and a second instruction are received. Dependency logic determines if any dependencies between the first and second instructions. The dependency logic then selects between first and second issue queue partitions for storing the first and second instructions pending issue based upon the dependency determination, wherein the first issue queue partition issues instructions to a first execution unit and the second issue queue partition issues instructions to a second execution unit. The first and second issue queue partitions may be asymmetric with respect to a first register file in which instruction results are stored. The first and second instructions are then stored in the selected partitions.

Abstract: A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform addressing operations and assigns those instructions to specialized pipes in a pipeline structure. The invention can assign such instructions to both an execute pipe and a load/store pipe to avoid the occurrence of “bubbles” in the event execution of the instruction requires the calculation capability of the execute pipe. The invention can also examine a sequence of instructions to identify an instruction for performing a calculation where the result of the calculation is used by a succeeding load or store instruction. In this case, the invention controls the pipeline to assure the result of the calculation is available for the succeeding load or store instruction even if both instructions are being processed concurrently.

Abstract: An apparatus for executing an instruction in a computational pipeline includes a first instruction memory. The first instruction memory includes a first plurality of instruction fields, each of which is capable of holding an instruction therein. Each of a first plurality of value fields is uniquely associated with a corresponding instruction field from the first plurality of instruction fields. Each value field is capable of holding a data value therein that is likely to be required in executing an instruction held in the instruction field.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A data processing unit having superscalar structure able to execute a plurality of instructions in parallel includes a memory for storing the instructions having a plurality of n-bit input/output ports, an instruction fetch unit, a coupling unit for coupling said memory with the instruction fetch unit, and an instruction stream request control unit for addressing the mmory to provide an instruction stream at its output ports. The coupling unit includes a shifter having an input and an output and a control input, the input being coupled with the output ports of the memory, the output being coupled with the instruction fetch unit, and the control input being coupled with the instruction stream request control unit. The instruction fetch unit has a register for storing said instruction stream and a shifter to shift the content of the register.

Abstract: A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. The instruction loading circuit loads the L instructions from the second instruction storing circuit into the positions previously occupied by the L instructions dispatched from the first instruction storing circuit.

Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

Abstract: A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed.

Abstract: A method, apparatus and article of manufacture are provided for sequencing graphics processing in a transform or lighting operation. A plurality of mode bits are first received which are indicative of the status of a plurality of modes of process operations. A plurality of addresses are then identified in memory based on the mode bits. Such addresses are then accessed in the memory for retrieving code segments which each are adapted to carry out the process operations in accordance with the status of the modes. The code segments are subsequently executed within a transform or lighting module for processing vertex data.

Abstract: A method of prefetching addresses includes the step of accessing a stored instruction using a current address. During the access using the current address, a target address is accessed in a branch target address cache. A stored instruction associated with the target address accessed from the branch target address cache is prefetched and the branch target address is indexed with selected bits from the address accessed from the branch target address cache.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides information for the instruction beginning at the fetch address, as well as alignment information for up to one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Since the line predictor provides alignment information from one entry per fetch, the line predictor may provide a flow control mechanism for the initial portion of the pipeline within a microprocessor. Each entry may store combinations of instructions which the hardware within the pipeline may handle without creating stalls resulting from the combinations.

Abstract: A microprocessor, data processing system, and an associated method of executing microprocessor instructions and generating instruction fetch addresses are disclosed. The microprocessor includes an instruction fetch unit comprising and instruction fetch address register (IFAR) and an instruction processing unit (IPU). The IFAR is configured to provide an address to an instruction cache. The IPU is suitable for receiving a set of instructions from the instruction cache and for generating an instruction fetch address upon determining from the set of instructions that the program execution flow requires redirection. The IPU is adapted to determine that the program flow requires redirection if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle.

Abstract: A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.

Abstract: A method, apparatus, and article of manufacture for a computer implemented technique for prefetching pages. Pages are prefetched from a database stored on a data storage device connected to a computer. Pages to be retrieved are identified. Identifiers for the identified pages are stored in multiple prefetch page lists. Concurrently, the retrieved pages are processed and prefetch commands are issued to alternating multiple prefetch page lists.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

Abstract: A parallel computation processor being capable of high-speed loop operation. When instruction decoders decode the VLOOP instruction, which triggers loop operation, an instruction buffer starts storing normal instructions. The instruction buffer dispatches a VLIW instruction composed of n pieces of normal instructions to execution units each time n pieces of instructions are stored therein. The execution units concurrently execute the instructions. After all instructions comprised in a loop have been stored in the buffer and once dispatched as VLIW instructions to be executed, the loop is executed repeatedly.

Abstract: A processor comprises an instruction cache that stores a cache line of instructions and an execution engine for executing the instructions, along with a buffer to store a plurality of entries. A first logic circuit divides the cache line into instruction bundles, each of which gets written into an entry of the buffer. A second logic circuit reads out a number of consecutive instruction bundles from the buffer for dispersal to the execution engine to optimize speculative fetching and maximizing instruction supply to the execution resources of the processor.

Abstract: In an instruction control apparatus that enables a plurality of instructions of different instruction lengths to be selected simultaneously from an instruction buffer, the amount of circuitry is reduced while achieving high speed processing. The instruction control apparatus includes a selection circuit and a pointer that points to the beginning of the next instruction word, within the instruction sequence fetched in a holding means, to be loaded into an execution stage. The selection circuit first selects a portion of the instruction sequence, starting from the beginning pointed to by the pointer and extending until reaching a maximum length of instructions that can be loaded into the execution stage, then simultaneously examines the lengths of instructions contained in the selected portion on the basis of a minimum instruction length unit, and selects the plurality of instructions to be loaded into the execution stage, based on the combination of the instruction lengths.

Abstract: A circuit is provided to provide instruction streams to a processing device: embodiments of the circuit are appropriate for use with RISC CPUs, whereas other embodiments are useable with other processing devices, such as small processing devices used in a field programmable array. The circuit receives an external instruction stream which provides a first set of instruction values, and has a memory which contains a second set of instruction values. Two or more outputs provide instruction streams to the processing device. The circuit has a control input in the form of a mask which causes a selection means to allocate bits from the first and second sets of instruction values to different instruction streams to the processing device.

Abstract: A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster).

Abstract: A system includes multiple program execution entities (e.g., tasks, processes, threads, and the like) and a cache memory having multiple sections. An identifier is assigned to each execution entity. An instruction of one of the execution entities is retrieved and an associated identifier is decoded. Information associated with the instruction is stored in one of the cache sections based on the identifier.

Abstract: The processor is configured to predecode instruction bytes prior to their storage within an instruction cache. During the predecoding, relative branch instructions are detected. The displacement included within the relative branch instruction is added to the address corresponding to the relative branch instruction, thereby generating the target address. The processor replaces the displacement field of the relative branch instruction with an encoding of the target address, and stores the modified relative branch instruction in the instruction cache. The branch prediction mechanism may select the target address from the displacement field of the relative branch instruction instead of performing an addition to generate the target address. In one embodiment, relative branch instructions having eight bit and 32-bit displacement fields are included in the instruction set executed by the processor.

Abstract: A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single vector instruction nor to repeat or loop instructions. Rather, the technique, termed register file indexing (RFI) allows full programmer flexibilty in control of the block data operational facility and provides the capability to mix non-RFI instructions with RFI instructions. The block-data operation facility is embedded in the iVLIW ManArray architecture allowing its generalized use across the instruction set architecture without specialized vector instructions or being limited in use only with repeat or loop instructions.

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address-collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: The inventive mechanism uses a cache table to map branch targets. When a fetch instruction is initiated, the inventive mechanism searches the IP-to-TM cache to determine whether the branch target instruction has been optimized and placed into the trace memory. If there is a match with the P-to-TM cache, then the code in the trace is executed. This cache is examined in parallel with Instruction Translation Lookup Buffer (ITLB). If not a match is found in the IP-to-TM cache, the original binary in the physical address provided by the ITLB will be executed.

Abstract: A system for time-ordered issuance of instruction fetch requests (IFR). More specifically, the system enables just-in-time delivery of instructions requested by an IFR. The system consists of a processor, an L1 instruction cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates an architected time dependency field of an IFR to create a Time of Dependency (ToD) field. The ToD field holds a time dependency value which is utilized to order the IFR in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The IFR is issued from RTOQ to the L1 instruction cache so that the requested instruction is fetched from the L1 instruction cache at the time specified by the ToD value. In an alternate embodiment the ToD is converted to a CoD and the instruction is fetched from a lower level cache at the CoD value.

Abstract: A system for instructing a data processor, the system including an instruction root having an operation selection field for selecting an operation to be performed by said data processor and an instruction prefix. The instruction prefix has a field selected from the group of a conditional execution field for selecting a condition under which a data processor will perform said selected operation, an operand length modification field for modifying the selected operation so as to be performed on an operand having a different length, an instruction group field for selecting a length of an instruction group that includes the instruction root, and a prefix length selection field for selecting a length of said instruction prefix. A data processor system responsive to this instruction system is also disclosed. An instruction system for statically grouping instructions without using an instruction prefix is also disclosed.

Abstract: There is disclosed a data processor containing an instruction issue unit that efficiently transfers instruction bundles from a cache to an instruction pipeline. The data processor comprises 1) an instruction pipeline comprising N processing stages; and 2) an instruction issue unit for fetching into the instruction pipeline instructions fetched from the instruction cache, each of the fetched instructions comprising from one to S syllables.

Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

Abstract: A system and method for increasing effective bus bandwidth in communicating with a graphics device. Graphics commands and associated parameters are written into a contiguous region of system memory and transmitted in a weakly ordered fashion over a bus to a graphics device. The graphics device reorders the incoming data into the same order as which the data was written into the contiguous region of system memory, thereby allowing the use of order dependent encoded commands with the weakly ordered bus interface.

Abstract: A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher. Individual instructions within the fetched group for the branch pipeline are assigned a concatenated version (group tag concatenated with instruction lane) of the transfer tag which is used to match on requests to flush any newer instructions. All potential instruction or Internal Operation latches in the decode pipeline must perform a match and if a match is encountered, all valid bits associated with newer instructions or internal operations upstream from the match are cleared. The transfer tag representing the next instruction to be processed in the branch pipeline is passed to the Instruction Dispatch Unit. The Instruction Dispatch Unit queries the branch pipeline to compare its transfer tag with transfer tags of instructions in the branch pipeline.

Abstract: A system and method for recipe integration provides a single timeline for a cook preparing a meal of several different dishes. A food recipe integration computer combines steps from the recipes of the individual dishes and de-conflicts steps as necessary such that the cook is not required to perform multiple actions at once. The single timeline is a list of steps and corresponding times for preparing the dishes to be ready at the selected times. The time allocated to a given step may be greater for a beginning cook than for a more skilled cook. Optionally, one or more steps in a list are more detailed for less skilled cooks and less detailed for cooks having higher skills.

Abstract: A dispersal unit in combination with a chain affinity unit and an intra-cycle dependency analyzer routes instructions in a microprocessor in order to improve microprocessor performance. The dispersal unit routes instructions to a particular cluster in the microprocessor in response to information stored in the chain affinity unit. The intra-cycle dependency analyzer identifies dependencies in groups of instructions to the dispersal unit, and the dispersal unit routes instructions in the group based on those dependencies.

Abstract: A compiling method, for compiling a source program into an object program for a CPU having multiple functional units that allow for concurrent operations and supporting predicated execution, for generating the object program that can be executed on the CPU at high speed by analyzing the source program and generating intermediate codes, making an analysis of the intermediate codes, generating, based on the analysis, an execution mode set instruction to set an execution mode managed within the CPU, allocating, based on the analysis, instructions such that whether they are to be executed or not to be executed depends on the execution mode set by the execution mode set instruction from the intermediate codes, wherein one or more instructions in which values in their respective specific fields are identical make an block together for every value in the specific field, finding, for each block, an ending part of the block in which its last instruction is allocated, and generating, when the ending part of a certain b

Abstract: An apparatus and a method are distinguished in that an instruction queue is provided which is configured such that when instruction data are written into the instruction queue and/or when instruction data are read out of the instruction queue, a plurality of defined points within the instruction queue are made to start up selectively. As a result, the incidence of pauses in program execution can be reduced to a minimum.

Abstract: Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.

Abstract: A very long instruction word (VLIW) processor exploits program level parallelism as well as instruction level parallelism. Unlike prior VLIW machines which obtain speed advantages using instruction level parallelism, the present processor exploits the parallelism inherent in a VLIW processor by providing new instruction level mechanisms to separate processor execution into parallel threads. This separation allows greater hardware use because more than one program can exploit instruction level parallelism on the system at the same time. A first program and a second program execute concurrently such that the second program executes using resources and cycles that would have been wasted by the first program. This construct is especially useful where the second program is an interrupt service routine because the interrupt service routine can be threaded through the machine with high or low priority while the functional units still process the first program stream.