Abstract: A decode unit (20) decodes instructions in a processor. These, instructions include instructions of a first length in a first instruction mode and instructions of a second, shorter length in a second instruction mode. The decode unit has decoding circuitry (50-60) which decode the instructions. A register holds the instruction mode and generates an instruction mode signal. Switching circuitry (MUX6,MUX7) is responsive to the instruction mode signal to output decoded instructions from the decode unit depending on the instruction mode. A detector (70) is provided for detecting a length change instruction of the second, shorter length while in the second instruction mode which indicates that the subsequent instruction is of the first length. The detector also temporarily alters the state of the instruction mode signal to allow the first length instructions to be decoded without changing the instruction mode held in the register.

Abstract: Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles.

Abstract: A processor is adapted to support a complex instruction set without making major modifications to the existing hardware but by adding just a few controls and thereby emulating instructions in hardware. The processor is implemented by adding, to the existing processor, a second instruction decoder for decoding an expanded instruction code not capable of issuing an instruction per cycle, and for issuing one instruction per cycle by translating the expanded instruction code into a sequence of basic instructions; a counter for counting the number of instructions to be issued by the second instruction decoder, and for outputting a signal indicating that the expanded instruction code is being executed; and an instruction selection unit for selecting the instruction issued from the first instruction decoder when executing a basic instruction code and the instruction issued from the second instruction decoder when executing the expanded instruction code.

Abstract: A disc storage apparatus includes at least one disc having at least one recording surface, at least one head associated with the at least one recording surface for recording data on the at least one recording surface, a decoder circuit which receives coded data from the at least one head, decodes the coded data to parallel data, and outputs the parallel data, and a disc control unit which receives the parallel data from the decoder circuit and outputs the parallel data outside the disc storage apparatus. The apparatus may further include a host interface control unit coupled to a host computer and the disc control unit, wherein the disc control unit outputs the parallel data to the host computer via the host interface control unit, and a buffer memory which stores the parallel data to be outputted to the host computer.

Abstract: A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first instruction 602 in a first position and the second instruction 604 in a second position. A first decoder 612 provides decoding of the first instruction and generates first control signals. The first control signals include first resource control signals, first address generation control signals, and a first validity signal indicative of the validity of the first instruction in the first position. A second decoder 614 provides decoding of the second instruction and generates second control signals. The second control signals include second resource control signals, second address generation control signals, and a second validity signal indicative of the validity of the second instruction in the second position.

Abstract: A parallel computation processor being capable of high-speed loop operation. When instruction decoders decode the VLOOP instruction, which triggers loop operation, an instruction buffer starts storing normal instructions. The instruction buffer dispatches a VLIW instruction composed of n pieces of normal instructions to execution units each time n pieces of instructions are stored therein. The execution units concurrently execute the instructions. After all instructions comprised in a loop have been stored in the buffer and once dispatched as VLIW instructions to be executed, the loop is executed repeatedly.

Abstract: In a computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU execution pipeline including a CPU decoder pipestage and the FPU execution pipeline including an FPU decoder pipestage, the method including the steps of, (a) sending a first instruction to the CPU decoder pipestage, (b) sending the first instruction to the FPU decoder pipestage, (c) generating a signal indicating that the first instruction has been accepted by the CPU decoder pipestage, (d) generating a signal indicating that the first instruction has been accepted by the FPU decoder pipestage, (e) sending a second instruction to the CPU decoder pipestage in response to step (d), and (f) sending a second instruction to the FPU decoder pipestage in response to step (c). A corresponding apparatus is also provided.

Abstract: An apparatus and method for determining register dependency in multiple architecture system. The system includes a microprocessor emulating an emulated instruction set using a native instruction set where the microprocessor contains at least one register. An execution engine provides the native instructions where each native instruction contains at least one register identifier. Flags are provided to each native instruction where each flag indicates whether a register identifier is valid. A bundler checks for dependency among the valid register identifiers in the native instructions.

Abstract: A clipping and quantization technique is described for producing clipped numbers in a range of 0 to N−1 (from unclipped numbers in a range of −0.5N to (1.5N−1)), where N is 2m and m is the bit length of the desired clipped and quantized number. The most significant bit of the unclipped data value indicates whether an overflow of the permitted range has occurred and that clipping is required. The next most significant bit (m−1th) indicates which saturated value should be adopted. These properties of the unclipped data value may be exploited to generate the desired clipped and quantized numbers using logical left shifting and conditionally executed saturating instructions executing upon a general purpose processor 24. The shifting operations performed to achieve saturation operation may simultaneously yield quantization.

Abstract: A VLIW processor includes a plurality of containers holding a plurality of sub-instructions in a VLIW instruction, an exchanging portion exchanging the plurality of sub-instructions held in the plurality of containers and inputting the instructions to the plurality of containers, a plurality of decoders decoding the sub-instructions held in the plurality of containers, and a plurality of processing units executing the sub-instructions decoded by the plurality of decoders. Since the exchanging portion exchanges a plurality of sub-instructions held in the plurality of containers and inputs the instructions to the plurality of containers, a compressed code can be executed in such an execution sequence that is taken prior to compression.

Abstract: Methods and apparatus for software threads to access both shared and unshared data in a single software unit. Prior to a thread executing a set of computer language instructions in a collection of software units, it creates a copy of the respective location data segment of the collection of software units. Thereafter, prior to the thread accessing a software unit in the collection of software units that has an associated set of shared data, the thread sets a pointer in its location data segment copy to the equivalent value in the location data segment of the collection of software units. The thread will thereafter access the set of data associated with the software unit when it executes the respective software unit. Also, prior to the thread accessing a software unit in the collection of software units that has an associated set of unshared data, the thread creates a copy of the set of unshared data.

Abstract: The present invention relates to a data processor, and particularly in a data processor performing condition execution on the basis of flag information, aims at obtaining a data processor having excellent code efficiency, which can reduce branch penalty. In order to attain the aforementioned object, it is so structured that, when a first instruction decoded in a first decoder is an execution condition specifying instruction specifying the execution condition for a pair of second instructions executed in parallel, a first execution condition determination unit performs determination of the execution condition for the second instructions defined by the execution condition specifying instruction on the basis of the flag information and controls assertion/non-assertion of an execution inhibit signal on the basis of whether the execution condition defined by the execution condition specifying instruction is satisfied or not.

Abstract: When a decision circuit (217) incorporated in a control circuit (21) in an instruction decode unit (2) in a microprocessor (1) decides that an integer operation unit (4) can not execute a following sub instruction, the decision circuit (217) controls each of selectors (211, 214, and 215) and an exchange circuit (216) so that a memory access unit (3) that has already executed a preceding sub instruction can execute the following sub instruction.

Abstract: A sequence control circuit provided in such as a test pattern generator of a memory test apparatus, and made capable of designating a plurality of branches according to a plurality of branch conditions in describing a test pattern program. This sequence control circuit comprises a plurality of branch address registers for storing different branch addresses, respectively, and a logic operation circuit receiving a plurality of flags for detecting combinations of flag values. A program counter controller selects a certain branch address according to a combination of flag values detected in the logic operation circuit and arranges to load the branch address stored in the selected branch address register to a program counter.

Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Abstract: A system for instructing a data processor, the system including an instruction root having an operation selection field for selecting an operation to be performed by said data processor and an instruction prefix. The instruction prefix has a field selected from the group of a conditional execution field for selecting a condition under which a data processor will perform said selected operation, an operand length modification field for modifying the selected operation so as to be performed on an operand having a different length, an instruction group field for selecting a length of an instruction group that includes the instruction root, and a prefix length selection field for selecting a length of said instruction prefix. A data processor system responsive to this instruction system is also disclosed. An instruction system for statically grouping instructions without using an instruction prefix is also disclosed.

Abstract: A RAM (12) used by the CPU comprises a work buffer (14) and a work register (151) for pipelined processing. The work buffer (14) consists of the first to fourth work buffers (141 to 144) each of which stores information on predetermined data, e.g., a current processing on the data. When the CPU accesses the first to fourth work buffers (141 to 144), an address decoder performs an address conversion on the basis of a value (R151) of the work register (151). For example, when the value (R151) of the work register (151) is “1”, addresses (P1, P2, P3 and P4) in an address space are converted (mapped) to addresses (AD141, AD142, AD143 and AD144) of work buffers (141, 142, 143 and 144). With this constitution, in performing a plurality of data processings in parallel, the CPU can improve its operation efficiency while controlling a currently performed processing on each data.

Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Abstract: In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.

Abstract: In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of operation executions are-flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.

Abstract: A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.

Abstract: Within a superscalar processor, multiple groups of instructions are dispatched simultaneously to a plurality of execution units. A renaming mechanism is utilized to permit out-of-order execution of these instructions within the multiple groups. The renaming mechanism includes a rename table allocated for each dispatched group. A delay register is implemented between a portion of the dispatch queue dispatching a second one of the groups of instructions and a second one of the rename tables.

Abstract: A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1th unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k−1)th unit field in the same parallel execution code.

Abstract: Decoding of addresses in a register file is simplified by reducing the number of bits used for addressing by one. Bits are read from even/odd cell combinations simultaneously, and a reserved address line is driven high. The reserved address line is coupled to each driver corresponding to a storage cell. Individual even cells may also be read. Writing to even/odd cell combinations may be performed in a similar manner. However, when writing, an even write enable line and an odd write enable line are provided to indicate whether an even cell, an odd cell, or an even/odd cell combination should be written to simultaneously. By simplifying the decoding stage, performance of reading and writing tasks may be performed much faster and use less resources.

Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.

Abstract: A method of use of real time machine control software integrating both event based mode and task based components. In particular, a collection of constructs have been created that allow machine control applications to be expressed in event based terms and the event based constructs to be seamlessly integrated with task based constructs. The method includes the use of response time specifications, in particular in conjunction with ReactiveTask and Task constructs. The method also includes the use of Register, ReferenceClock, and SchedulerLock constructs.

Abstract: A method and system for determining if a dispatch slot is required in a processing system is disclosed. The method and system comprises a plurality of predecode bits to provide routing information and utilizing the predecode bits to allow instructions to be directed to specific decode slots and to obey dispatch constraints without examining the instructions. The purpose of this precode encoding system scheme is to provide the most information possible about the grouping of the instructions without increasing the complexity of the logic which uses this information for decode and group formation. In a preferred embodiment, pre-decode bits for each instruction that may be issued in parallel are analyzed and the multiplexer controls are retained for each of the possible starting positions within the stream of instructions.

Abstract: Rapid thread processing is performed by associating thread contexts stored in a remote memory with interrupts for controlling the operation of a hardware-accelerated processor. This both minimizes the use of registers in the processor and provides a flexible, remotely accessible storage medium for the thread contexts.

Abstract: A program controller for use in a processor operating on pipe-line principles includes: a first memory section for outputting an instruction contained in a first program including a plurality of instructions; a second memory section for outputting an instruction contained in a second program including a plurality of instructions, the first program being different from the second program; a selection section for selecting either the instruction which is output from the first memory section or the instruction which is output from the second memory section; a determination section for determining whether or not the instruction selected by the selection section is an instruction for controlling the execution order of instructions; and a control section for, if the instruction selected by the selection section is determined as an instruction for controlling the execution order of instructions, controlling the selection section so as to switch from the selected instruction to the unselected instruction of either th

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Abstract: An arbiter system for the instruction issue logic of a CPU has at least two encoder circuits that select instructions in an instruction queue for issue to first and second execution units, respectively, based upon the positions of the instructions within the queue and requests by the instructions for the first and/or second execution units. As a result, since the instruction can request different execution units, this system is compatible with architectures where the execution units may have different capabilities to execute different instructions, i.e., each integer execution unit may not be able to execute all of the instructions in the CPU's integer instruction set. According to the present invention, one of the encoder circuits is subordinate to the other circuit. The subordinate encoder circuit selects instructions from the instruction queue based not only on the positions of the instructions and their requests, but the instruction selection of the dominant encoder circuit.

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Abstract: The present invention utilizes a cache which stores various decoded instructions, or parcels, so that these parcels can be made available to the execution units without having to decode a microprocessor instruction, such as a CISC instruction, or the like. This increases performance by bypassing the fetch/decode pipeline stages on the front end of the microprocessor by using a parcel cache to store previously decoded instructions. The parcel cache is coupled to the microprocessor fetch/decode unit and can be searched during an instruction fetch cycle. This search of the parcel cache will occur in parallel with the search of the microprocessor instruction cache. When parcel(s) corresponding to the complex instruction being fetched are found in the parcel cache a hit occurs and the corresponding micro-ops are then sent to the execution units, bypassing the previous pipeline stages.

Abstract: A packed data structure processor (25) is disclosed. The packed data structure processor (25) includes a register file (24) of multiple registers (REG0 through REG31), each of which is connected to an input of each of a plurality of operand multiplexers (26). Each operand multiplexer (26) is associated with a shift/mask circuit (28), which permits the selection of a particular portion (e.g., BYIE, WORD, DWORD) of the contents of a selected register file, for use as an operand. An arithmetic logic unit (ALU) (30) performs data processing operations upon the operands, and presents results on writeback bus (WBBUS), to external memory (18) over a memory interface (37), or to a register file (42) associated with other circuitry (44) over a coprocessor interface (41). A destination selector (40) is capable of writing to only a selected portion of a selected register, thus permitting a packed data structure to be present within the register file (24).

Abstract: A microprocessor configured to allow instructions to be decoded out of order is disclosed. The microprocessor is configured to assign fetch tags to groups of instruction bytes as they are fetched from an instruction cache. The instructions are then aligned and decoded. Multiple decode units may be used in parallel to perform the aligning and decoding. As the groups of instruction bytes are aligned and decoded, a separate instruction counter is maintained for each group. The instruction counters identify the number of instructions decoded within each group. Instruction tags are formed by appending the instruction counter values to the fetch tags. The instruction tags serve to identify the relative position of each decoded instruction in program order. After decoding, the instructions are stored in a reordering storage unit. The reordering storage unit allows the instructions to be reordered for dependency checking. A method for decoding instructions out of order is also disclosed.

Abstract: A processor for executing operations based on instructions includes an operation constant register 361, a branching constant register 362, a decoding unit 20 for decoding an instruction stored in an instruction register 10, a constant register control unit 32, and an execution unit 30. When the decoding unit 20 finds that the instruction includes a constant to be stored in the branching constant register 362, the constant register control unit 32 shifts a present value in the branching constant register 362 and inserts the constant to be stored, thereby storing a new constant in the branching constant register 362. When the decoding unit 20 finds that a constant is to be stored in the operation constant register 361, the constant register control unit 32 shifts the present value in the operation constant register 361 and inserts the constant to be stored, thereby storing a new constant in the operation constant register 361.

Abstract: Dynamically typed registers in a processor are provided by associating a type specifier with a register specifier for each register in the processor, storing the register specifiers and associated type specifiers in a register type table. The type specifier associated with an operand register of an instruction is employed to dispatch the instruction to an appropriate execution unit within the processor. The results of the instruction are stored in a register having an associated type specifier matching the execution unit type. Register specifiers are dynamically allocated to particular execution units within the processor by altering the type specifier associated with the register specifiers. Register values may be either discarded or converted when the register specifier type is altered. A general instruction allows conversion of the value from one type to another without storing the converted value in memory.

Abstract: A microprocessor capable of out-of-order instruction decoding and in-order dependency checking is disclosed. The microprocessor may include an instruction cache, two decode units, a reorder queue, and dependency checking logic. The instruction cache is configured to output cache line portions to the decode units. The decode units operate independently and in parallel. One of the decode units may be a split decoder that receives all instruction bytes from instructions that extend across cache line portion boundaries. The split decode unit may be configured to reassemble the instruction bytes into instructions. These instructions are then decoded by the split decode unit. A reorder queue may be used to store the decoded instructions according to their relative cache line positions. The decoded instructions are read out of the reorder queue in program order, thereby enabling the dependency checking logic to perform dependency checking in program order.

Abstract: A superscalar complex instruction set computer (“CISC”) processor having a reduced instruction set computer (“RISC”) superscalar core includes an instruction cache which identifies and marks raw x86 instruction start and end points and encodes “pre-decode” information, a byte queue which is a queue of aligned instruction and pre-decode information of the “predicted executed” state, and an instruction decoder which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue and determines the number of possible x86 instruction dispatch for shifting the byte que. The instruction decoder includes in each dispatch position a logic conversion path, a memory conversion path, and a common conversion path for converting CISC instructions to ROPs.

Abstract: A compiler system (190) stores a data structure (101, e.g., a program) to a memory (110) of an execution system (100). The data structure (101) comprises, for example, processor instructions coded by compressed portions of variable lengths. The compiler system (190) partitions some or all memory lines (115) of the memory (110) into P≧2 partitions, e.g., &agr; and &bgr;, and writes code portions A to a first partition (e.g., &agr;) and second code portions B to a second partition (e.g., &bgr;) of an adjacent memory line (115). The compiler system (190) also stores addresses for some or all of the code portions in, for example, the memory (110). The addresses (260) have pointers (a and b) which indicate start positions (jA and jB) for portions A and B. Optionally, pointer magnitudes distinguish portion-to-pointer relations without the need for further identification bits.

Abstract: A data processor comprises an instruction decoding unit having two decoders decoding respective instructions of an instruction group consisting of a plurality of instructions including a first instruction and a second instruction succeeding the first instruction, and a judging unit judging whether or not a combination of the first instruction and the second instruction can be executed in parallel and a bus for transferring two data in parallel between an operand access unit and an integer operation unit. The data processor uses a superscalar technique. Two instructions having an operand interference can be executed in parallel at high speed and two instructions accessing a memory can be executed in parallel without considerable hardware.

Abstract: A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifics which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed.

Abstract: A multithreaded processor includes a level one instruction cache shared by all threads. The I-cache is accessed with an instruction unit generated effective address, the I-cache directory containing real page numbers of the corresponding cache lines. A separate line fill sequencer exists for each thread. Preferably, the I-cache is N-way set associative, where N is the number of threads, and includes an effective-to-real address table (ERAT), containing pairs of effective and real page numbers. ERAT entries are accessed by hashing the effective address. The ERAT entry is then compared with the effective address of the desired instruction to verify an ERAT hit. The corresponding real page number is compared with a real page number in the directory array to verify a cache hit. Preferably, the line fill sequencer operates in response to a cache miss, where there is an ERAT hit.

Abstract: A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. When the cache line is scanned for dispatch, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the location of the first scanned instruction and the functional bits of the predecode data to multiplex instruction specific bytes of the first scanned instruction to the MROM unit. If the first scanned instruction is not the first microcode instruction, then in a subsequent clock cycle, the first microcode instruction is dispatched the MROM unit and the mispredicted instruction is canceled.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A data processor performs various types of EIT (exception, interrupt, trap) processing in connection with the execution of the preceding and following instructions in parallel. In one embodiment, an exception is detected resulting from processing the previous instruction in the pair being executed in parallel before completion of instruction processing where the exception requires re-execution. When the exception is detected a control means prevents the execution means from executing both preceding and following instructions. An additional feature is a control unit that controls when an interrupt is accepted during parallel execution. In another embodiment, a first decoder outputs suppressing information when the preceding instruction is a predetermined instruction having a possibility of causing a trap. A validity judgment circuit prevents the second decoded result from being issued when suppressing information is generated.

Abstract: An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated arithmetic operations proceeds much more rapidly. The digital signal processor is also augmented with additional instruction formats which are particularly useful for digital signal processing. A first additional instruction format allows the digital signal processor to incorporate a small constant immediately into an instruction, such as to add a small constant value to a register value, or to multiply a register by a small constant value; this allows the digital signal processor to conduct the arithmetic operation with only one memory lookup instead of two.