Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

Abstract: In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the microprocessor, so that it becomes possible for the microprocessor to protect processes that actually execute the program, without an intervention of the operating system, and it becomes possible to conceal secret information of the program not only from the other user program but also from the operating system.

Abstract: In a method for controlling mechanisms or technical systems, the mechanisms or technical systems to be controlled are stored in a controller with their states, and with associated signal formers of sensors and actuators, whereby starting from a defined reference state at the onset of the activation of the controller, the actual states signaled by the technical system via the sensors are continuously compared with the specified state, the specified state being stored in the controller, and, based on this comparison, every deviation from the specified state is identified in the technical system, and, when initiated, a new instruction that changes the state of the mechanisms or of the technical system updates the specified state for the comparison and monitors the time till the acknowledgment of the new state, and sensor signals and comparable information exclusively serve the state identification of elementary functions and state changes exclusively ensue upon the initiation of elementary instructions.

Abstract: A data processor includes at least one instruction pipeline for executing an instruction stream having branch instructions. The choices of a branch instruction, the next inline instruction or a target instruction, are made available for selection by a control bypass signal that is generated during decode of the branch instruction.

Abstract: Methods of performing dyadic digital signal processing (DSP) instructions. In one embodiment of the invention, the method includes fetching a dyadic DSP instruction having a main operation and a sub operation; predecoding the dyadic DSP instruction to generate predecoded instruction signals; and decoding the predecoded instruction signals to generate select signals to selectively couple data from a first plurality of buses coupled to inputs of multiplexers of a first plurality of DSP functional blocks to execute the main operation of the dyadic DSP instruction in one processor cycle and to selectively couple data from a second plurality of buses coupled to inputs of multiplexers of a second plurality of DSP functional blocks to execute the sub operation of the dyadic DSP instruction in the one processor cycle.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A method of and an apparatus for performing efficient software emulation of a multi-processor target computer by a host computer. The software technique permits multiple processors to be emulated by a single processor. The use of software emulation permits the host computer to execute both host programs and target programs. The software emulation is made particularly efficient by utilizing the operation code combined with a separate four bit field to directly address the corresponding host instructions.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: An apparatus and a system may include a modal property indicator and an access module to receive the modal property indicator and to access a selected location based on a condition of the modal property indicator. An article may include data, which, when accessed, results in a machine performing a method including indicating a processor mode to a memory including a plurality of instructions and predecoding an instruction selected from the plurality of instructions according to the processor mode.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A method and system for calculating a branch target address. Upon fetching a branch instruction from memory, the n?1 lower order bits of the branch target address may be pre-calculated and stored in the branch instruction prior to storing the branch instruction in the instruction cache. Upon retrieving the branch instruction from the instruction cache, the upper order bits of the branch target address may be recovered using the sign bit and the carry bit stored in the branch instruction. The sign bit and the carry bit may be used to select one of three possible upper-order bit value combinations of the branch target address. The selected upper-order bit value combination may then be appended to the n?1 lower order bits of the branch target address to form the complete branch target address.

Abstract: A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of the operation. The status of the condition setting indicator determines whether or not multibit condition codes are set. When they are to be set, they are set depending on the results of carrying out the operation for each lane.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: Binary data is processed and organized by determining patterns specific for the binary data in a software package. Code sections may be split from an instruction according to the code section type or behavior. Certain of these code sections may be organized into specialized ordered lists. Furthermore, some code sections may be abbreviated and sections deleted. Dictionaries are used to store references for or values of the code sections. The processed data may be useful in subsequent compression techniques. In addition, other aspects of the present invention relating to the reducing the size and/or ordering the form of the binary data are described.

Abstract: Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes) singly or in groups in accordance with one or more execution bits set during post-processing in opcodes preceding opcodes to be skipped. Thus portions of an application program which consume excessive power or are unsupported in particular operating environments can be easily and selectively de-activate while maintaining the integrity of the applications program. Local or cache memory is also effectively expanded and processor performance improved by eliminating opcodes from local or cache memory which will not be called.

Abstract: A microprocessor to reduce wasteful power consumption of the floating-point unit. An instruction invalidation logic circuit is utilized to substitute the instruction not-to-use-the-floating-point unit, in the instruction string supplied from the instruction cache, with an invalidating instruction, hold that invalidating instruction in the floating-point register, and supply that invalidating instruction to a floating-point decoder in the floating-point unit. In cases when the invalidating instruction was continuous, the power consumption in the floating-point data path as well as the in the floating-point decoder and floating-point register is reduced.

Abstract: A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed.

Abstract: A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.

Abstract: A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.

Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Abstract: A plurality of fold decoders are each coupled to a different set of successive entries within an instruction fetch buffer stack and check the contents of the successive entries for a variable number of variable-length instructions which may be folded. Folding information for each of the respective set of entries, identifying a number of instructions therein which may be folded (if any) and a size of each instruction which may be folded, is produced by the fold decoders and stored in the first entry of the set, then transmitted to the main decoder for use in folding instructions during decoding.

Abstract: The present invention includes a novel audio recognition peripheral system and method. The audio recognition peripheral system comprises an audio recognition peripheral a programmable processor such as a microprocessor or microcontroller. In one embodiment, the audio recognition peripheral includes a feature extractor and vector processor. The feature extractor receives an audio signal and extracts recognition features. The extracted audio recognition features are transmitted to the programmable processor and processed in accordance with an audio recognition algorithm. During execution of the audio recognition algorithm, the programmable processor signals the audio recognition peripheral to perform vector operations. Thus, computationally intensive recognition operations are advantageously offloaded to the peripheral.

Abstract: Each of registers R0 to R31 is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit 431 outputs information to the selectors 4321 and 4322 on the registers and the locations (upper and lower areas) in which data is written by the instructions that have issued in one cycle. Each of the selectors 4321 and 4322 selects one out of pieces of data that have been output from first, second, and third arithmetic operation units 44, 45, and 46 and writes the selected data in the upper or lower area in one register. A dependency analysis unit 110 in a compiling apparatus considers the upper and lower registers in one 64-bit register as separate resources, analyzes the data dependency relations between the instructions, and generates a dependency graph that indicates the data dependency relations. A instruction rearrangement unit 111 rearranges the instructions and generates execution codes using the dependency graph.

Abstract: A method and system for utilizing bits in a collection of illegal op codes in order to enable pre-decoded instructions to be stored in an instruction cache without increasing the number of bits required to represent the pre-decoded instructions. Upon fetching an instruction from memory, the op code is examined for membership in a collection of illegal op codes. If the instruction op code is a member of this collection, the instruction may be re-encoded to use a different, common illegal op code. If the instruction op code is not a member of the collection of illegal op codes, but is instead an instruction to be stored in the instruction cache in a pre-decoded format, the additional pre-decoded information may be stored in the instruction encoding by utilizing the portion of the op code space which has been vacated by the re-encoding of the illegal op codes.

Abstract: In a conventional information processor that performs speculative execution of a following instruction having a data dependency, since an arithmetic and logical unit is used in performing the speculative execution and the same ALU is used again when the prediction is wrong, the frequency of use of the ALU increases. To prevent this, a history ALU for outputting a past execution result of an instruction, as it is, as an execution result of the instruction and an instruction issue circuit for issuing an instruction whose operand is the same as a past value to the history ALU are provided with an intention of omitting the actual speculative execution. A Guard cache provided in the history cache stores addresses of instructions that give low prediction accuracy, whereby any instruction whose address has been registered in the Guard cache is prevented from being registered again in the history cache.

Abstract: A computer system has a memory which holds a computer program consisting of a sequence of program instructions. The format of the program instructions depends on an instruction mode of the computer system. A decoder is arranged to receive and decode program instructions. A microinstruction generator is responsive to information from the decoder to generate microinstructions according to a predetermined microinstruction format which is independent of the instruction mode of the computer system. The computer system has a plurality of parallel execution units for receiving and executing the microinstructions.

Abstract: The present invention provides a RISC processor with a debug interface unit that enables the external replication of the data processing sequence within a RISC processor for debug purposes. The data exchanged between the sequence controller and the instruction decoder are intermediately stored and forwarded via a free bus line to an interface unit. In the interface unit, the data pending at its inputs are forwarded to defined outputs of the interface. This allows the register contents to be co-read in real time. Accordingly, all the required information to perform an efficient error search are displayed for an outside operator who may then monitor the data processing sequence and conduct an error search.

Abstract: An operation-processing apparatus is equipped with an instruction decoder for decoding an existing instruction and an extension instruction into the same operation code including at least instruction-type-determining bits for determining the existing instruction or the extension instruction, an existing-operation-executing unit for executing an existing operation according to the operation code and outputting an operation-termination-notifying signal, an extension-operation-executing unit that operates in synchronism with the existing-operation-executing unit to thereby execute an extension operation according to the operation code, a control circuit for determining the type of the instruction according to the instruction-type-determining bits, and a multiplexer that, when the type of the instruction has been determined to be the extension instruction and when an operation-termination-notifying signal has been input, selects an extension instruction operated-result data.

Abstract: An apparatus and a system may include a modal property indicator and an access module to receive the modal property indicator and to access a selected location based on a condition of the modal property indicator. An article may include data, which, when accessed, results in a machine performing a method including indicating a processor mode to a memory including a plurality of instructions and predecoding an instruction selected from the plurality of instructions according to the processor mode.

Abstract: A data processing system is provided with a digital signal processor which has an instruction for shifting a source operand in response to a signed shift count value and storing the shifted result in a selected destination register. A first 32-bit operand (600) is treated as a signed shift value that has a sign and a shift count value. A second operand (602) is shifted by an amount according to the shift count value and in a direction according to the sign of the shift count. One instruction is provided that performs a right shift for a positive shift count and a left shift for a negative shift count, and another instruction is provided performs a left shift for a positive shift count and a right shift for a negative shift count. If the shift count value is greater than 31, then the shift is limited to 31.

Abstract: Methods and apparatuses to clear state for operation of a stack. According to one embodiment of the invention, a processor comprises a set of one or more storage areas and a decode unit. The set of one or more storage areas are to store a plurality of tags and a top of stack indication, where each of the plurality of tags is to indicate if a register is in an empty or non-empty state. The decode unit is to decode scalar floating point instructions and packed data instructions, where at least certain of said scalar floating point instructions specify registers in a stack referenced manner and at least certain of said packed data instructions specify registers in a non-stack referenced manner. In addition, the packed data instructions include an instruction to mark the end of blocks of the packed data instructions in programs. The processor also comprises circuitry to cause the plurality of tags to indicate the empty state responsive to execution of the instruction.

Abstract: Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. A single DSP instruction includes a pair of sub-instructions: a primary DSP sub-instruction and a shadow DSP sub-instruction. Both the primary and the shadow DSP sub-instructions are dyadic DSP instructions performing two operations in one instruction cycle. Each signal processing unit of the ASSP includes a primary stage to execute a primary DSP sub-instruction based upon current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based upon delayed data stored locally within registers of the signal processing units. The present invention efficiently executes DSP instructions by simultaneously executing primary DSP sub-instructions (based upon current data) and shadow DSP sub-instructions (based upon delayed locally stored data) with a single DSP instruction.

Abstract: A data processing system is provided with a digital signal processor which has an instruction for saturating multiple fields of a selected set of source operands and storing the separate saturated results in a selected destination register. A first 32-bit operand (600) and a second 32-bit operand (602) are treated as four 16-bit fields and the sixteen bits in each field are saturated separately. Multi-field saturation circuitry is operable to treat a source operand as a number of fields, such that a multi-field saturated (610) result is produced that includes a number of saturated results each corresponding to each field. One instruction is provided which treats an operand pair as having two packed fields, and another instruction is provided that treats the operand pair has having four packed fields. Saturation circuitry is operable to selectively treat a field as either a signed value or an unsigned value.

Abstract: An instruction prefetch buffer is described which has a powersave mechanism. A set of output devices of an instruction supply mechanism each have a stop switch which either pass on a changed bit sequence or the previously supplied bit sequence. If the previously supplied bit sequence is supplied, no power is utilized in that machine cycle.

Abstract: One embodiment of the present invention provides a system for executing variable-size computer instructions, wherein a variable-size computer instruction includes an action component that specifies an operation to be performed and a data component of variable size that specifies data associated with the operation. The system operates by first retrieving the variable-size computer instruction from a computing device's memory. The system then decodes the variable-size computer instruction by separating the variable-size computer instruction into the action component and the data component. Next, the system stores the action component in a first store and the data component in a second store so they can be reused without repeated decoding. Finally, the system provides a first flow path for the action component and a second flow path for the data component.

Abstract: An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load requests out-of-order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out-of-order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: According to the present invention, instruction decoding can be separated into two stages. In a first instruction decoding stage, multiple instructions are decoded in a single machine cycle. Also, in the first instruction decoding stage, when a branch instruction is decoded a memory is requested to read a branch destination instruction for the branch instruction. The instructions decoded in the first instruction decoding stage is stored temporarily in instruction flow registers. In a second instruction decoding stage, instructions read sequentially from the instruction flow registers are decoded.

Abstract: A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an operating mode or modes in which the address size is greater than 32 bits (e.g. up to 64 bits). In some embodiments, the displacement may be limited to less than the address size (e.g. 32 bits, in one implementation) when such operating modes are active. Code density may be higher than if the displacements were expanded, and flexibility in the placement of variables in memory may be achieved. For example, static variables may be placed in memory with flexibility, and IP relative addressing may be used to locate the static variables.

Abstract: A system comprises: a first execution unit, a second execution unit and a third execution unit; a first-in-first-out memory arranged to receive a plurality of instructions for the first to third execution units and to output the instructions to the execution units; a memory store for storing at least one instruction for one of the execution units, the at least one instruction being received from the first-in-first-out memory, the first and second execution units being arranged to receive their instructions from the first-in-first-out memory and the third execution unit being arranged to receive the instructions from the memory store, wherein a given instruction for the third execution unit is available to the third execution unit at substantially the same time that the instruction would be available to the first or second execution unit if that instruction was for the first or second execution unit.

Abstract: A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform addressing operations and assigns those instructions to specialized pipes in a pipeline structure. The invention can assign such instructions to both an execute pipe and a load/store pipe to avoid the occurrence of “bubbles” in the event execution of the instruction requires the calculation capability of the execute pipe. The invention can also examine a sequence of instructions to identify an instruction for performing a calculation where the result of the calculation is used by a succeeding load or store instruction. In this case, the invention controls the pipeline to assure the result of the calculation is available for the succeeding load or store instruction even if both instructions are being processed concurrently.

Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

Abstract: A data processing device capable of high speed operation and shorter instruction processing time without causing software compatibility problems. When storing an instruction from the memory into the instruction cache memory and the instruction possesses a spare field, the instruction code of that instruction is predecoded in the predecode-processor and the information generated is stored in the spare field corresponding area of the instruction cache memory. When that instruction is fetched from the instruction cache memory, the information stored in the spare field corresponding area of the instruction cache memory is utilized. In this way, processing can proceed based on the predecoded information without having to await the completion of decoding of the instruction fetched from the instruction cache memory.

Abstract: A data processing system and method of fetching instructions in a data processing system are described. The data processing system includes at least one execution unit that executes fetched instructions and instruction sequencing logic that fetches instructions from memory. In response to detection of a particular instruction trigger within an instruction stream, the instruction sequencing logic fetches one or more non-sequential blocks of instructions from memory, where each of the non-sequential blocks includes a plurality of instructions.

Abstract: A high cost-performance data processing device and electronic equipment are capable of executing an instruction set including a prefix instruction without increasing the circuit scale. The data processing device of the present invention performs pipeline control and includes a fetch circuit which fetches instruction codes of a plurality of instructions in instruction queues, a prefix instruction decoder circuit which performs a decode processing only on a prefix instruction, the prefix instruction decoder circuit receiving the instruction code before decoding, judging whether or not the instruction is a given prefix instruction, and causing a target instruction modifying information register to store information necessary for decoding a target instruction when the instruction is the given prefix instruction, and a decoder circuit which receives each of the instruction codes of the instructions other than the prefix instruction as a decode instruction and decodes the decode instruction.

Abstract: A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder coupled to the decoder, and operates in parallel with the decoder, determines if subsequent instructions switches the decoder from one mode to the other temporarily or permanently. In particular, the pre-decoder examines at least five Bytecodes concurrently with the decoder decoding a current instruction from a particular instruction set. If the pre-decoder determines that at least one of the five Bytecodes includes a predetermined instruction, the predetermined instruction is skipped and a following instruction is loaded into the decode logic and the decode logic switches from one mode to the other for the decoding of at least the following instruction.

Abstract: An apparatus and method for generating 64 bit displacement and immediate values. In a given processor architecture such as the x86 architecture, instructions may conform to a specified instruction format. The instruction format can include a displacement field and an immediate field. The displacement field can include a displacement value of up to 32 bits and the immediate field can include an immediate value of up to 32 bits. In order to generate 64 bit displacement and immediate values, the 32 bit value from the displacement field of an instruction and the 32 bit value from the immediate field of the instruction may be concatenated to generate a 64 bit concatenated value. The concatenated value may be used by an execution core as a 64 bit displacement or immediate value as specified by the instruction.

Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

Abstract: A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a state vector which includes representation of source and destination registers of instructions within said instruction group and corresponding state vectors for instruction groups of a number of preceding processor cycles.