Abstract: Embodiments of an apparatus, method, and system provide for no-operation instruction (“NOP”) folding such that information regarding the presence of a NOP instruction in the instruction stream is folded into a buffer entry for another instruction. Information regarding a target NOP instruction is thus maintained in a buffer entry associated with an instruction other than the target NOP instruction. For at least one embodiment, NOP information is folded into entries of a re-order buffer.

Abstract: An apparatus and method for performing early correction of a conditional branch instruction in a pipeline microprocessor is disclosed. Early branch correction logic examines early status flags to detect a branch misprediction. The early status flags are generated in response to an instruction preceding the branch instruction earlier in the pipeline than the architected status flags are generated and may or may not be valid. If the early status flags are valid and indicate a misprediction, the early correction logic corrects the misprediction. If the pipeline stages below the early correction logic stage become void of uncompleted flag-modifying instructions, such as after a pipeline flush, the early status flags are re-validated by copying to the architected status flags to the early status flags. Late branch correction logic corrects the misprediction if the architected status flags indicate a misprediction and if the early correction logic did not correct the misprediction.

Abstract: A mechanism processes memory reads and writes in a packet processor. Each memory access has an associated sequence number and information is maintained allowing the detection of memory conflicts. The mechanism is placed between a processing element and a memory system such that write data is buffered and both reads and writes are recorded. When a memory conflict is detected, based on a strict or alternate ordering model, a restart signal is generated and the entries for the associated sequence number are flushed. When the work associated with a sequence number has completed, a signal is made so that associated write data can be sent to the memory system and the entries for that sequence number can be flushed.

Abstract: A data processor includes program registers with individual byte-location write enables. Bypass networks allow a precision pipeline to respond to read requests by accessing a program register or pipeline stage on a byte-by-byte basis. The data processor can thus write to individual byte locations without overwriting other byte locations within the same register. The data processor has an instruction set with instructions that combine two operands and yield a one-byte result that is stored in a specified byte location of a specified result register. Eight instances of this instruction can pack eight results into a single 64-bit result register without additional packing instructions and without using a read port to read the result register before writing to it. As plural functional units can write concurrently to different subwords of the same result register, a system with four functional units can pack eight results into a result register in two instruction cycles.

Abstract: An apparatus and method for generating early status flags in a pipeline microprocessor is disclosed. The apparatus includes early status flag generation logic that receives an instruction, an early result of the instruction, and a valid indicator of the early result and responsively generates the early flags. If the instruction is flag-modifying, then the early status flags are stored in an early flags register. The early flags in the register are invalidated if the early result from which they are generated is invalid. The early status flags and associated valid indicator may be employed by subsequent conditional instructions for early execution to avoid delay in waiting for the architected status flag values to be generated by execution units later in the pipeline. The early flags are revalidated if all flags-modifying instructions in pipeline stages below the early flag generation logic, if any, have already updated the architected status flags.

Abstract: A data processing system for executing a plurality of instructions having a prescribed program order comprises a register file, a reorder buffer, and a plurality of functional units. The register file includes a plurality of registers to store data. The reorder buffer includes N buffer locations of which M buffer locations are bypassable and N?M buffer locations are non-bypassable, wherein N and M are integers and N>M. Each functional unit is capable of executing instructions regardless of the prescribed program order. The reorder buffer temporarily stores data corresponding to the plurality of instructions. When data of one of the plurality of instructions to be executed by a corresponding one of the plurality of functions units is temporarily stored in one of the M bypassable buffer locations, the reorder buffer transfers the data in one of the bypassable M buffer locations to the corresponding one of the functional units in order to execute the instruction.

Abstract: There is disclosed a data processor that uses bypass circuitry to transfer result data from late pipeline stages to earlier pipeline stages in an efficient manner and with a minimum amount of wiring. The data processor comprises: 1) an instruction execution pipeline comprising a) a read stage; b) a write stage; and c) a first execution stage comprising E execution units that produce data results from data operands.

Abstract: A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique and/or processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. A high-level program controlling simulation of a VHDL model of a processor can simulate extension of the completion time of a predetermined instruction in order to hold the instruction in the execution and completion queues, placing an effective hold on the resources allocated for the instruction. Alternatively, the VHDL model may include logic for controlling completion timing of the program instruction by using a processor clock cycle counter. Verification testing of actual processor hardware may be facilitated by including the counter and associated control logic within production or prototype processors.

Abstract: A real-time processor includes a clock register updating a time at a predetermined interval, a time register storing an arbitrary time, a time comparator comparing the time in the clock register with the time stored in the time register, and an instruction processing unit executing an instruction whose execution status is altered according to the comparison result of the time comparator. A predetermined operation can be carried out correctly at a predetermined time since the instruction processing unit executes an instruction whose execution status is altered according to the comparison result of the time comparator.

Abstract: In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.

Abstract: An apparatus for speculatively forwarding storehit data in a microprocessor pipeline. First and second virtual address comparators compare a virtual load address with first and second virtual store addresses to generate a virtual match signal for indicating whether first and second storehit data is likely present in a store buffer and a result forwarding cache, respectively. If the first and second storehit data are both present the second storehit data is newer than the first storehit data. First and second physical address comparators compare a physical load address translated from the virtual load address with first and second physical store addresses translated from the plurality of virtual store addresses to generate a physical match signal for indicating whether the first and second storehit data is certainly present in the store buffer and the result forwarding cache, respectively.

Abstract: Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine The issue engine categorizes operations as at least one of either a speculative operation, which perform computations, or an architectural operation, which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.

Abstract: A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an integer number S of sub-units (541, 542, 543), wherein S is greater than one. Each of the sub-units is operable to execute, during an execution cycle, at least one of the instructions in the instruction set in response to at least two data arguments (A, B). The processor further comprises circuitry (58A1, 58A2, 58A3, 58B1, 58B2) for providing an updated value of the at least two data arguments to less than all S of the sub-units for a single execution cycle.

Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

Abstract: A resource management system and method is disclosed. The resource management system and method enable first and second instructions, each of which requires access to a memory resource, to be processed in an instruction pipeline at the same time. The resource management system and method manage the memory resource to prevent a data hazard based on an order of receipt of a first instruction response and a second instruction response.

Abstract: One embodiment of the present invention provides a system that predicts a result produced by a section of code in order to support speculative program execution. The system begins by executing the section of code using a head thread in order to produce a result. Before the head thread produces the result, the system generates a predicted result to be used in place of the result. Next, the system allows a speculative thread to use the predicted result in speculatively executing subsequent code that follows the section of code. After the head thread finishes executing the section of code, the system determines if a difference between the predicted result and the result generated by the head thread has affected execution of the speculative thread. If so, the system executes the subsequent code again using the result generated by the head thread. If not, the system performs a join operation to merge state associated with the speculative thread with state associated with the head thread.

Abstract: A distributed system is provided for apportioning an instruction stream into multiple segments for processing in multiple parallel processing units, and for merging the processed segments into a single processed instruction stream having the same sequential relative order as the original instruction stream. Tags may be attached to each segment after apportioning to indicate the order in which the various segments are to be merged. In one embodiment, the end of each segment includes a tag indicating the unit to which the next instruction in the original instruction sequence is directed.

Abstract: A method and apparatus for retaining flag values when an associated data value dies. A first storage circuit includes a free list for storing physical register names (PRNs) and indications indicative of whether a physical register associated with a PRN was assigned to store a logical register result and flag results of a first instruction and a logical register result and a subsequent instruction which overwrites the logical register result but not the flags. A second storage circuit stores PRNs separate from the free list. The first and second storage circuits output first and second PRNs to a selection circuit. If the first indication (associated with the first PRN) is in a first state, the selection circuit may provide the first PRN to a mapper for assignment to a logical register. If the first indication is in a second state, the second PRN may be provided to the mapper.

Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.

Abstract: A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill instructions without having to determine whether a remaining portion of the fill instructions will execute without exceptions.

Abstract: The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available.

Abstract: A programmable processor that includes a pipeline with a number of stages. A stall controller is associated with the pipeline, and detects a hazard condition in at least one of those stages. The stall controller produces a set of signals that can control the stages individually, to stall stages of the pipeline in order to avoid a hazard. In an embodiment, a bubble is formed in the pipeline which allows one instruction to complete prior to allowing the pipeline to continue.

Abstract: A processor system and method that reduces the number of register value copying made from alias registers to corresponding real (architectural) registers. One method entails not performing an alias register to real register copying if the incoming instruction does not designate a real register. Another method entails delaying alias register to real register copying until the corresponding reorder buffer (ROB) entry is actually written to. Yet another method entails not performing an alias register to real register copying if the ROB entry is the same as the existing ROB entry. And, still another method entails further delaying or stalling the allocation of an ROB entry.

Abstract: A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill instructions that allow the retirement window to retire a portion of the spill instructions without having to determine whether a remaining portion of the spill instructions will execute without exceptions.

Abstract: A method and apparatus for solving the output dependence problem in an explicit parallelism architecture microprocessor with consideration for implementation of the precise exception. In case of an output dependence hazard, the issue into bypass of a result of the earlier issued operation having an output hazard is cancelled. Latencies of short instructions are aligned by including additional stages on the way of writing the results into the register file in shorter executive units, which allows to save the issue order while writing the results into the register file. For long and unpredictable latencies of the instructions, writing of the result of the earlier issued operation having an output dependence hazard into the register file is cancelled after checking for no precise exception condition. All additional stages are connected to the bypass not to increase the result access time in case of this result use in the following operations.

Abstract: The assignment of an address to a transaction for serialization purposes is disclosed. A simulated address is assigned to a transaction of a first type. The simulated address may be determined by selecting a mask based on one or more bits of a command type attribute of the transaction, and performing a logical OR operation on the highest bits of the mask with a number of bits determined by concatenating various bits of various attributes of the transaction. The lowest bits of the resulting simulated address can be incremented for each transaction assigned a simulated address having the same highest bits. The transaction is serialized relative to other transactions of the first type, such as I/O-related transactions, utilizing a serialization approach for transactions of a second type. The serialization approach may be an existing approach already used to serialize transactions of the second type, such as coherent transactions.

Abstract: An SMT system has a single thread mode and an SMT mode. Instructions are alternately selected from two threads every clock cycle and loaded into the IFAR in a three cycle pipeline of the IFU. If a branch predicted taken instruction is detected in the branch prediction circuit in stage three of the pipeline, then in the single thread mode a calculated address from the branch prediction circuit is loaded into the IFAR on the next clock cycle. If the instruction in the branch prediction circuit detects a branch predicted taken in the SMT mode, then the selected instruction address is loaded into the IFAR on the first clock cycle following branch predicted taken detection. The calculated target address is fed back and loaded into the IFAR in the second clock cycle following branch predicted taken detection. Feedback delay effectively switches the pipeline from three stages to four stages.

Abstract: A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another transaction, such as by evaluating the transaction against a hazard content-addressable memory (CAM). The hazard CAM can enforce various hazard rules, such as considering a transaction as active if it is referencing a memory line and is currently being processed within the pipeline, and ensuring that only one active transaction with a given coherent memory line is in the pipeline at a single time. In response to determining that a transaction is a hazard, the transaction is routed to a hazard queue, such as at the end of the pipeline. Once the hazard is released, the transaction re-enters the pipeline.

Abstract: The present invention, in various embodiments, provides techniques for retiring instructions that typically complete early as compared to most instructions. In a first embodiment, at each stage of the various processing stages, each instruction capable of early retirement is processed in accordance with that stage. At a particular stage, if the instruction meets the criteria for early retirement, then the instruction is terminated, e.g., “retired,” and the system is updated to reflect that the instruction has been terminated. However, if, at that particular stage, the instruction does not meet the criteria for early retirement, then the instruction is processed to the next stage, and it is determined again whether the instruction meets the criteria for early retirement. If the instruction meets the criteria, then the instruction is terminated, or if the instruction does not meet the criteria, then the instruction is processed to the next stage, and so on, until the instruction is retired.

Abstract: A method is provided for use in a processing pipeline operable to dispatch a plurality of instructions up to a first number of instructions per cycle to execution stages of the pipeline. According to such method, a skip instruction is decoded in a first cycle of the processing pipeline to determine a total number of subsequent instructions in the processing pipeline that are to be skipped. The skip instruction is executed in a second cycle. Subsequent instructions in the processing pipeline are prohibited from being executed, including prohibiting execution of a second number of instructions subsequent to the skip instruction in the second cycle, the second number being variable between zero and one less than the first number.

Abstract: Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

Abstract: Multiple register input multiplexors select a respective one of the results generated by operation units, and store the selected results in respective architecture registers as specified by the corresponding instructions (from which the results are generated). A forwarding multiplexor receives the results before the results are provided to the register input multiplexors, and selects one of the results for use as an operand for execution of a dependent instruction. As the forwarding multiplexor receives the results at a point before the inputs of the register input multiplexors, the time duration required to forward the results may be minimized, and a greater instruction throughput performance may be attained in a processor.

Abstract: A mechanism processes memory reads and writes in a packet processor. Each memory access has an associated sequence number and information is maintained allowing the detection of memory conflicts. The mechanism is placed between a processing element and a memory system such that write data is buffered and both reads and writes are recorded. When a memory conflict is detected, based on a strict or alternate ordering model, a restart signal is generated and the entries for the associated sequence number are flushed. When the work associated with a sequence number has completed, a signal is made so that associated write data can be sent to the memory system and the entries for that sequence number can be flushed.

Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or “glitch” will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.

Abstract: A system and method to detect when a page access exception occurs on a subsequent part of a long operand processed out of order before the page is asynchronously marked valid by the operating system where the first request of the operand when later processed out of order after a subsequent buffer found no exception. In this case the instruction that encountered this situation is aborted and is re-executed with no page access exceptions. This prevents reporting improper delayed access exceptions on the operand data.

Abstract: A floating point unit includes floating point processing units for executing floating point instructions that write operands to an external memory and for executing floating point instructions that read operands from the external memory. The floating point also includes an operand queue for storing a plurality of operands associated with one or more operations being processed in the floating point unit. The operand queue stores a first operand written by a floating point write instruction executed by a first one of the plurality of floating point processing units and supplies the first operand to a floating point read instruction executed by a second one of the plurality of floating point processing units when the first operand is committed or virtually committed.

Abstract: A method for stopping replay tornadoes in a processor. The method of one embodiment comprises scheduling an instruction for execution speculatively. A determination is made whether the instruction executed correctly. The instruction is routed to a replay mechanism if the instruction did not execute correctly. A determination is made whether a replay tornado exists. The instruction is routed for re-execution if the instruction executed incorrectly and no replay tornado exists. Breaking the replay tornado if the replay tornado exists. Replay safe instructions in the pipeline are retired. Non-replay safe instructions in the pipeline are marked for re-execution. The non-replay safe instructions are rescheduled for re-execution.

Abstract: The invention provides a processor architecture that bypasses data hazards. The architecture has an array of pipelines and a register file. Each of the pipelines includes an array of execution units. The register file has a first section of n registers (e.g., 128 registers) and a second section of m registers (e.g., 16 registers). A write mux couples speculative data from the execution units to the second set of m registers and non-speculative data from a write-back stage of the execution units to the first section of n registers. A read mux couples the speculative data from the second set of m registers to the execution units to bypass data hazards within the execution units. The register file preferably includes column decode logic for each of the registers in the second section of m registers to architect speculative data without moving data. The decode logic first decodes, and then selects, an age of the producer of the speculative state; the newest producer enables the decode.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: By using an entry number (WRB number) of a re-order buffer 6, each of function units such as an operation unit 3, a store unit 4, a load unit 5, etc. notifies to the re-order buffer 6 the processing end for a instruction stored in the entry concerned in the unit thereof. The load unit 5 manages the latest speculation state of a load instruction issued on the basis of a branch prediction success/failure signal output from the branch unit 2, and makes no notification to the re-order buffer 6 on the basis of WRB number for subsequent load instructions of a branch-prediction failed branch instruction even when the processing of the instruction is finished. Accordingly, the re-order buffer 6 can re-use entries in which the subsequent instructions of the branch prediction failed branch instruction are stored.

Abstract: A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of when floating point addresses are stored.

Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent “pipes” from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the “fpr target”) are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand.

Abstract: A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at least one source register. A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity of the data in a destination register based upon the validity bit in the at least one source register. The processor optionally comprising a checker unit to retire those instructions from the execution unit which write valid data to the destination register, and to re-schedules those instructions for execution which write invalid data to the destination register.

Abstract: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results.

Abstract: Register adjustment is performed based on adjustment values determined at multiple stages within a pipeline of a processor. In one embodiment, a programmable processor is adapted to include a speculative count register. The speculative count register may be loaded with data associated with an instruction before the instruction commits. However, if the instruction is terminated before it commits, the speculative count register may be adjusted. A set of counters may monitor the difference between the speculative count register and its architectural counterpart.

Abstract: A processor system and method that reduces the number of register value copying made from alias registers to corresponding real (architectural) registers. The method entails determining whether to copy the register value generated by executing an instruction from the alias register to the real register at the time the reorder buffer entry associated with the alias register is needed for a new instruction. If before the reorder buffer is needed for a new instruction, an interim instruction resulted in a new register value for the real register, then the original register value would be invalid at the time the reorder buffer entry is needed for the new instruction. Thus, there would not be a need to copy the original register value to the real register. The reduction in copying can make the processor system consume less power.

Abstract: Embodiments are provided in which result forwarding for each execution unit in a processor is implemented for only one operand input of the execution unit. If another non-implemented operand input of the execution unit needs forwarded results, the forwarded results are passed through the implemented operand input. Non-forwarded operands are passed through the non-implemented operand input.

Abstract: In an embodiment, a pipelined processor includes a future file for storing updated data address values generated by a data address generator (DAG). These updated values may be provided to the DAG for subsequent address calculation operations.

Abstract: In an embodiment, a pipelined processor may be adapted to process multi-cycle instructions (MCIs). Results generated in response to non-terminal sub-instructions may be written to a speculative commit register. When the MCI commits, i.e., a terminal sub-instruction reaches the WB stage, the value in the speculative commit register may be written to the architectural register.

Abstract: An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.