Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.

Abstract: Qubit allocation for noisy intermediate-scale quantum computers is provided. A quantum circuit comprises a plurality of logical qubits. A hardware specification comprising a connectivity graph of a plurality of physical qubits. A directed acyclic allocation graph is determined based on the plurality of logical qubits and the connectivity graph. The allocation graph comprises a node for each possible allocation of the plurality of logical qubits to the plurality of physical qubits, each allocation having a fidelity, and a plurality of directed edges, each edge connecting to its corresponding first node from its corresponding second node, the first node corresponding to a first allocation, the second node corresponding to a sub-allocation of the first allocation. The allocation graph is searched for a weighted shortest path from a root node of the allocation graph to a leaf node of the allocation graph. The allocation corresponding to the weighted shortest path is outputted.

Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

Abstract: An apparatus and method are provided for performing bit permutation operations. The apparatus has an interface for receiving an input data operand and a control operand. The input data operand comprises one or more data elements, each data element comprising a plurality of bits, and the control operand provides control information identifying bit permutations required when performing a given bit permutation operation on each data element. The bit permute circuitry treats the input data operand as a plurality of fixed size data portions, each data element comprising one or more of the data portions with the number being dependent on the data element size. The bit permute circuitry performs bit permutation operations on each data portion of the input data operand, using the control information provided for that data portion, generating, for each data portion, at least one intermediate result.

Abstract: Address collisions are managed when performing vector operations. A register store stores vector operands. Execution circuitry performs memory access operations to move the vector operands between the register store and memory and data processing operations using the vector operands. The execution circuitry may iteratively execute a vector loop, where during each iteration the execution circuitry executes a sequence of instructions to implement the vector loop. The sequence includes a check instruction identifying a plurality of memory addresses. The execution circuitry responds to the check instruction to determine whether an address hazard condition exists among the plurality of memory addresses. For each iteration of the vector loop, the execution circuitry responds to the check instruction determining an absence of the hazard address condition to employ a default level of vectorization when executing the sequence of instructions to implement the vector loop.

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

Abstract: An apparatus comprises instruction decoding circuitry to generate micro-operations in response to program instructions; and processing circuitry to perform data processing in response to the micro-operations generated by the instruction decoding circuitry. In response to a predicated vector instruction, the instruction decoding circuitry reads or predicts an estimated value of the predicate value, and depending on the estimated value, varies a composition of at least one micro-operation generated in response to the predicated vector instruction. This can enable more efficient use of hardware resources in the processing circuitry.

Abstract: Among other things, an apparatus comprises quantum units; and couplers among the quantum units. Each coupler is configured to couple a pair of quantum units according to a quantum Hamiltonian characterizing the quantum units and the couplers. The quantum Hamiltonian includes quantum annealer Hamiltonian and a quantum governor Hamiltonian. The quantum annealer Hamiltonian includes information bearing degrees of freedom. The quantum governor Hamiltonian includes non-information bearing degrees of freedom that are engineered to steer the dissipative dynamics of information bearing degrees of freedom.

Abstract: An electronic neuromorphic core processor circuit and related method include a dendrite circuit comprising an input that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit associates the identifier with a set of synaptic connections, possibly shared hierarchically over populations of neurons defined implicitly by the mapping structures, that are read from the memory. The synaptic connections determine n-tuple information comprising a dendrite ID, a weight, and a network delay time. A dendrite accumulator circuit accumulates weight values scheduled at the appropriate future time as identified by the n-tuple information and maps them to a soma compartment.

Abstract: A processor core comprising in its set of instructions, a combined addition and bound-checking instruction (ADDCK) defining an integer n implicitly, or explicitly as a parameter of the instruction; an adder having a width p strictly greater than n bits; and a processing circuit (MUX, 42) designed to respond to the combined instruction by activating an overflow signal (BX) when the adder generates a carry of rank n during the addition of operands of width p.

Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.

Abstract: A video conferencing apparatus includes an acquisition processing portion, a calculation processing portion, and a combining processing portion. The acquisition processing portion acquires site video data that represents site videos captured at a plurality of sites. The calculation processing portion calculates respective display priorities of the sites based on evaluation values for a plurality of predetermined evaluation items. The combining processing portion generates composite video data based on the site video data acquired by the acquisition processing portion, the composite video data representing a composite video which is a combination of a plurality of site videos having display sizes corresponding to the display priorities.

Abstract: Embodiments herein describe a reservation station (RS) in a processor that merges control data from multiple sources into a merged control data value. Before an instruction issues, the RS gathers and saves control data indicating how the instruction is to be executed. This control data may be saved in control registers. An instruction, however, can update many different types of status control bits in these registers. As such, the RS may store different types of control data for an instruction. Instead of the RS containing multiple registers and data paths for every type of control data, the embodiments herein describe merge logic in the RS that permits control data from different sources to be merged into a single control data value. Once the instruction is issued, the RS passes the merged control data value to an execution unit for processing.

Abstract: A machine instruction is provided that has associated therewith a result location to be used for a set operation, a first source, a second source, and an operation select field configured to specify a plurality of selectable operations. The machine instruction is executed, which includes obtaining the first source, the second source, and a selected operation, and performing the selected operation on the first source and the second source to obtain a result in one data type. That result is quantized to a value in a different data type, and the value is placed in the result location.

Abstract: A system includes reception of a query comprising one or more search terms, determination that one of the one or more search terms corresponds to a table column comprising Boolean operators, determination of a value of the table column corresponding to TRUE, and addition of a condition to the query, the condition specifying the value of the table column.

Abstract: An apparatus and method are provided for controlling instruction execution behaviour. The apparatus includes a set of data registers for storing data values, and a set of bounded pointer storage elements, where each bounded pointer storage element stores a pointer having associated range information indicative of an allowable range of addresses when using that pointer. A control storage element stores a current instruction context, and that current instruction context is used to influence the behaviour of at least one instruction executed by processing circuitry, that at least one instruction specifying a pointer reference for a required pointer, where the pointer reference is within at least a first subset of values (in one embodiment the behaviour is influenced irrespective of the value of the required pointer).

Abstract: A receiving device comprises an iterative decoder, a first determination unit and a control unit. The iterative decoder is for receiving at least one coded signal and for performing an iterative decoding on the at least one coded signal, to generate a plurality of decoded signals, wherein the plurality of decoded signals comprise a first decoded signal from a first iteration, a second decoded signal from a second iteration and a third decoded signal from a third iteration. The first determination unit is for determining whether the plurality of decoded signals diverge, to generate a first determination result. The control unit is for generating a control signal according to at least the first determination result, wherein the control signal indicates the iterative decoder whether to stop performing the iterative decoding on the at least one coded signal.

Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

Abstract: A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.

Abstract: Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.

Abstract: A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.

Abstract: Embodiments are directed to techniques for allowing write operations to proceed on units smaller than a block. Merely decreasing the block size is not desirable, however, since many files are written in large chunks at once, and larger block sizes can increase speed and decrease the amount of overhead metadata required. Therefore, in order to maintain large block sizes while still obtaining the benefit of being able to make small writes when necessary, blocks may be divided into sub-blocks. Unaligned writes that do not fill up an entire block may be segregated and stored separately from aligned writes, the unaligned writes having finer granularity. These techniques may result in faster operation for unaligned writes. They also especially benefit systems using compression because they allow efficiently partially overwriting compressed blocks.

Abstract: The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication.

Abstract: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the rotated elements in the second operand replaces the corresponding bit in a first operand of the instruction.

Abstract: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the rotated elements in the second operand replaces the corresponding bit in a first operand of the instruction.

Abstract: Embodiments relate to program structure-based blocking. An aspect includes receiving source code corresponding to a computer program by a compiler of a computer system. Another aspect includes determining a prefetching section in the source code by a marking module of the compiler. Yet another aspect includes performing, by a blocking module of the compiler, blocking of instructions located in the prefetching section into instruction blocks, such that the instruction blocks of the prefetching section only contain instructions that are located in the prefetching section.

Abstract: A method, computer system and computer program for optimizing the processing of a character string during execution of the program by using characteristic information that indicates a characteristic of the character string and is associated with the character string. The method includes the steps of determining, on the basis of a characteristic of a first character string and operation for the first character string, a characteristic information of at least one of the first character string and a second character string obtained as a result of the operation, and associating the characteristic information with the at least one character string.

Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

Abstract: An apparatus and method are described for shuffling data elements from source registers to a destination register.

Abstract: A digital processor for recovering a source bitstream from an encoded bitstream that has been encoded according to a context adaptive binary arithmetic coding (CABAC) algorithm. The processor includes a first execution unit and a second execution unit. The first execution unit generates first execution data by operating on a first register and a second register, and stores the first execution data in the first register. The first execution data includes a current output bit, a temporary range value and a temporary offset value. The current output bit corresponds to a bit of the source bitstream. The second execution unit generates second execution data by operating on the first register and the second register, and stores the second execution data in the second register. The second execution data includes a normalized range value and a normalized offset value.

Abstract: Methods of bit manipulation within a computer processor are disclosed. Improved flexibility in bit manipulation proves helpful in computing elementary functions critical to the performance of many programs and for other applications. In one embodiment, a unit of input data is shifted/rotated and multiple non-contiguous bit fields from the unit of input data are inserted in an output register. In another embodiment, one of two units of input data is optionally shifted or rotated, the two units of input data are partitioned into a plurality of bit fields, bitwise operations are performed on each bit field, and pairs of bit fields are combined with either an AND or an OR bitwise operation. Embodiments are also disclosed to simultaneously perform these processes on multiple units and pairs of units of input data in a Single Input, Multiple Data processing environment capable of performing logical operations on floating point data.

Abstract: Methods of bit manipulation within a computer processor are disclosed. Improved flexibility in bit manipulation proves helpful in computing elementary functions critical to the performance of many programs and for other applications. In one embodiment, a unit of input data is shifted/rotated and multiple non-contiguous bit fields from the unit of input data are inserted in an output register. In another embodiment, one of two units of input data is optionally shifted or rotated, the two units of input data are partitioned into a plurality of bit fields, bitwise operations are performed on each bit field, and pairs of bit fields are combined with either an AND or an OR bitwise operation. Embodiments are also disclosed to simultaneously perform these processes on multiple units and pairs of units of input data in a Single Input, Multiple Data processing environment capable of performing logical operations on floating point data.

Abstract: A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.

Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

Abstract: System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step, applicant's invention significantly enhances the efficiency of the conversion process. In one embodiment, a file system or storage system provides indirections to locations of data elements stored on a persistent storage media. A source virtual machine file includes hypervisor metadata (HM) data elements in one hypervisor file format, and virtual machine payload (VMP) data elements.

Abstract: A method, computer program product, and computing system for receiving a reservation for a LUN from Host A, wherein the LUN is defined within a data array. A lock for the LUN is defined as Host A. A write request is received for the LUN from Host B. The lock for the LUN is defined as Transitioning A to B. The write request is delayed for a defined period of time.

Abstract: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.

Abstract: A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a throttle disable signal. A downstream valid signal is generated by the first pipeline stage based on an upstream valid signal and the delayed ready signal. An upstream ready signal is generated by the first pipeline stage based on the delayed ready signal and the downstream valid signal.

Abstract: An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.

Abstract: A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.

Abstract: Systems and methods allow formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor). In a first stage, sets of connected subgraphs are successively generated, each set including a respective subgraph for each decision variable in the problem graph, adjacent decisions variables in the problem graph mapped to respective vertices in the hardware graph, the respective vertices which are connected by at least one respective edge in the hardware graph. In a second stage, the connected subgraphs are refined such that no vertex represents more than a single decision variable.

Abstract: A virtual parallel computing system and method represents bits with matrices and computes over all input states in parallel through a sequence of matrix operations. The matrix operations relate to logic gate operators to carry out a function implementation that represents a problem to be solved. Initial matrices are prepared to encode the weights of all input states, which can be binary states. Intermediate results can be simplified to decrease computational complexity while maintaining useful approximation results. The final matrices can encode the answer(s) to the problem represented by the function implementation. The system and method are particularly useful in speeding up database searches and in counting solutions of satisfiability problems.

Abstract: Reading a value into a register, checking to see if the value is a NULL, and then jumping out of a loop if the value is a NULL is a common task that processors perform. To speed performance of such a task, a novel “blank bit” is added to the flag register of a processor. When a first instruction (arithmetic, logic or load) is executed, the instruction operands are checked to see if any is a NULL character value. Information on the result of the check is stored in the blank bit. Execution of a second instruction uses the information stored in the blank bit to determine whether or not a second operation (for example, a jump) will be performed. By using the first and second instructions in a loop, the number of instructions executed to check for NULLs at the end of strings and arrays is reduced.

Abstract: A device employing techniques to optimize Context-based Adaptive Binary Arithmetic Coding (CABAC) for the H.264 video decoding is provided. The device includes a processing circuit operative to implement a set of instructions to decode multiple bins simultaneously and renormalize an offset register and a range register after the multiple bins are decoded. The range register and offset registers may be 32 or 64 bits. The use of a larger range register allows renormalization to be skipped when enough bits are still in the range register.

Abstract: Embodiments of systems, apparatuses, and methods for counting instructions of a particular type are described herein. In some embodiments, a processor includes a plurality of write mask registers, logic to determine write mask register usage of an instruction in a particular manner and a counter to count a number of instances of instructions that have been determined to use a write mask register in the particular manner.

Abstract: A method, computer program product, and system are provided for multi-input bitwise logical operations. The method includes the steps of receiving a multi-input bitwise logical operation instruction that specifies two or more input operands and a function operand, where a first input operand of the two or more input operands comprises a number of bits, each bit having a corresponding bit in each of the additional input operands in the two or more input operands. The function operand is written to a lookup table. Then, the lookup table is accessed for each set of corresponding input operand bits in the two or more input operands to generate an output for the multi-input bitwise logical operation instruction.

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.